verilog/rtl/softshell/third_party/wb2axip/doc/gfx/aximwr2wbsp-single.json

{signal: [
  {name: 'S_AXI_ACLK',   wave: 'p........'},
  {name: 'S_AXI_ARESETN',wave: '01.......'},
  {},
  {name: 'S_AXI_AWVALID',wave: '0.1....0.'},
  {name: 'S_AXI_AWREADY',wave: '01...01..'},
  {name: 'S_AXI_AWID',   wave: 'x.2..6.x.', data: ['2','3']},
  {name: 'S_AXI_AWADDR', wave: 'x.3456.x.', data: ['A0','A1','A2','A3']},
  {name: 'S_AXI_AWLEN',  wave: 'x.3456.x.', data: ['0','0','0','0']},
  {},
  {name: 'S_AXI_WVALID', wave: '0.1..010.'},
  {name: 'S_AXI_WREADY', wave: '01.......'},
  {name: 'S_AXI_WDATA',  wave: 'x.345x6x.', data: ['D0','D1','D2','D3','D4','D5']},
  {name: 'S_AXI_WLAST',  wave: 'x.1..x1x.', data: ['0']},
  {},
  {name: 'o_wb_stb',  wave: '0..1..01.'},
  {name: 'o_wb_addr', wave: 'x..345.6.', data: ['A0','A1','A2','A3']},
  {name: 'o_wb_data', wave: 'x..345x6x', data: ['D0','D1','D2','D3','D4','D5']},
  {name: 'i_wb_stall',wave: '0......1.'},
  {name: 'i_wb_ack',  wave: '0..1..0.1'},
  {},
  {name: 'S_AXI_BVALID', wave: '0.....345'},
  {name: 'S_AXI_BREADY', wave: 'x.....1..'},
  {name: 'S_AXI_BID',    wave: 'x.....2..', data: ['2']},
]}