verilog/rtl/softshell/third_party/wb2axip/doc/gfx/aximrd2wbsp.json

{signal: [
  {name: 'S_AXI_ACLK',    wave: 'P..........'},
  {name: 'S_AXI_ARESETN', wave: '01.........'},
  {},
  {name: 'S_AXI_ARVALID', wave: '0.1....0...', data:[]},
  {name: 'S_AXI_ARREADY', wave: '01.0101....', data:[]},
  {name: 'S_AXI_ARID',    wave: 'x.3.4.5x...', data:['I0','I1','I2']},
  {name: 'S_AXI_ARADDR',  wave: 'x.3.4.5x...', data:['A0','A1','A2']},
  {name: 'S_AXI_ARLEN',   wave: 'x.3.4.5x...', data:['1','1','1']},
  {},
  {name: 'o_cyc',         wave: 'x0.1.....0.', data:['A0']},
  {name: 'o_stb',         wave: 'x0.1.....0.', data:['A0']},
  {name: 'o_addr',        wave: 'x0.3344550.', data:['A0','','A1','','A2']},
  {name: 'i_ack',         wave: 'x0.1.....0.'},
  {name: 'i_data',        wave: 'x..3344550.', data:['D0','D1','D2','D3','D4','D5']},
  {},
  {name: 'S_AXI_RVALID',  wave: '0...1.....0'},
  {name: 'S_AXI_RREADY',  wave: 'x1.........'},
  {name: 'S_AXI_RID',     wave: 'x...3.4.5.x', data:['I0','I1','I2']},
  {name: 'S_AXI_RDATA',   wave: 'x...334455x', data:['D0','D1','D2','D3','D4','D5']},
  {name: 'S_AXI_RLAST',   wave: 'x...010101x'},
]}