verilog/rtl/softshell/third_party/wb2axip/doc/gfx/axifull-rdwr.json

{signal: [
  {name: 'S_AXI_ACLK',    wave: 'p...............'},
  {name: 'S_AXI_ARESETN', wave: '01..............'},
  {name: 'S_AXI_ARVALID', wave: '0.1.0...........'},
  {name: 'S_AXI_ARREADY', wave: '0..10...........'},
  {name: 'S_AXI_ARLEN',   wave: 'x..2x...........', data: ['2']},
  {name: 'S_AXI_RVALID',  wave: '0...304050......'},
  {name: 'S_AXI_RREADY',  wave: 'x...1....x......'},
  {name: 'S_AXI_RLAST',   wave: '0.......10......'},
  {},
  {name: 'S_AXI_AWVALID', wave: '0.....1....0....'},
  {name: 'S_AXI_AWREADY', wave: '0.........10....'},
  {name: 'S_AXI_AWLEN',   wave: 'x.........2x....', data: ['2']},
  {name: 'S_AXI_WVALID',  wave: '0.........1...0.'},
  {name: 'S_AXI_WREADY',  wave: '0..........1..0.'},
  {name: 'S_AXI_WDATA',   wave: '0..........3450.'},
  {name: 'S_AXI_WLAST',   wave: '0............10.'},
  {name: 'S_AXI_BVALID',  wave: '0.............10'},
  {},
]}