verilog/rtl/softshell/third_party/wb2axip/doc/gfx/axifull-rdid.json

{signal: [
  {name: 'S_AXI_ACLK',    wave: 'P....'},
  {name: 'S_AXI_ARESETN', wave: '01...'},
  {name: 'S_AXI_ARVALID', wave: '0.10.'},
  {name: 'S_AXI_ARREADY', wave: '0.10.'},
  {name: 'S_AXI_ARLEN',   wave: 'x.2x.', data: ['0']},
  {name: 'S_AXI_ARID',    wave: 'x.23x', data: ['0','1']},
  {},
  {name: 'S_AXI_RVALID',  wave: '0..10'},
  {name: 'S_AXI_RLAST',   wave: 'x..1x'},
  {name: 'S_AXI_RID',     wave: 'x.23x', data: ['0','1']},
]}