verilog/rtl/softshell/third_party/wb2axip/doc/gfx/axidouble-write.json

{signal: [
  {name: 'S_AXI_ACLK',    wave: 'p...................'},
  {name: 'S_AXI_ARESETN', wave: '01..................', data: ['B7','B6','B5 ...']},
  {},
  {name: 'S_AXI_ARVALID', wave: '0.1x..1x..10........'},
  {name: 'S_AXI_ARREADY', wave: '1..0..10..10........'},
  {name: 'S_AXI_ARLEN',   wave: 'x.2x..3x..4x........', data: ['3','3','3','3','3']},
  {name: 'S_AXI_ARADDR',  wave: 'x.2x..3x..4x........', data: ['A0','A1','A2','A3','A4']},
  {},
  {name: 'S_AXI_RVALID',  wave: '0.....1...........0.'},
  {name: 'S_AXI_RREADY',  wave: 'x.....1...........x.'},
  {name: 'S_AXI_RDATA',   wave: 'x.....2222333344440.', data: ['D0','','','','D1','','','','D2','','','','D3','','','']},
  {name: 'S_AXI_RLAST',   wave: 'x0.......20..30..40.'},
  {},
  {name: 'M_AXI_ARVALID', wave: '0..2...3...4...0....', data: ['S0','S1','S2']},
  {name: '(M_AXI_RVALID)',wave: 'x...1...........0...'},
  {name: 'M_AXI_RDATA',   wave: 'x...2222333344440...', data: ['D0','','','','D1','','','','D2','','','','D3','','','']},
  {},
]}