verilog/rtl/softshell/third_party/wb2axip/doc/gfx/axidma.json

{signal: [
  {name: 'S_AXI_ACLK',    wave: 'p.............................'},
  {name: 'S_AXI_ARESETN', wave: '01............................'},
  {},
  {name: 'S_AXIL_AWVALID',wave: '0.1...0.......................'},
  {name: 'S_AXIL_WVALID', wave: '0.1...0.......................'},
  {name: 'S_AXIL_AWADDR', wave: 'x.3456x.......................', data: ['LEN','DST','SRC','GO']},
  {},
  {name: 'M_AXI_ARVALID',wave: '0......1010...........10......'},
  {name: 'M_AXI_ARADDR', wave: 'x......3x5x...........3x......', data: ['A0','A2','AA','A3']},
  {name: 'M_AXI_ARLEN',  wave: 'x......3x5x...........3x......', data: ['1','7','0']},
  {},
  {name: 'M_AXI_RVALID', wave: '0.......1.........0.....10....'},
  {name: 'M_AXI_RDATA',  wave: 'x.......3456734567x.....3x....', data: ['D0','D1','D2','D3','D4','D5','D6','D7','D8','D9','DA','DB']},
  {name: 'M_AXI_RLAST',  wave: 'x.......010......1x.....1x....', data: ['0']},
  {},
  {name: 'M_AXI_AWVALID',wave: '0.........10......10......10..'},
  {name: 'M_AXI_AWADDR', wave: 'x.........3x......4x......7x..', data: ['a0','a1','a9','a3']},
  {name: 'M_AXI_AWLEN',  wave: 'x.........3x......4x......7x..', data: ['0','7','1','0']},
  {},
  {name: 'M_AXI_WVALID', wave: '0.........10......1.........0.'},
  {name: 'M_AXI_WDATA',  wave: 'x.........3x......4567345673x.', data: ['D0','D1','D2','D3','D4','D5','D6','D7','D8','D9','DA','DB']},
  {name: 'M_AXI_WLAST',  wave: 'x.........1x......0......101x.', data: ['0']},
  {},
  {name: 'S_AXI_BVALID', wave: '0..........30.............4070'},
  {},
  {name: 'fifo_fill',    wave: 'x2.......34.5673456345673.452.', data: ['0','1','2','3','4','5','6','7','8','9','8','7','6','5','4','3','2','1','0']},
  {name: 'r_busy',       wave: '0.....1.....................0.'},
  {name: 'o_int',        wave: '0...........................10'},
]}