| diff --git a/config/default.config b/config/default.config |
| index b671223..c0b2bb4 100644 |
| --- a/config/default.config |
| +++ b/config/default.config |
| @@ -1,18 +1,18 @@ |
| torture.generator.nseqs 1000 |
| torture.generator.memsize 1024 |
| torture.generator.fprnd 0 |
| -torture.generator.amo true |
| +torture.generator.amo false |
| torture.generator.mul true |
| torture.generator.divider true |
| torture.generator.run_twice true |
| |
| torture.generator.mix.xmem 10 |
| torture.generator.mix.xbranch 20 |
| -torture.generator.mix.xalu 50 |
| -torture.generator.mix.fgen 10 |
| -torture.generator.mix.fpmem 5 |
| -torture.generator.mix.fax 3 |
| -torture.generator.mix.fdiv 2 |
| +torture.generator.mix.xalu 70 |
| +torture.generator.mix.fgen 0 |
| +torture.generator.mix.fpmem 0 |
| +torture.generator.mix.fax 0 |
| +torture.generator.mix.fdiv 0 |
| torture.generator.mix.vec 0 |
| |
| torture.generator.vec.vf 1 |
| diff --git a/generator/src/main/scala/HWRegPool.scala b/generator/src/main/scala/HWRegPool.scala |
| index de2ad8d..864bcc4 100644 |
| --- a/generator/src/main/scala/HWRegPool.scala |
| +++ b/generator/src/main/scala/HWRegPool.scala |
| @@ -86,7 +86,7 @@ trait PoolsMaster extends HWRegPool |
| |
| class XRegsPool extends ScalarRegPool |
| { |
| - val (name, regname, ldinst, stinst) = ("xreg", "reg_x", "ld", "sd") |
| + val (name, regname, ldinst, stinst) = ("xreg", "reg_x", "lw", "sw") |
| |
| hwregs += new HWReg("x0", true, false) |
| for (i <- 1 to 31) |
| diff --git a/generator/src/main/scala/Prog.scala b/generator/src/main/scala/Prog.scala |
| index 6fb49e2..685c2f8 100644 |
| --- a/generator/src/main/scala/Prog.scala |
| +++ b/generator/src/main/scala/Prog.scala |
| @@ -385,7 +385,7 @@ class Prog(memsize: Int, veccfg: Map[String,String], run_twice: Boolean) |
| "\n" + |
| (if (using_vec) "RVTEST_RV64UV\n" |
| else if (using_fpu) "RVTEST_RV64UF\n" |
| - else "RVTEST_RV64U\n") + |
| + else "RVTEST_RV32U\n") + |
| "RVTEST_CODE_BEGIN\n" + |
| (if (using_vec) init_vector() else "") + |
| "\n" + |
| diff --git a/generator/src/main/scala/Rand.scala b/generator/src/main/scala/Rand.scala |
| index a677d2d..ec0745f 100644 |
| --- a/generator/src/main/scala/Rand.scala |
| +++ b/generator/src/main/scala/Rand.scala |
| @@ -15,7 +15,7 @@ object Rand |
| low + Random.nextInt(span) |
| } |
| |
| - def rand_shamt() = rand_range(0, 63) |
| + def rand_shamt() = rand_range(0, 31) |
| def rand_shamtw() = rand_range(0, 31) |
| def rand_seglen() = rand_range(0, 7) |
| def rand_imm() = rand_range(-2048, 2047) |
| diff --git a/generator/src/main/scala/SeqALU.scala b/generator/src/main/scala/SeqALU.scala |
| index a1f27a5..18d6d7b 100644 |
| --- a/generator/src/main/scala/SeqALU.scala |
| +++ b/generator/src/main/scala/SeqALU.scala |
| @@ -68,17 +68,12 @@ class SeqALU(xregs: HWRegPool, use_mul: Boolean, use_div: Boolean) extends InstS |
| candidates += seq_src1_immfn(SRAI, rand_shamt) |
| candidates += seq_src1_immfn(ORI, rand_imm) |
| candidates += seq_src1_immfn(ANDI, rand_imm) |
| - candidates += seq_src1_immfn(ADDIW, rand_imm) |
| - candidates += seq_src1_immfn(SLLIW, rand_shamtw) |
| - candidates += seq_src1_immfn(SRLIW, rand_shamtw) |
| - candidates += seq_src1_immfn(SRAIW, rand_shamtw) |
| |
| val oplist = new ArrayBuffer[Opcode] |
| |
| oplist += (ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND) |
| - oplist += (ADDW, SUBW, SLLW, SRLW, SRAW) |
| - if (use_mul) oplist += (MUL, MULH, MULHSU, MULHU, MULW) |
| - if (use_div) oplist += (DIV, DIVU, REM, REMU, DIVW, DIVUW, REMW, REMUW) |
| + if (use_mul) oplist += (MUL, MULH, MULHSU, MULHU) |
| + if (use_div) oplist += (DIV, DIVU, REM, REMU) |
| |
| for (op <- oplist) |
| { |
| diff --git a/generator/src/main/scala/SeqBranch.scala b/generator/src/main/scala/SeqBranch.scala |
| index bba9895..0d257d7 100644 |
| --- a/generator/src/main/scala/SeqBranch.scala |
| +++ b/generator/src/main/scala/SeqBranch.scala |
| @@ -75,7 +75,7 @@ class SeqBranch(xregs: HWRegPool) extends InstSeq |
| val reg_mask = reg_write_visible(xregs) |
| |
| insts += ADDI(reg_one, reg_read_zero(xregs), Imm(1)) |
| - insts += SLL(reg_one, reg_one, Imm(63)) |
| + insts += SLL(reg_one, reg_one, Imm(31)) |
| insts += ADDI(reg_mask, reg_read_zero(xregs), Imm(-1)) |
| insts += XOR(reg_mask, reg_mask, reg_one) |
| insts += AND(reg_dst1, reg_src, reg_mask) |
| @@ -95,7 +95,7 @@ class SeqBranch(xregs: HWRegPool) extends InstSeq |
| val reg_mask = reg_write_visible(xregs) |
| |
| insts += ADDI(reg_one, reg_read_zero(xregs), Imm(1)) |
| - insts += SLL(reg_one, reg_one, Imm(63)) |
| + insts += SLL(reg_one, reg_one, Imm(31)) |
| insts += ADDI(reg_mask, reg_read_zero(xregs), Imm(-1)) |
| insts += XOR(reg_mask, reg_mask, reg_one) |
| insts += AND(reg_dst1, reg_src1, reg_mask) |
| diff --git a/generator/src/main/scala/SeqMem.scala b/generator/src/main/scala/SeqMem.scala |
| index 3c180ed..89200f6 100644 |
| --- a/generator/src/main/scala/SeqMem.scala |
| +++ b/generator/src/main/scala/SeqMem.scala |
| @@ -51,7 +51,7 @@ class SeqMem(xregs: HWRegPool, mem: Mem, use_amo: Boolean) extends InstSeq |
| |
| def getRandOpAndAddr (dw_addr: Int, is_store: Boolean): (Opcode, Int) = |
| { |
| - val typ = AccessType.values.toIndexedSeq(rand_range(0,6)) |
| + val typ = AccessType.values.toIndexedSeq(rand_range(0,4)) |
| if (is_store) |
| { |
| if (typ == byte || typ ==ubyte) (SB, dw_addr + rand_addr_b(8)) |
| @@ -110,13 +110,10 @@ class SeqMem(xregs: HWRegPool, mem: Mem, use_amo: Boolean) extends InstSeq |
| candidates += seq_load_addrfn(LH, rand_addr_h) |
| candidates += seq_load_addrfn(LHU, rand_addr_h) |
| candidates += seq_load_addrfn(LW, rand_addr_w) |
| - candidates += seq_load_addrfn(LWU, rand_addr_w) |
| - candidates += seq_load_addrfn(LD, rand_addr_d) |
| |
| candidates += seq_store_addrfn(SB, rand_addr_b) |
| candidates += seq_store_addrfn(SH, rand_addr_h) |
| candidates += seq_store_addrfn(SW, rand_addr_w) |
| - candidates += seq_store_addrfn(SD, rand_addr_d) |
| |
| if (use_amo) |
| { |