add default nettype none
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 9ce690a..a423124 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,3 +1,4 @@
+`default_nettype none
 `ifndef TOP_ROUTING 
 	`define USER1_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\