add default nettype none
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index d6d2d33..c6af2a6 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -1,3 +1,4 @@
+`default_nettype none
`ifndef USE_CUSTOM_DFFRAM
module DFFRAM(
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index 1b88ef7..712a253 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
Building blocks for DFF based RAM compiler for SKY130A
BYTE : 8 memory cells used as a building block for WORD module
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 24a2f3f..784fdae 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*--------------------------------------------------------------*/
/* caravel, a project harness for the Google/SkyWater sky130 */
/* fabrication process and open source PDK */
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index 1b1555f..aa49d6f 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -1,3 +1,4 @@
+`default_nettype none
// This routine synchronizes the
module caravel_clocking(
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 36b08df..2a2bea7 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,3 +1,4 @@
+`default_nettype none
module chip_io(
// Package Pins
inout vddio, // Common padframe/ESD supply
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 01d03a8..54bf194 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Integer-N clock divider */
module clock_div #(
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index cac5141..c7d53f3 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Convert the standard set of GPIO signals: input, output, output_enb,
* pullup, and pulldown into the set needed by the s8 GPIO pads:
* input, output, output_enb, input_enb, mode. Note that dm[2] on
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index 76db8b9..b66ee6b 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Simple 32-bit counter-timer for Caravel. */
/* Counter acts as high 32 bits of a 64-bit counter
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index b9e1191..f0505a7 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Simple 32-bit counter-timer for Caravel. */
/* Counter acts as low 32 bits of a 64-bit counter
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 7233b8a..1aec155 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -1,3 +1,4 @@
+`default_nettype none
// Global parameters
`define MPRJ_IO_PADS 38
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 06ceaf9..dac708a 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -1,3 +1,4 @@
+`default_nettype none
// Digital PLL (ring oscillator + controller)
// Technically this is a frequency locked loop, not a phase locked loop.
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index d4f7a4c..1437c93 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -1,3 +1,4 @@
+`default_nettype none
// (True) digital PLL
//
// Output goes to a trimmable ring oscillator (see documentation).
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index bca5aa3..ed3d531 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
*---------------------------------------------------------------------
* See gpio_control_block for description. This module is like
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index e4e92e9..77d1f3a 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
module gpio_wb # (
parameter BASE_ADR = 32'h 2100_0000,
parameter GPIO_DATA = 8'h 00,
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index cc8d5d0..bd09dcb 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -1,3 +1,4 @@
+`default_nettype none
//-------------------------------------
// SPI controller for Caravel (PicoSoC)
//-------------------------------------
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index 68e0cc0..9b963af 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
module la_wb # (
parameter BASE_ADR = 32'h 2200_0000,
parameter LA_DATA_0 = 8'h00,
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 8688f9a..55f9eef 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
module mem_wb (
`ifdef USE_POWER_PINS
input VPWR,
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 50043c4..21e36dc 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,3 +1,4 @@
+`default_nettype none
module mgmt_core (
`ifdef USE_POWER_PINS
inout vdd1v8,
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 4dcf111..f8fe7fb 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*----------------------------------------------------------------------*/
/* Buffers protecting the management region from the user region. */
/* This mainly consists of tristate buffers that are enabled by a */
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index df81c2c..8d3e1f7 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index e70ac93..6b17fe2 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -1,3 +1,4 @@
+`default_nettype none
module mprj_ctrl_wb #(
parameter BASE_ADR = 32'h 2300_0000,
parameter XFER = 8'h 00,
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 5bc4483..11a7dc3 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,3 +1,4 @@
+`default_nettype none
module mprj_io #(
parameter AREA1PADS = 18 // Highest numbered pad in area 1
) (
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 9ce690a..a423124 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,3 +1,4 @@
+`default_nettype none
`ifndef TOP_ROUTING
`define USER1_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
diff --git a/verilog/rtl/picorv32.v b/verilog/rtl/picorv32.v
index cbbbb60..60dea84 100644
--- a/verilog/rtl/picorv32.v
+++ b/verilog/rtl/picorv32.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 9bf6252..719da6e 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -1,3 +1,4 @@
+`default_nettype none
// Tunable ring oscillator---synthesizable (physical) version.
//
// NOTE: This netlist cannot be simulated correctly due to lack
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index f308fbf..2c51e9a 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -1,3 +1,4 @@
+`default_nettype none
`timescale 1 ns / 1 ps
module simple_por(
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index 447f0f1..8a81954 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -1,3 +1,4 @@
+`default_nettype none
//----------------------------------------------------------------------------
// Module: simple_spi_master
//
diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 54a3cb4..62a3ea6 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index 074fff7..a982981 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index 67f6baa..cf0489d 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -1,3 +1,4 @@
+`default_nettype none
// OpenRAM SRAM model
// Words: 256
// Word size: 32
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index e16ab5e..fe0eae7 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -1,3 +1,4 @@
+`default_nettype none
module storage (
// MGMT_AREA R/W Interface
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index aabcc36..ddce210 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
module storage_bridge_wb (
// MGMT_AREA R/W WB Interface
input wb_clk_i,
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 6c2d376..8a0ac42 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -1,3 +1,4 @@
+`default_nettype none
module sysctrl_wb #(
parameter BASE_ADR = 32'h2F00_0000,
parameter PWRGOOD = 8'h00,
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 5133605..d3186c1 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -1,3 +1,4 @@
+`default_nettype none
// This module represents an unprogrammed mask revision
// block that is configured with via programming on the
// chip top level. This value is passed to the block as
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index f1feed5..6c1c117 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
*-------------------------------------------------------------
*
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 488e4cc..549353e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,3 +1,4 @@
+`default_nettype none
/*
*-------------------------------------------------------------
*
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 1397cd4..7d9ddb1 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -1,3 +1,4 @@
+`default_nettype none
module wb_intercon #(
parameter DW = 32, // Data Width
parameter AW = 32, // Address Width
