| ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/vdp_lite_user_proj,vdp_lite_user_proj,17-12_05-51,0h22m44s,1.54,15438.311688311687,30876.623376623374,-1,1165.7,23775,0,0,0,0,0,0,0,3,0,1364741,206644,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1090431818,0.0,21.18,16.67,0.97,0.0,-1,24299,24887,4557,5145,0,0,0,23775,90,213,90,45,923,120,31,8024,3818,3775,18,792,19500,0,20292,25.641025641025642,39.0,39,2,5,50,1,153.6,153.18,0.28,0,sky130_fd_sc_hd,8,0 |
