Add current gl user_project_wrapper.v

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index fdab7b5..9828a82 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,6 +1,6 @@
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
-module user_project_wrapper(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_sel_i, wbs_dat_i, wbs_adr_i, wbs_ack_o, wbs_dat_o, la_data_in, la_data_out, la_oen, io_in, io_out, io_oeb, analog_io, user_clock2);
+module user_project_wrapper(user_clock2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, vccd1, vssd1, vccd2, vssd2, vdda1, vssa1, vdda2, vssa2, analog_io, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
   inout [30:0] analog_io;
   input [37:0] io_in;
   output [37:0] io_oeb;
@@ -9,6 +9,14 @@
   output [127:0] la_data_out;
   input [127:0] la_oen;
   input user_clock2;
+  input vccd1;
+  input vccd2;
+  input vdda1;
+  input vdda2;
+  input vssa1;
+  input vssa2;
+  input vssd1;
+  input vssd2;
   input wb_clk_i;
   input wb_rst_i;
   output wbs_ack_o;
@@ -20,6 +28,8 @@
   input wbs_stb_i;
   input wbs_we_i;
   vdp_lite_user_proj mprj (
+    .VGND(vssd1),
+    .VPWR(vccd1),
     .io_in(io_in),
     .io_oeb(io_oeb),
     .io_out(io_out),