Update configs
diff --git a/openlane/RAM_2x4KB/config.tcl b/openlane/RAM_2x4KB/config.tcl new file mode 100644 index 0000000..5808c81 --- /dev/null +++ b/openlane/RAM_2x4KB/config.tcl
@@ -0,0 +1,40 @@ +set script_dir [file dirname [file normalize [info script]]] +# User config +set ::env(DESIGN_NAME) RAM_2x4KB + +set ::env(DESIGN_IS_CORE) 0 + +set ::env(ROUTING_CORES) 16 + +# Change if needed +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/DFFRAM_4KB.v \ + $script_dir/../../verilog/rtl/DFFRAMBB.v \ + $script_dir/../../verilog/rtl/RAM_2x4KB.v \ + $script_dir/../../verilog/rtl/RAM_6Kx32.v" + +# set ::env(SYNTH_TOP_LEVEL) 1 +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +# Fill this +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "CLK" +set ::env(CLOCK_TREE_SYNTH) 0 + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order-bot.cfg + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 950 3100" +set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)" + +#set ::env(FP_CORE_UTIL) 80 +# set ::env(PL_TARGET_DENSITY) 0. + +set ::env(PDN_CFG) $script_dir/pdn.tcl +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_ADJUSTMENT) 0.3 + +set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 +set ::env(PL_TARGET_DENSITY) 0.88 +set ::env(CELL_PAD) 0 +set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/RAM_2x4KB/pdn.tcl b/openlane/RAM_2x4KB/pdn.tcl new file mode 100644 index 0000000..19b9cce --- /dev/null +++ b/openlane/RAM_2x4KB/pdn.tcl
@@ -0,0 +1,28 @@ +# Power nets +set ::power_nets $::env(VDD_PIN) +set ::ground_nets $::env(GND_PIN) + + +pdngen::specify_grid stdcell { + name grid + rails { + met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} + } + straps { + met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + } + connect {{met1 met4}} +} + + +set ::halo 0 + +# Metal layer for rails on every row +set ::rails_mlayer "met1" ; + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ; +
diff --git a/openlane/RAM_2x4KB/pin_order-bot.cfg b/openlane/RAM_2x4KB/pin_order-bot.cfg new file mode 100644 index 0000000..f629e68 --- /dev/null +++ b/openlane/RAM_2x4KB/pin_order-bot.cfg
@@ -0,0 +1,7 @@ +#S +Do.* +Di.* +A.* +CLK +WE.* +EN
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index e5c389a..be6cec8 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -33,7 +33,8 @@ set ::env(FP_IO_HTHICKNESS_MULT) 4 # set ::env(PL_SKIP_INITIAL_PLACEMENT) 1 -set ::env(PL_BASIC_PLACEMENT) 1 +# set ::env(PL_BASIC_PLACEMENT) 1 +set ::env(PL_RANDOM_INITIAL_PLACEMENT) 1 set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_NET) "wb_clk_i" @@ -41,9 +42,13 @@ set ::env(CLOCK_PERIOD) "10" set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 -set ::env(DIODE_INSERTION_STRATEGY) 0 +set ::env(DIODE_INSERTION_STRATEGY) 4 -set ::env(PL_TARGET_DENSITY) 0.4 +set ::env(FP_HORIZONTAL_HALO) 30 +set ::env(FP_VERTICAL_HALO) 5 + +set ::env(PL_TARGET_DENSITY) 0.01 +# set ::env(PL_TARGET_DENSITY_CELLS) 0.01 # Need to fix a FastRoute bug for this to work, but it's good # for a sense of "isolation" @@ -56,15 +61,16 @@ $script_dir/../../verilog/rtl/user_project_wrapper.v $script_dir/../../verilog/rtl/Caravel_RAM_24KB_wb.v $script_dir/../../verilog/rtl/Caravel_RAM_24KB.v + $script_dir/../../verilog/rtl/RAM_6Kx32.v $script_dir/../../verilog/rtl/DFFRAMBB.v" set ::env(VERILOG_FILES_BLACKBOX) "\ $script_dir/../../verilog/rtl/defines.v $script_dir/../../verilog/rtl/DFFRAM.v - $script_dir/../../verilog/rtl/RAM_6Kx32.v" + $script_dir/../../verilog/rtl/RAM_2x4KB.v" set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/RAM_6Kx32.lef" + $script_dir/../../lef/RAM_2x4KB.lef" set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/RAM_6Kx32.gds" + $script_dir/../../gds/RAM_2x4KB.gds"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl index 15062ee..c5e08db 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -27,10 +27,13 @@ apply_def_template -set margin_x 15 -set margin_y 400 +set margin_x 30 +set margin_y 380 +set ram_width 950 -add_macro_placement ram.RAM0 $margin_x $margin_y N +add_macro_placement _587_ $margin_x $margin_y N +add_macro_placement _588_ [expr {$margin_x+$ram_width+5}] $margin_y N +add_macro_placement _589_ [expr {$margin_x+2*($ram_width+5)}] $margin_y N manual_macro_placement f @@ -39,11 +42,11 @@ set ::env(_VDD_NET_NAME) vccd1 set ::env(_GND_NET_NAME) vssd1 set ::env(_V_OFFSET) 14 -set ::env(_H_OFFSET) $::env(_V_OFFSET) +set ::env(_H_OFFSET) 14 set ::env(_V_PITCH) 180 set ::env(_H_PITCH) 180 set ::env(_V_PDN_OFFSET) 0 -set ::env(_H_PDN_OFFSET) 0 +set ::env(_H_PDN_OFFSET) 0.24 set ::env(_SPACING) 1.7 set ::env(_WIDTH) 3