Update RAM_6Kx32 configs and .gitignore

openlane/.gitignore

diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc

openlane/Makefile

diff --git a/openlane/Makefile b/openlane/Makefile
index b556fb5..c66971b 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -18,7 +18,7 @@
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
-OPENLANE_TAG ?= rc6
+OPENLANE_TAG ?= rc7
 OPENLANE_IMAGE_NAME ?= openlane:$(OPENLANE_TAG)
 OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"

openlane/RAM_6Kx32/config.tcl

diff --git a/openlane/RAM_6Kx32/config.tcl b/openlane/RAM_6Kx32/config.tcl
new file mode 100644
index 0000000..18e0f66
--- /dev/null
+++ b/openlane/RAM_6Kx32/config.tcl
@@ -0,0 +1,38 @@
+set script_dir [file dirname [file normalize [info script]]]
+# User config
+set ::env(DESIGN_NAME) RAM_6Kx32
+
+set ::env(DESIGN_IS_CORE) 0
+set ::env(LVS_INSERT_POWER_PINS) 0
+
+set ::env(ROUTING_CORES) 16
+
+# Change if needed
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/DFFRAM.v \
+	$script_dir/../../verilog/rtl/DFFRAMBB.v \
+	$script_dir/../../verilog/rtl/RAM_6Kx32.v"
+	
+# set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+# Fill this
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "CLK"
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order-bot.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2900 3100"
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+#set ::env(FP_CORE_UTIL) 80
+# set ::env(PL_TARGET_DENSITY) 0.
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(PL_TARGET_DENSITY) 0.84
+set ::env(CELL_PAD) 0
+set ::env(DIODE_INSERTION_STRATEGY) 4

openlane/RAM_6Kx32/pdn.tcl

diff --git a/openlane/RAM_6Kx32/pdn.tcl b/openlane/RAM_6Kx32/pdn.tcl
new file mode 100644
index 0000000..19b9cce
--- /dev/null
+++ b/openlane/RAM_6Kx32/pdn.tcl
@@ -0,0 +1,28 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+    }
+    connect {{met1 met4}}
+}
+
+
+set ::halo 0
+
+# Metal layer for rails on every row
+set ::rails_mlayer "met1" ;
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+

openlane/RAM_6Kx32/pin_order-bot.cfg

diff --git a/openlane/RAM_6Kx32/pin_order-bot.cfg b/openlane/RAM_6Kx32/pin_order-bot.cfg
new file mode 100644
index 0000000..f629e68
--- /dev/null
+++ b/openlane/RAM_6Kx32/pin_order-bot.cfg
@@ -0,0 +1,7 @@
+#S
+Do.*
+Di.*
+A.*
+CLK
+WE.*
+EN