Added power_pins to DFFRAM modules
diff --git a/verilog/rtl/Caravel_RAM_24KB.v b/verilog/rtl/Caravel_RAM_24KB.v
index 5e6687d..143138d 100644
--- a/verilog/rtl/Caravel_RAM_24KB.v
+++ b/verilog/rtl/Caravel_RAM_24KB.v
@@ -1,4 +1,8 @@
module Caravel_RAM_24KB (
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
CLK,
WE,
EN,
@@ -6,6 +10,12 @@
Do,
A
);
+
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
+
input CLK;
input [3:0] WE;
input EN;
@@ -14,6 +24,10 @@
input [12:0] A;
RAM_6Kx32 RAM0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
.CLK(CLK),
.WE(WE),
.EN(EN),
diff --git a/verilog/rtl/Caravel_RAM_24KB_wb.v b/verilog/rtl/Caravel_RAM_24KB_wb.v
index adc2a73..2e527cf 100644
--- a/verilog/rtl/Caravel_RAM_24KB_wb.v
+++ b/verilog/rtl/Caravel_RAM_24KB_wb.v
@@ -1,4 +1,4 @@
-module mem_wb (
+module Caravel_RAM_24KB_wb (
// Wishbone Interface
input wb_clk_i,
input wb_rst_i,
@@ -56,6 +56,6 @@
assign WE = wen;
assign EN = valid;
assign Di = wb_dat_i;
- assign A = wb_adr_i;
+ assign A = wb_adr_i[14:2];
endmodule
\ No newline at end of file
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index 7011bb9..b80677f 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -1,17 +1,56 @@
-/*
- A parameterized DFF based RAM for SKY130A
- Use the COLS parameter to set the size
- Valid sizes: 1 (default), 2 or 4
-*/
-/*
- Author: Mohamed Shalan (mshalan@aucegypt.edu)
-*/
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
-`timescale 1ns / 1ps
`default_nettype none
+`ifndef USE_CUSTOM_DFFRAM
-module DFFRAM_4kb #( parameter COLS=4)
+module DFFRAM(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input CLK,
+ input [3:0] WE,
+ input EN,
+ input [31:0] Di,
+ output reg [31:0] Do,
+ input [7:0] A
+);
+
+
+reg [31:0] mem [0:`MEM_WORDS-1];
+
+always @(posedge CLK) begin
+ if (EN == 1'b1) begin
+ Do <= mem[A];
+ if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0];
+ if (WE[1]) mem[A][15: 8] <= Di[15: 8];
+ if (WE[2]) mem[A][23:16] <= Di[23:16];
+ if (WE[3]) mem[A][31:24] <= Di[31:24];
+ end
+end
+endmodule
+
+`else
+
+module DFFRAM #( parameter COLS=1)
(
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
CLK,
WE,
EN,
@@ -27,58 +66,10 @@
output [31:0] Do;
input [7+$clog2(COLS):0] A;
- wire [31:0] DOUT [COLS-1:0];
- wire [31:0] Do_pre;
- wire [COLS-1:0] EN_lines;
-
- generate
- genvar i;
- for (i=0; i<COLS; i=i+1) begin : COLUMN
- DFFRAM_COL4 RAMCOLS ( .CLK(CLK),
- .WE(WE),
- .EN(EN_lines[i]),
- .Di(Di),
- .Do(DOUT[i]),
- .A(A[7:0])
- );
- end
- if(COLS==4) begin
- MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A[9:8]), .X(Do_pre) );
- DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) );
- end
- else if(COLS==2) begin
- MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A[8]), .X(Do_pre) );
- //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
- //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
- DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) );
-
- end
- else begin
- PASS MUX ( .A(DOUT[0]), .X(Do_pre) );
- sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) );
- end
- endgenerate
-
- sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
-
-endmodule
-
-module DFFRAM_2kb #( parameter COLS=4)
-(
- CLK,
- WE,
- EN,
- Di,
- Do,
- A
-);
-
- input CLK;
- input [3:0] WE;
- input EN;
- input [31:0] Di;
- output [31:0] Do;
- input [7+$clog2(COLS):0] A;
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
wire [31:0] DOUT [COLS-1:0];
wire [31:0] Do_pre;
@@ -87,7 +78,12 @@
generate
genvar i;
for (i=0; i<COLS; i=i+1) begin : COLUMN
- DFFRAM_COL4 RAMCOLS ( .CLK(CLK),
+ DFFRAM_COL4 RAMCOLS (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK),
.WE(WE),
.EN(EN_lines[i]),
.Di(Di),
@@ -96,22 +92,85 @@
);
end
if(COLS==4) begin
- MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A[9:8]), .X(Do_pre) );
- DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) );
+ MUX4x1_32 MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A0(DOUT[0]),
+ .A1(DOUT[1]),
+ .A2(DOUT[2]),
+ .A3(DOUT[3]),
+ .S(A[9:8]),
+ .X(Do_pre)
+ );
+ DEC2x4 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A[9:8]),
+ .SEL(EN_lines)
+ );
end
else if(COLS==2) begin
- MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A[8]), .X(Do_pre) );
+ MUX2x1_32 MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A0(DOUT[0]),
+ .A1(DOUT[1]),
+ .S(A[8]),
+ .X(Do_pre)
+ );
//sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
//sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
- DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) );
+ DEC1x2 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A[8]),
+ .SEL(EN_lines[1:0])
+ );
end
else begin
- PASS MUX ( .A(DOUT[0]), .X(Do_pre) );
- sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) );
+ PASS MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A(DOUT[0]),
+ .X(Do_pre)
+ );
+ sky130_fd_sc_hd__clkbuf_4 ENBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(EN_lines[0]),
+ .A(EN)
+ );
end
endgenerate
- sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
+ sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(Do),
+ .A(Do_pre)
+ );
endmodule
+
+`endif
\ No newline at end of file
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index ad75f22..2019be0 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -14,6 +14,10 @@
*/
module BYTE (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input CLK,
input WE,
input SEL,
@@ -26,15 +30,50 @@
wire SEL_B;
wire GCLK;
- sky130_fd_sc_hd__inv_1 INV(.Y(SEL_B), .A(SEL));
- sky130_fd_sc_hd__and2_1 CGAND( .A(SEL), .B(WE), .X(we_wire) );
- sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
+ sky130_fd_sc_hd__inv_1 INV(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .Y(SEL_B), .A(SEL));
+ sky130_fd_sc_hd__and2_1 CGAND(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A(SEL), .B(WE), .X(we_wire) );
+ sky130_fd_sc_hd__dlclkp_1 CG(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
generate
genvar i;
for(i=0; i<8; i=i+1) begin : BIT
- sky130_fd_sc_hd__dfxtp_1 FF ( .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) );
- sky130_fd_sc_hd__ebufn_2 OBUF ( .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) );
+ sky130_fd_sc_hd__dfxtp_1 FF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) );
+ sky130_fd_sc_hd__ebufn_2 OBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) );
end
endgenerate
@@ -42,6 +81,10 @@
module WORD32 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input CLK,
input [3:0] WE,
input SEL,
@@ -49,52 +92,186 @@
output [31:0] Do
);
- BYTE B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
- BYTE B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
- BYTE B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
- BYTE B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
+ BYTE B0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
+ BYTE B1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
+ BYTE B2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
+ BYTE B3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
endmodule
module DEC1x2 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input EN,
input [0:0] A,
output [1:0] SEL
);
- sky130_fd_sc_hd__and2b_2 AND1 ( .X(SEL[0]), .A_N(A), .B(EN) );
- sky130_fd_sc_hd__and2_2 AND3 ( .X(SEL[1]), .A(A), .B(A[0]) );
+ sky130_fd_sc_hd__and2b_2 AND1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[0]), .A_N(A), .B(EN) );
+ sky130_fd_sc_hd__and2_2 AND3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[1]), .A(A), .B(A[0]) );
endmodule
module DEC2x4 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input EN,
input [1:0] A,
output [3:0] SEL
);
- sky130_fd_sc_hd__nor3b_4 AND0 ( .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) );
- sky130_fd_sc_hd__and3b_4 AND1 ( .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
- sky130_fd_sc_hd__and3b_4 AND2 ( .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
- sky130_fd_sc_hd__and3_4 AND3 ( .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) );
+ sky130_fd_sc_hd__nor3b_4 AND0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) );
+ sky130_fd_sc_hd__and3b_4 AND1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
+ sky130_fd_sc_hd__and3b_4 AND2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
+ sky130_fd_sc_hd__and3_4 AND3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) );
endmodule
module DEC3x8 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input EN,
input [2:0] A,
output [7:0] SEL
);
- sky130_fd_sc_hd__nor4b_2 AND0 ( .Y(SEL[0]) , .A(A[0]), .B(A[1]) , .C(A[2]), .D_N(EN) ); // 000
- sky130_fd_sc_hd__and4bb_2 AND1 ( .X(SEL[1]) , .A_N(A[2]), .B_N(A[1]), .C(A[0]) , .D(EN) ); // 001
- sky130_fd_sc_hd__and4bb_2 AND2 ( .X(SEL[2]) , .A_N(A[2]), .B_N(A[0]), .C(A[1]) , .D(EN) ); // 010
- sky130_fd_sc_hd__and4b_2 AND3 ( .X(SEL[3]) , .A_N(A[2]), .B(A[1]), .C(A[0]) , .D(EN) ); // 011
- sky130_fd_sc_hd__and4bb_2 AND4 ( .X(SEL[4]) , .A_N(A[0]), .B_N(A[1]), .C(A[2]) , .D(EN) ); // 100
- sky130_fd_sc_hd__and4b_2 AND5 ( .X(SEL[5]) , .A_N(A[1]), .B(A[0]), .C(A[2]) , .D(EN) ); // 101
- sky130_fd_sc_hd__and4b_2 AND6 ( .X(SEL[6]) , .A_N(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 110
- sky130_fd_sc_hd__and4_2 AND7 ( .X(SEL[7]) , .A(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 111
+ sky130_fd_sc_hd__nor4b_2 AND0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .Y(SEL[0]) , .A(A[0]), .B(A[1]) , .C(A[2]), .D_N(EN) ); // 000
+ sky130_fd_sc_hd__and4bb_2 AND1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[1]) , .A_N(A[2]), .B_N(A[1]), .C(A[0]) , .D(EN) ); // 001
+ sky130_fd_sc_hd__and4bb_2 AND2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[2]) , .A_N(A[2]), .B_N(A[0]), .C(A[1]) , .D(EN) ); // 010
+ sky130_fd_sc_hd__and4b_2 AND3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[3]) , .A_N(A[2]), .B(A[1]), .C(A[0]) , .D(EN) ); // 011
+ sky130_fd_sc_hd__and4bb_2 AND4 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[4]) , .A_N(A[0]), .B_N(A[1]), .C(A[2]) , .D(EN) ); // 100
+ sky130_fd_sc_hd__and4b_2 AND5 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[5]) , .A_N(A[1]), .B(A[0]), .C(A[2]) , .D(EN) ); // 101
+ sky130_fd_sc_hd__and4b_2 AND6 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[6]) , .A_N(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 110
+ sky130_fd_sc_hd__and4_2 AND7 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[7]) , .A(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 111
endmodule
module DEC6x64 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input EN,
input [5:0] A,
output [63:0] SEL
@@ -102,39 +279,87 @@
wire [7:0] SEL0_w ;
wire [2:0] A_buf;
- DEC3x8 DEC_L0 ( .EN(EN), .A(A[5:3]), .SEL(SEL0_w) );
+ DEC3x8 DEC_L0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN), .A(A[5:3]), .SEL(SEL0_w) );
- sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (.X(A_buf), .A(A[2:0]));
+ sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(A_buf), .A(A[2:0]));
generate
genvar i;
for(i=0; i<8; i=i+1) begin : DEC_L1
- DEC3x8 U ( .EN(SEL0_w[i]), .A(A_buf), .SEL(SEL[7+8*i: 8*i]) );
+ DEC3x8 U (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(SEL0_w[i]), .A(A_buf), .SEL(SEL[7+8*i: 8*i]) );
end
endgenerate
endmodule
module MUX2x1_32(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input [31:0] A0, A1,
input [0:0] S,
output [31:0] X
);
- sky130_fd_sc_hd__mux2_1 MUX[31:0] (.A0(A0), .A1(A1), .S(S[0]), .X(X) );
+ sky130_fd_sc_hd__mux2_1 MUX[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A0(A0), .A1(A1), .S(S[0]), .X(X) );
endmodule
module MUX4x1_32(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input [31:0] A0, A1, A2, A3,
input [1:0] S,
output [31:0] X
);
- sky130_fd_sc_hd__mux4_1 MUX[31:0] (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
+ sky130_fd_sc_hd__mux4_1 MUX[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
endmodule
-module PASS (input [31:0] A, output [31:0] X);
+module PASS (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input [31:0] A, output [31:0] X);
assign X = A;
endmodule
module SRAM64x32(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
input CLK,
input [3:0] WE,
input EN,
@@ -149,30 +374,89 @@
wire CLK_buf;
wire [3:0] WE_buf;
- sky130_fd_sc_hd__clkbuf_16 CLKBUF (.X(CLK_buf), .A(CLK));
- sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (.X(WE_buf), .A(WE));
- sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (.X(Di_buf), .A(Di));
+ sky130_fd_sc_hd__clkbuf_16 CLKBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(CLK_buf), .A(CLK));
+ sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(WE_buf), .A(WE));
+ sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(Di_buf), .A(Di));
- DEC6x64 DEC ( .EN(EN), .A(A), .SEL(SEL) );
+ DEC6x64 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN), .A(A), .SEL(SEL) );
generate
genvar i;
for (i=0; i< 64; i=i+1) begin : WORD
- WORD32 W ( .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) );
+ WORD32 W (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) );
end
endgenerate
// Ensure that the Do_pre lines are not floating when EN = 0
wire lo;
wire float_buf_en;
- sky130_fd_sc_hd__clkbuf_4 FBUFENBUF( .X(float_buf_en), .A(EN) );
- sky130_fd_sc_hd__conb_1 TIE (.LO(lo), .HI());
- sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( .A( lo ), .Z(Do_pre), .TE_B(float_buf_en) );
+ sky130_fd_sc_hd__clkbuf_4 FBUFENBUF(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(float_buf_en), .A(EN) );
+ sky130_fd_sc_hd__conb_1 TIE (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .LO(lo), .HI());
+ sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A( lo ), .Z(Do_pre), .TE_B(float_buf_en) );
generate
//genvar i;
for(i=0; i<32; i=i+1) begin : OUT
- sky130_fd_sc_hd__dfxtp_1 FF ( .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) );
+ sky130_fd_sc_hd__dfxtp_1 FF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) );
end
endgenerate
@@ -180,6 +464,10 @@
module DFFRAM_COL4
(
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
CLK,
WE,
EN,
@@ -188,6 +476,10 @@
A
);
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
input CLK;
input [3:0] WE;
input EN;
@@ -209,20 +501,79 @@
wire [3:0] row_sel;
- sky130_fd_sc_hd__clkbuf_8 CLKBUF (.X(CLK_buf), .A(CLK));
- sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (.X(WE_buf), .A(WE));
- sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (.X(Di_buf), .A(Di));
+ sky130_fd_sc_hd__clkbuf_8 CLKBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
- sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( .X(A_buf), .A(A[5:3]) );
+ .X(CLK_buf), .A(CLK));
+ sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(WE_buf), .A(WE));
+ sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(Di_buf), .A(Di));
+
+ sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(A_buf), .A(A[5:3]) );
- DEC2x4 DEC ( .EN(EN), .A(A[7:6]), .SEL(row_sel) );
+ DEC2x4 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN), .A(A[7:6]), .SEL(row_sel) );
- SRAM64x32 B_0_0 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A({A_buf,A[2:0]}) );
- SRAM64x32 B_0_1 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A({A_buf,A[2:0]}) );
- SRAM64x32 B_0_2 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A({A_buf,A[2:0]}) );
- SRAM64x32 B_0_3 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A({A_buf,A[2:0]}) );
+ SRAM64x32 B_0_0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A({A_buf,A[2:0]}) );
+ SRAM64x32 B_0_1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A({A_buf,A[2:0]}) );
+ SRAM64x32 B_0_2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A({A_buf,A[2:0]}) );
+ SRAM64x32 B_0_3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A({A_buf,A[2:0]}) );
- MUX4x1_32 MUX ( .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do) );
+ MUX4x1_32 MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do) );
endmodule
diff --git a/verilog/rtl/RAM_6Kx32.v b/verilog/rtl/RAM_6Kx32.v
index 29760a8..df1d149 100644
--- a/verilog/rtl/RAM_6Kx32.v
+++ b/verilog/rtl/RAM_6Kx32.v
@@ -1,5 +1,9 @@
//`define USE_DFFRAM_BEH
module RAM_6Kx32 (
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
CLK,
WE,
EN,
@@ -7,6 +11,10 @@
Do,
A
);
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
input CLK;
input [3:0] WE;
input EN;
@@ -26,9 +34,13 @@
`ifdef USE_DFFRAM_BEH
DFFRAM_beh
`else
- DFFRAM
+ DFFRAM_4KB
`endif
#(.COLS(4)) RAM (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
.CLK(CLK),
.WE(WE),
.EN(_EN_[gi]),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index ea844ca..f7cc312 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -83,7 +83,7 @@
/*------------------------------*/
/* Include user project here */
/*------------------------------*/
-`include "user_proj_example.v"
+// `include "user_proj_example.v"
// `ifdef USE_OPENRAM
// `include "sram_1rw1r_32_256_8_sky130.v"
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 341565f..ef15dec 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -250,7 +250,7 @@
sky130_fd_io__top_xres4v2 resetb_pad (
`MGMT_ABUTMENT_PINS
`ifndef TOP_ROUTING
- .PAD(resetb),
+ ,.PAD(resetb),
`endif
.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
.TIE_HI_ESD(),
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 8e7a669..af5a2e8 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -62,7 +62,7 @@
sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] (
`USER1_ABUTMENT_PINS
`ifndef TOP_ROUTING
- .PAD(io[AREA1PADS - 1:0]),
+ ,.PAD(io[AREA1PADS - 1:0]),
`endif
.OUT(io_out[AREA1PADS - 1:0]),
.OE_N(oeb[AREA1PADS - 1:0]),
@@ -93,7 +93,7 @@
sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [`MPRJ_IO_PADS - AREA1PADS - 1:0] (
`USER2_ABUTMENT_PINS
`ifndef TOP_ROUTING
- .PAD(io[`MPRJ_IO_PADS - 1:AREA1PADS]),
+ ,.PAD(io[`MPRJ_IO_PADS - 1:AREA1PADS]),
`endif
.OUT(io_out[`MPRJ_IO_PADS - 1:AREA1PADS]),
.OE_N(oeb[`MPRJ_IO_PADS - 1:AREA1PADS]),
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index a523518..f89ba90 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -27,7 +27,7 @@
.VCCD(vccd1),\
.VSSIO(vssio),\
.VSSD(vssd1),\
- .VSSIO_Q(vssio_q),
+ .VSSIO_Q(vssio_q)
`define USER2_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@@ -41,7 +41,7 @@
.VCCD(vccd2),\
.VSSIO(vssio),\
.VSSD(vssd2),\
- .VSSIO_Q(vssio_q),
+ .VSSIO_Q(vssio_q)
`define MGMT_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@@ -55,7 +55,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
- .VSSIO_Q(vssio_q),
+ .VSSIO_Q(vssio_q)
`else
`define USER1_ABUTMENT_PINS
`define USER2_ABUTMENT_PINS
@@ -78,7 +78,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
- .PAD(X), \
+ ,.PAD(X), \
`endif \
.OUT(vssd), \
.OE_N(vccd), \
@@ -110,7 +110,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
- .PAD(X), \
+ ,.PAD(X), \
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
@@ -142,7 +142,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
- .PAD(X),\
+ ,.PAD(X), \
`endif \
.OUT(Y_OUT), \
.OE_N(OUT_EN_N), \
