Added dv test
diff --git a/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v b/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v new file mode 100644 index 0000000..6c03f57 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/DFFRAM_beh.v
@@ -0,0 +1,42 @@ +module DFFRAM_beh #( parameter COLS=1) +( +`ifdef USE_POWER_PINS + VPWR, + VGND, +`endif + CLK, + WE, + EN, + Di, + Do, + A +); + +`ifdef USE_POWER_PINS + input VPWR; + input VGND; +`endif + + localparam A_WIDTH = 8+$clog2(COLS); + + input wire CLK; + input wire [3:0] WE; + input wire EN; + input wire [31:0] Di; + output reg [31:0] Do; + input wire [(A_WIDTH - 1): 0] A; + + reg [31:0] RAM[(256*COLS)-1 : 0]; + + always @(posedge CLK) + if(EN) begin + Do <= RAM[A]; + if(WE[0]) RAM[A][ 7: 0] <= Di[7:0]; + if(WE[1]) RAM[A][15:8] <= Di[15:8]; + if(WE[2]) RAM[A][23:16] <= Di[23:16]; + if(WE[3]) RAM[A][31:24] <= Di[31:24]; + end + else + Do <= 32'b0; + +endmodule \ No newline at end of file
diff --git a/verilog/dv/caravel/user_proj_example/Makefile b/verilog/dv/caravel/user_proj_example/Makefile index 7e37e02..1a7f9e2 100644 --- a/verilog/dv/caravel/user_proj_example/Makefile +++ b/verilog/dv/caravel/user_proj_example/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = io_ports la_test1 la_test2 +PATTERNS = mem all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile deleted file mode 100644 index 321de72..0000000 --- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile +++ /dev/null
@@ -1,67 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -FIRMWARE_PATH = ../.. -VERILOG_PATH = ../../../.. -RTL_PATH = $(VERILOG_PATH)/rtl -IP_PATH = ../../../../ip -BEHAVIOURAL_MODELS = ../../ - -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A - -SIM?=RTL - -.SUFFIXES: - -PATTERN = io_ports - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \ - -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ - $< -o $@ -else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \ - -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c deleted file mode 100644 index f0542f6..0000000 --- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c +++ /dev/null
@@ -1,70 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "../../defs.h" - -/* - IO Test: - - Configures MPRJ lower 8-IO pins as outputs - - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) -*/ - -void main() -{ - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - // Configure lower 8-IOs as user output - // Observe counter value in the testbench - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - -} -
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v deleted file mode 100644 index 3a98f7a..0000000 --- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v +++ /dev/null
@@ -1,168 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "caravel.v" -`include "spiflash.v" - -module io_ports_tb; - reg clock; - reg RSTB; - reg CSB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - - assign mprj_io_0 = mprj_io[7:0]; - // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]}; - - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - // assign mprj_io[3] = 1'b1; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("io_ports.vcd"); - $dumpvars(0, io_ports_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (25) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - // Observe Output pins [7:0] - wait(mprj_io_0 == 8'h01); - wait(mprj_io_0 == 8'h02); - wait(mprj_io_0 == 8'h03); - wait(mprj_io_0 == 8'h04); - wait(mprj_io_0 == 8'h05); - wait(mprj_io_0 == 8'h06); - wait(mprj_io_0 == 8'h07); - wait(mprj_io_0 == 8'h08); - wait(mprj_io_0 == 8'h09); - wait(mprj_io_0 == 8'h0A); - wait(mprj_io_0 == 8'hFF); - wait(mprj_io_0 == 8'h00); - - `ifdef GL - $display("Monitor: Test 1 Mega-Project IO (GL) Passed"); - `else - $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); - `endif - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #100; - power1 <= 1'b1; - #100; - power2 <= 1'b1; - #100; - power3 <= 1'b1; - #100; - power4 <= 1'b1; - end - - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire USER_VDD3V3 = power3; - wire USER_VDD1V8 = power4; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("io_ports.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c deleted file mode 100644 index c5d47bc..0000000 --- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c +++ /dev/null
@@ -1,123 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "../../defs.h" -#include "../../stub.c" - -// -------------------------------------------------------- - -/* - MPRJ Logic Analyzer Test: - - Observes counter value through LA probes [31:0] - - Sets counter initial value through LA probes [63:32] - - Flags when counter value exceeds 500 through the management SoC gpio - - Outputs message to the UART when the test concludes successfuly -*/ - -void main() -{ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - // The upper GPIO pins are configured to be output - // and accessble to the management SoC. - // Used to flad the start/end of a test - // The lower GPIO pins are configured to be output - // and accessible to the user project. They show - // the project count value, although this test is - // designed to read the project count through the - // logic analyzer probes. - // I/O 6 is configured for the UART Tx line - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Set UART clock to 64 kbaud (enable before I/O configuration) - reg_uart_clkdiv = 625; - reg_uart_enable = 1; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - // Configure LA probes [31:0], [127:64] as inputs to the cpu - // Configure LA probes [63:32] as outputs from the cpu - reg_la0_ena = 0xFFFFFFFF; // [31:0] - reg_la1_ena = 0x00000000; // [63:32] - reg_la2_ena = 0xFFFFFFFF; // [95:64] - reg_la3_ena = 0xFFFFFFFF; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB400000; - - // Set Counter value to zero through LA probes [63:32] - reg_la1_data = 0x00000000; - - // Configure LA probes from [63:32] as inputs to disable counter write - reg_la1_ena = 0xFFFFFFFF; - - while (1) { - if (reg_la0_data > 0x1F4) { - reg_mprj_datal = 0xAB410000; - break; - } - } - print("\n"); - print("Monitor: Test 2 Passed\n\n"); // Makes simulation very long! - reg_mprj_datal = 0xAB510000; -} -
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v deleted file mode 100644 index 8f07fe4..0000000 --- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v +++ /dev/null
@@ -1,148 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "caravel.v" -`include "spiflash.v" -`include "tbuart.v" - -module la_test1_tb; - reg clock; - reg RSTB; - reg CSB; - - reg power1, power2; - - wire gpio; - wire uart_tx; - wire [37:0] mprj_io; - wire [15:0] checkbits; - - assign checkbits = mprj_io[31:16]; - assign uart_tx = mprj_io[6]; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - initial begin - // $dumpfile("la_test1.vcd"); - // $dumpvars(0, la_test1_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (200) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test LA (GL) Failed"); - `else - $display ("Monitor: Timeout, Test LA (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'hAB40); - $display("LA Test 1 started"); - wait(checkbits == 16'hAB41); - wait(checkbits == 16'hAB51); - #10000; - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD1V8; - wire VDD3V3; - wire VSS; - - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("la_test1.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - - // Testbench UART - tbuart tbuart ( - .ser_rx(uart_tx) - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile deleted file mode 100644 index 189dfa4..0000000 --- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile +++ /dev/null
@@ -1,68 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - - -FIRMWARE_PATH = ../.. -VERILOG_PATH = ../../../.. -RTL_PATH = $(VERILOG_PATH)/rtl -IP_PATH = ../../../../ip -BEHAVIOURAL_MODELS = ../../ - -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A - -SIM?=RTL - -.SUFFIXES: - -PATTERN = la_test2 - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \ - -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ - $< -o $@ -else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \ - -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c deleted file mode 100644 index ef1b5e9..0000000 --- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c +++ /dev/null
@@ -1,110 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "../../defs.h" -#include "../../stub.c" - -/* - MPRJ LA Test: - - Sets counter clk through LA[64] - - Sets counter rst through LA[65] - - Observes count value for five clk cycle through LA[31:0] -*/ - -int clk = 0; -int i; - -void main() -{ - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - - // All GPIO pins are configured to be output - // Used to flad the start/end of a test - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - // Configure All LA probes as inputs to the cpu - reg_la0_ena = 0xFFFFFFFF; // [31:0] - reg_la1_ena = 0xFFFFFFFF; // [63:32] - reg_la2_ena = 0xFFFFFFFF; // [95:64] - reg_la3_ena = 0xFFFFFFFF; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB600000; - - // Configure LA[64] LA[65] as outputs from the cpu - reg_la2_ena = 0xFFFFFFFC; - - // Set clk & reset to one - reg_la2_data = 0x00000003; - - // Toggle clk & de-assert reset - for (i=0; i<11; i=i+1) { - clk = !clk; - reg_la2_data = 0x00000000 | clk; - } - - if (reg_la0_data == 0x05) { - reg_mprj_datal = 0xAB610000; - } - -} -
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v deleted file mode 100644 index a0e7fcf..0000000 --- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v +++ /dev/null
@@ -1,138 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "caravel.v" -`include "spiflash.v" - -module la_test2_tb; - reg clock; - reg RSTB; - reg CSB; - - reg power1, power2; - - wire gpio; - wire [37:0] mprj_io; - wire [15:0] checkbits; - - assign checkbits = mprj_io[31:16]; - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("la_test2.vcd"); - $dumpvars(0, la_test2_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (30) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'h AB60); - $display("Monitor: Test 2 MPRJ-Logic Analyzer Started"); - wait(checkbits == 16'h AB61); - $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed"); - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD1V8; - wire VDD3V3; - wire VSS; - - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("la_test2.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), - .io3() - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/mem/Makefile similarity index 92% rename from verilog/dv/caravel/user_proj_example/la_test1/Makefile rename to verilog/dv/caravel/user_proj_example/mem/Makefile index e9ad798..ca67552 100644 --- a/verilog/dv/caravel/user_proj_example/la_test1/Makefile +++ b/verilog/dv/caravel/user_proj_example/mem/Makefile
@@ -14,7 +14,6 @@ # # SPDX-License-Identifier: Apache-2.0 - FIRMWARE_PATH = ../.. VERILOG_PATH = ../../../.. RTL_PATH = $(VERILOG_PATH)/rtl @@ -29,7 +28,7 @@ .SUFFIXES: -PATTERN = la_test1 +PATTERN = mem all: ${PATTERN:=.vcd} @@ -37,8 +36,8 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \ - -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -DSIM -DUSE_DFFRAM_BEH -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I .. \ $< -o $@ else iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
diff --git a/verilog/dv/caravel/user_proj_example/mem/mem.c b/verilog/dv/caravel/user_proj_example/mem/mem.c new file mode 100644 index 0000000..b7f8d1e --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/mem/mem.c
@@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../../defs.h" + +// -------------------------------------------------------- + +/* + Storage area Test + It uses GPIO to flag the success or failure of the test +*/ + +void main() +{ + int i; + volatile uint32_t* ram_addr; + /* Upper 16 user area pins are configured to be GPIO output */ + + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + + // Apply configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // start test + reg_mprj_datal = 0xA0400000; + + // Test DFFRAM R/W + for (i=0; i<10; i++){ + ram_addr = ®_mprj_slave + i; + *ram_addr = i*5000 + 10000; + } + + for (i=0; i<10; i++){ + ram_addr = ®_mprj_slave + i; + if ((i*5000+10000) != *ram_addr) + reg_mprj_datal = 0xAB400000; + } + + reg_mprj_datal = 0xAB410000; +} +
diff --git a/verilog/dv/caravel/user_proj_example/mem/mem_tb.v b/verilog/dv/caravel/user_proj_example/mem/mem_tb.v new file mode 100644 index 0000000..a8f00c3 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/mem/mem_tb.v
@@ -0,0 +1,177 @@ +`default_nettype none +/* + * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards + * + * StriVe - A full example SoC using PicoRV32 in SkyWater s8 + * + * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2018 Tim Edwards <tim@efabless.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * SPDX-License-Identifier: ISC + */ + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" + +`ifdef USE_DFFRAM_BEH + `include "DFFRAM_beh.v" +`else + `include "DFFRAM_4KB.v" +`endif + +`include "RAM_6Kx32.v" +`include "Caravel_RAM_24KB_wb.v" +`include "Caravel_RAM_24KB.v" + + + +module mem_tb; + reg clock; + reg RSTB; + reg power1, power2; + + wire gpio; + wire [15:0] checkbits; + wire [37:0] mprj_io; + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + assign checkbits = mprj_io[31:16]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #10 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("mem.vcd"); + $dumpvars(0, mem_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (100) begin + repeat (1000) @(posedge clock); + //$display("+1000 cycles"); + end + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Timeout, Test Storage (GL) Failed"); + `else + $display ("Monitor: Timeout, Test Storage (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + RSTB <= 1'b0; + #1000; + RSTB <= 1'b1; // Release reset + #2000; + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + end + + always @(checkbits) begin + if(checkbits == 16'hA040) begin + `ifdef GL + $display("Mem Test storage MGMT block0 (GL) [word rw] started"); + `else + $display("Mem Test storage MGMT block0 (RTL) [word rw] started"); + `endif + end + else if(checkbits == 16'hAB40) begin + $display("%c[1;31m",27); + `ifdef GL + $display("Monitor: Test storage MGMT block0 (GL) [word rw] failed"); + `else + $display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed"); + `endif + $display("%c[0m",27); + $finish; + end + else if(checkbits == 16'hAB41) begin + `ifdef GL + $display("Monitor: Test storage MGMT block0 (GL) [word rw] passed"); + `else + $display("Monitor: Test storage MGMT block0 (RTL) [word rw] passed"); + `endif + $finish; + end + end + + wire VDD3V3; + wire VDD1V8; + wire VSS; + + assign VSS = 1'b0; + assign VDD3V3 = power1; + assign VDD1V8 = power2; + + assign mprj_io[3] = 1'b1; // Force CSB high. + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("mem.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire