TB update

verilog/dv/caravel/user_proj_example/mem/Makefile

diff --git a/verilog/dv/caravel/user_proj_example/mem/Makefile b/verilog/dv/caravel/user_proj_example/mem/Makefile
index ca67552..627ef7e 100644
--- a/verilog/dv/caravel/user_proj_example/mem/Makefile
+++ b/verilog/dv/caravel/user_proj_example/mem/Makefile
@@ -36,7 +36,7 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -DUSE_DFFRAM_BEH -I $(BEHAVIOURAL_MODELS) \
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I .. \
 	$< -o $@ 
 else  

verilog/dv/caravel/user_proj_example/mem/mem_tb.v

diff --git a/verilog/dv/caravel/user_proj_example/mem/mem_tb.v b/verilog/dv/caravel/user_proj_example/mem/mem_tb.v
index a8f00c3..e0a3935 100644
--- a/verilog/dv/caravel/user_proj_example/mem/mem_tb.v
+++ b/verilog/dv/caravel/user_proj_example/mem/mem_tb.v
@@ -34,11 +34,10 @@
 `endif
 
 `include "RAM_6Kx32.v"
+`include "RAM_2x4KB.v"
 `include "Caravel_RAM_24KB_wb.v"
 `include "Caravel_RAM_24KB.v"
 
-
-
 module mem_tb;
 	reg clock;
 	reg RSTB;