Migrated to the latest DFFRAM
diff --git a/verilog/rtl/DFFRAM _4KB.v b/verilog/rtl/DFFRAM _4KB.v new file mode 100644 index 0000000..e70cbd1 --- /dev/null +++ b/verilog/rtl/DFFRAM _4KB.v
@@ -0,0 +1,69 @@ +/* + A parameterized DFF based RAM for SKY130A + Use the COLS parameter to set the size + Valid sizes: 1 (default), 2 or 4 +*/ +/* + Author: Mohamed Shalan (mshalan@aucegypt.edu) +*/ + +`timescale 1ns / 1ps +`default_nettype none + +module DFFRAM_4KB #( parameter COLS=4, USE_LATCH=0) +( + CLK, + WE, + EN, + Di, + Do, + A +); + + input CLK; + input [3:0] WE; + input EN; + input [31:0] Di; + output [31:0] Do; + input [7+$clog2(COLS):0] A; + + wire [31:0] DOUT [COLS-1:0]; + wire [31:0] Do_pre; + wire [COLS-1:0] EN_lines; + + wire [9:8] A_buf; + + generate + genvar i; + for (i=0; i<COLS; i=i+1) begin : COLUMN + DFFRAM_COL4 #(.USE_LATCH(USE_LATCH)) + RAMCOLS ( .CLK(CLK), + .WE(WE), + .EN(EN_lines[i]), + .Di(Di), + .Do(DOUT[i]), + .A(A[7:0]) + ); + end + if(COLS==4) begin + sky130_fd_sc_hd__clkbuf_8 ABUF[1:0] (.X(A_buf[9:8]), .A(A[9:8]) ); + MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A_buf[9:8]), .X(Do_pre) ); + DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) ); + end + else if(COLS==2) begin + sky130_fd_sc_hd__clkbuf_8 ABUF[8:8] (.X(A_buf[8]), .A(A[8]) ); + MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A_buf[8]), .X(Do_pre) ); + //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) ); + //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) ); + DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) ); + + end + else begin + PASS MUX ( .A(DOUT[0]), .X(Do_pre) ); + sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) ); + end + endgenerate + + sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre)); + +endmodule
diff --git a/verilog/rtl/DFFRAM-.v b/verilog/rtl/DFFRAM-.v new file mode 100644 index 0000000..b80677f --- /dev/null +++ b/verilog/rtl/DFFRAM-.v
@@ -0,0 +1,176 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +`ifndef USE_CUSTOM_DFFRAM + +module DFFRAM( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input CLK, + input [3:0] WE, + input EN, + input [31:0] Di, + output reg [31:0] Do, + input [7:0] A +); + + +reg [31:0] mem [0:`MEM_WORDS-1]; + +always @(posedge CLK) begin + if (EN == 1'b1) begin + Do <= mem[A]; + if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0]; + if (WE[1]) mem[A][15: 8] <= Di[15: 8]; + if (WE[2]) mem[A][23:16] <= Di[23:16]; + if (WE[3]) mem[A][31:24] <= Di[31:24]; + end +end +endmodule + +`else + +module DFFRAM #( parameter COLS=1) +( +`ifdef USE_POWER_PINS + VPWR, + VGND, +`endif + CLK, + WE, + EN, + Di, + Do, + A +); + + input CLK; + input [3:0] WE; + input EN; + input [31:0] Di; + output [31:0] Do; + input [7+$clog2(COLS):0] A; + +`ifdef USE_POWER_PINS + input VPWR; + input VGND; +`endif + + wire [31:0] DOUT [COLS-1:0]; + wire [31:0] Do_pre; + wire [COLS-1:0] EN_lines; + + generate + genvar i; + for (i=0; i<COLS; i=i+1) begin : COLUMN + DFFRAM_COL4 RAMCOLS ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), + .WE(WE), + .EN(EN_lines[i]), + .Di(Di), + .Do(DOUT[i]), + .A(A[7:0]) + ); + end + if(COLS==4) begin + MUX4x1_32 MUX ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .A0(DOUT[0]), + .A1(DOUT[1]), + .A2(DOUT[2]), + .A3(DOUT[3]), + .S(A[9:8]), + .X(Do_pre) + ); + DEC2x4 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), + .A(A[9:8]), + .SEL(EN_lines) + ); + end + else if(COLS==2) begin + MUX2x1_32 MUX ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .A0(DOUT[0]), + .A1(DOUT[1]), + .S(A[8]), + .X(Do_pre) + ); + //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) ); + //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) ); + DEC1x2 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), + .A(A[8]), + .SEL(EN_lines[1:0]) + ); + + end + else begin + PASS MUX ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .A(DOUT[0]), + .X(Do_pre) + ); + sky130_fd_sc_hd__clkbuf_4 ENBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(EN_lines[0]), + .A(EN) + ); + end + endgenerate + + sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Do), + .A(Do_pre) + ); + +endmodule + +`endif \ No newline at end of file
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v index b80677f..73ad0ad 100644 --- a/verilog/rtl/DFFRAM.v +++ b/verilog/rtl/DFFRAM.v
@@ -1,56 +1,17 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 +/* + A parameterized DFF based RAM for SKY130A + Use the COLS parameter to set the size + Valid sizes: 1 (default), 2 or 4 +*/ +/* + Author: Mohamed Shalan (mshalan@aucegypt.edu) +*/ +`timescale 1ns / 1ps `default_nettype none -`ifndef USE_CUSTOM_DFFRAM -module DFFRAM( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif - input CLK, - input [3:0] WE, - input EN, - input [31:0] Di, - output reg [31:0] Do, - input [7:0] A -); - - -reg [31:0] mem [0:`MEM_WORDS-1]; - -always @(posedge CLK) begin - if (EN == 1'b1) begin - Do <= mem[A]; - if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0]; - if (WE[1]) mem[A][15: 8] <= Di[15: 8]; - if (WE[2]) mem[A][23:16] <= Di[23:16]; - if (WE[3]) mem[A][31:24] <= Di[31:24]; - end -end -endmodule - -`else - -module DFFRAM #( parameter COLS=1) +module DFFRAM #( parameter COLS=4, USE_LATCH=0) ( -`ifdef USE_POWER_PINS - VPWR, - VGND, -`endif CLK, WE, EN, @@ -66,24 +27,17 @@ output [31:0] Do; input [7+$clog2(COLS):0] A; -`ifdef USE_POWER_PINS - input VPWR; - input VGND; -`endif - wire [31:0] DOUT [COLS-1:0]; wire [31:0] Do_pre; wire [COLS-1:0] EN_lines; + wire [9:8] A_buf; + generate genvar i; for (i=0; i<COLS; i=i+1) begin : COLUMN - DFFRAM_COL4 RAMCOLS ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK), + DFFRAM_COL4 #(.USE_LATCH(USE_LATCH)) + RAMCOLS ( .CLK(CLK), .WE(WE), .EN(EN_lines[i]), .Di(Di), @@ -92,85 +46,24 @@ ); end if(COLS==4) begin - MUX4x1_32 MUX ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .A0(DOUT[0]), - .A1(DOUT[1]), - .A2(DOUT[2]), - .A3(DOUT[3]), - .S(A[9:8]), - .X(Do_pre) - ); - DEC2x4 DEC ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .EN(EN), - .A(A[9:8]), - .SEL(EN_lines) - ); + sky130_fd_sc_hd__clkbuf_8 ABUF[1:0] (.X(A_buf[9:8]), .A(A[9:8]) ); + MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A_buf[9:8]), .X(Do_pre) ); + DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) ); end else if(COLS==2) begin - MUX2x1_32 MUX ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .A0(DOUT[0]), - .A1(DOUT[1]), - .S(A[8]), - .X(Do_pre) - ); + sky130_fd_sc_hd__clkbuf_8 ABUF[8:8] (.X(A_buf[8]), .A(A[8]) ); + MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A_buf[8]), .X(Do_pre) ); //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) ); //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) ); - DEC1x2 DEC ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .EN(EN), - .A(A[8]), - .SEL(EN_lines[1:0]) - ); + DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) ); end else begin - PASS MUX ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .A(DOUT[0]), - .X(Do_pre) - ); - sky130_fd_sc_hd__clkbuf_4 ENBUF ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(EN_lines[0]), - .A(EN) - ); + PASS MUX ( .A(DOUT[0]), .X(Do_pre) ); + sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) ); end endgenerate - sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(Do), - .A(Do_pre) - ); + sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre)); endmodule - -`endif \ No newline at end of file
diff --git a/verilog/rtl/DFFRAMBB-.v b/verilog/rtl/DFFRAMBB-.v new file mode 100644 index 0000000..2019be0 --- /dev/null +++ b/verilog/rtl/DFFRAMBB-.v
@@ -0,0 +1,579 @@ +/* + Building blocks for DFF based RAM compiler for SKY130A + BYTE : 8 memory cells used as a building block for WORD module + WORD : 32-bit memory word with select and byte-level WE + DEC6x64 : 2x4 Binary Decoder + DEC6x64 : 6x64 Binary decoder + MUX4x1_32 : 32-bit 4x1 MUX + MUX2x1_32 : 32-bit 2x1 MUX + SRAM64x32 : Tri-state buffers based 64x32 DFF RAM + DFFRAM_COL4 : A single column of 4 SRAM64x32 blocks using 4x1 multiplexors +*/ +/* + Author: Mohamed Shalan (mshalan@aucegypt.edu) +*/ + +module BYTE ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input CLK, + input WE, + input SEL, + input [7:0] Di, + output [7:0] Do +); + + wire [7:0] q_wire; + wire we_wire; + wire SEL_B; + wire GCLK; + + sky130_fd_sc_hd__inv_1 INV( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL_B), .A(SEL)); + sky130_fd_sc_hd__and2_1 CGAND( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(SEL), .B(WE), .X(we_wire) ); + sky130_fd_sc_hd__dlclkp_1 CG( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) ); + + generate + genvar i; + for(i=0; i<8; i=i+1) begin : BIT + sky130_fd_sc_hd__dfxtp_1 FF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) ); + sky130_fd_sc_hd__ebufn_2 OBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) ); + end + endgenerate + +endmodule + + +module WORD32 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input CLK, + input [3:0] WE, + input SEL, + input [31:0] Di, + output [31:0] Do +); + + BYTE B0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) ); + BYTE B1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) ); + BYTE B2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) ); + BYTE B3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) ); + +endmodule + +module DEC1x2 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input EN, + input [0:0] A, + output [1:0] SEL +); + sky130_fd_sc_hd__and2b_2 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[0]), .A_N(A), .B(EN) ); + sky130_fd_sc_hd__and2_2 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]), .A(A), .B(A[0]) ); + +endmodule + +module DEC2x4 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input EN, + input [1:0] A, + output [3:0] SEL +); + sky130_fd_sc_hd__nor3b_4 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) ); + sky130_fd_sc_hd__and3b_4 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) ); + sky130_fd_sc_hd__and3b_4 AND2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) ); + sky130_fd_sc_hd__and3_4 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) ); + +endmodule + +module DEC3x8 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input EN, + input [2:0] A, + output [7:0] SEL +); + sky130_fd_sc_hd__nor4b_2 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]) , .A(A[0]), .B(A[1]) , .C(A[2]), .D_N(EN) ); // 000 + sky130_fd_sc_hd__and4bb_2 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]) , .A_N(A[2]), .B_N(A[1]), .C(A[0]) , .D(EN) ); // 001 + sky130_fd_sc_hd__and4bb_2 AND2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[2]) , .A_N(A[2]), .B_N(A[0]), .C(A[1]) , .D(EN) ); // 010 + sky130_fd_sc_hd__and4b_2 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[3]) , .A_N(A[2]), .B(A[1]), .C(A[0]) , .D(EN) ); // 011 + sky130_fd_sc_hd__and4bb_2 AND4 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[4]) , .A_N(A[0]), .B_N(A[1]), .C(A[2]) , .D(EN) ); // 100 + sky130_fd_sc_hd__and4b_2 AND5 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[5]) , .A_N(A[1]), .B(A[0]), .C(A[2]) , .D(EN) ); // 101 + sky130_fd_sc_hd__and4b_2 AND6 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[6]) , .A_N(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 110 + sky130_fd_sc_hd__and4_2 AND7 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[7]) , .A(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 111 +endmodule + + +module DEC6x64 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input EN, + input [5:0] A, + output [63:0] SEL +); + wire [7:0] SEL0_w ; + wire [2:0] A_buf; + + DEC3x8 DEC_L0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), .A(A[5:3]), .SEL(SEL0_w) ); + + sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(A_buf), .A(A[2:0])); + + generate + genvar i; + for(i=0; i<8; i=i+1) begin : DEC_L1 + DEC3x8 U ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(SEL0_w[i]), .A(A_buf), .SEL(SEL[7+8*i: 8*i]) ); + end + endgenerate +endmodule + +module MUX2x1_32( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input [31:0] A0, A1, + input [0:0] S, + output [31:0] X +); + sky130_fd_sc_hd__mux2_1 MUX[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A0(A0), .A1(A1), .S(S[0]), .X(X) ); +endmodule + +module MUX4x1_32( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input [31:0] A0, A1, A2, A3, + input [1:0] S, + output [31:0] X +); + sky130_fd_sc_hd__mux4_1 MUX[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) ); +endmodule + +module PASS ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input [31:0] A, output [31:0] X); + assign X = A; +endmodule + +module SRAM64x32( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input CLK, + input [3:0] WE, + input EN, + input [31:0] Di, + output [31:0] Do, + input [5:0] A +); + + wire [63:0] SEL; + wire [31:0] Do_pre; + wire [31:0] Di_buf; + wire CLK_buf; + wire [3:0] WE_buf; + + sky130_fd_sc_hd__clkbuf_16 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Di_buf), .A(Di)); + + DEC6x64 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), .A(A), .SEL(SEL) ); + + generate + genvar i; + for (i=0; i< 64; i=i+1) begin : WORD + WORD32 W ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) ); + end + endgenerate + + // Ensure that the Do_pre lines are not floating when EN = 0 + wire lo; + wire float_buf_en; + sky130_fd_sc_hd__clkbuf_4 FBUFENBUF( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(float_buf_en), .A(EN) ); + sky130_fd_sc_hd__conb_1 TIE ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .LO(lo), .HI()); + sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A( lo ), .Z(Do_pre), .TE_B(float_buf_en) ); + + generate + //genvar i; + for(i=0; i<32; i=i+1) begin : OUT + sky130_fd_sc_hd__dfxtp_1 FF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) ); + end + endgenerate + +endmodule + +module DFFRAM_COL4 +( +`ifdef USE_POWER_PINS + VPWR, + VGND, +`endif + CLK, + WE, + EN, + Di, + Do, + A +); + +`ifdef USE_POWER_PINS + input VPWR; + input VGND; +`endif + input CLK; + input [3:0] WE; + input EN; + input [31:0] Di; + output [31:0] Do; + input [7:0] A; + + + wire [31:0] Di_buf; + wire [31:0] Do_pre; + wire CLK_buf; + wire [3:0] WE_buf; + wire [5:3] A_buf; + + wire [31:0] Do_B_0_0; + wire [31:0] Do_B_0_1; + wire [31:0] Do_B_0_2; + wire [31:0] Do_B_0_3; + + wire [3:0] row_sel; + + sky130_fd_sc_hd__clkbuf_8 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + + .X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Di_buf), .A(Di)); + + sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(A_buf), .A(A[5:3]) ); + + DEC2x4 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), .A(A[7:6]), .SEL(row_sel) ); + + SRAM64x32 B_0_0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A({A_buf,A[2:0]}) ); + SRAM64x32 B_0_1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A({A_buf,A[2:0]}) ); + SRAM64x32 B_0_2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A({A_buf,A[2:0]}) ); + SRAM64x32 B_0_3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A({A_buf,A[2:0]}) ); + + MUX4x1_32 MUX ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do) ); + +endmodule +
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v index 2019be0..41da41d 100644 --- a/verilog/rtl/DFFRAMBB.v +++ b/verilog/rtl/DFFRAMBB.v
@@ -14,10 +14,6 @@ */ module BYTE ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input CLK, input WE, input SEL, @@ -30,61 +26,50 @@ wire SEL_B; wire GCLK; - sky130_fd_sc_hd__inv_1 INV( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .Y(SEL_B), .A(SEL)); - sky130_fd_sc_hd__and2_1 CGAND( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .A(SEL), .B(WE), .X(we_wire) ); - sky130_fd_sc_hd__dlclkp_1 CG( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) ); - + sky130_fd_sc_hd__inv_1 INV(.Y(SEL_B), .A(SEL)); + sky130_fd_sc_hd__and2_1 CGAND( .A(SEL), .B(WE), .X(we_wire) ); + sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) ); generate genvar i; for(i=0; i<8; i=i+1) begin : BIT - sky130_fd_sc_hd__dfxtp_1 FF ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) ); - sky130_fd_sc_hd__ebufn_2 OBUF ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) ); + sky130_fd_sc_hd__dfxtp_1 FF ( .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) ); + sky130_fd_sc_hd__ebufn_2 OBUF ( .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) ); end endgenerate endmodule +module BYTE_LATCH ( + input CLK, + input WE, + input SEL, + input [7:0] Di, + output [7:0] Do +); -module WORD32 ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif + wire [7:0] q_wire; + wire we_wire; + wire SEL_B; + wire GCLK; + wire CLK_B; + + sky130_fd_sc_hd__inv_1 SELINV(.Y(SEL_B), .A(SEL)); + sky130_fd_sc_hd__inv_1 CLKINV(.Y(CLK_B), .A(CLK)); + sky130_fd_sc_hd__and2_1 CGAND( .A(SEL), .B(WE), .X(we_wire) ); + sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK_B), .GCLK(GCLK), .GATE(we_wire) ); + + generate + genvar i; + for(i=0; i<8; i=i+1) begin : BIT + //sky130_fd_sc_hd__dfxtp_1 FF ( .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) ); + sky130_fd_sc_hd__dlxtp_1 LATCH (.Q(q_wire[i]), .D(Di[i]), .GATE(GCLK) ); + sky130_fd_sc_hd__ebufn_2 OBUF ( .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) ); + end + endgenerate + +endmodule + +module WORD32 #(parameter USE_LATCH=1)( input CLK, input [3:0] WE, input SEL, @@ -92,186 +77,66 @@ output [31:0] Do ); - BYTE B0 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) ); - BYTE B1 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) ); - BYTE B2 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) ); - BYTE B3 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) ); - + generate + if(USE_LATCH == 1) begin + BYTE_LATCH B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) ); + BYTE_LATCH B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) ); + BYTE_LATCH B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) ); + BYTE_LATCH B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) ); + end else begin + BYTE B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) ); + BYTE B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) ); + BYTE B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) ); + BYTE B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) ); + end + endgenerate endmodule module DEC1x2 ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input EN, input [0:0] A, output [1:0] SEL ); - sky130_fd_sc_hd__and2b_2 AND1 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[0]), .A_N(A), .B(EN) ); - sky130_fd_sc_hd__and2_2 AND3 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[1]), .A(A), .B(A[0]) ); + sky130_fd_sc_hd__and2b_2 AND1 ( .X(SEL[0]), .A_N(A), .B(EN) ); + sky130_fd_sc_hd__and2_2 AND3 ( .X(SEL[1]), .A(A), .B(A[0]) ); endmodule module DEC2x4 ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input EN, input [1:0] A, output [3:0] SEL ); - sky130_fd_sc_hd__nor3b_4 AND0 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) ); - sky130_fd_sc_hd__and3b_4 AND1 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) ); - sky130_fd_sc_hd__and3b_4 AND2 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) ); - sky130_fd_sc_hd__and3_4 AND3 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) ); + sky130_fd_sc_hd__nor3b_4 AND0 ( .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) ); + sky130_fd_sc_hd__and3b_4 AND1 ( .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) ); + sky130_fd_sc_hd__and3b_4 AND2 ( .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) ); + sky130_fd_sc_hd__and3_4 AND3 ( .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) ); endmodule module DEC3x8 ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input EN, input [2:0] A, output [7:0] SEL ); - sky130_fd_sc_hd__nor4b_2 AND0 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .Y(SEL[0]) , .A(A[0]), .B(A[1]) , .C(A[2]), .D_N(EN) ); // 000 - sky130_fd_sc_hd__and4bb_2 AND1 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[1]) , .A_N(A[2]), .B_N(A[1]), .C(A[0]) , .D(EN) ); // 001 - sky130_fd_sc_hd__and4bb_2 AND2 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[2]) , .A_N(A[2]), .B_N(A[0]), .C(A[1]) , .D(EN) ); // 010 - sky130_fd_sc_hd__and4b_2 AND3 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[3]) , .A_N(A[2]), .B(A[1]), .C(A[0]) , .D(EN) ); // 011 - sky130_fd_sc_hd__and4bb_2 AND4 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[4]) , .A_N(A[0]), .B_N(A[1]), .C(A[2]) , .D(EN) ); // 100 - sky130_fd_sc_hd__and4b_2 AND5 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[5]) , .A_N(A[1]), .B(A[0]), .C(A[2]) , .D(EN) ); // 101 - sky130_fd_sc_hd__and4b_2 AND6 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[6]) , .A_N(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 110 - sky130_fd_sc_hd__and4_2 AND7 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(SEL[7]) , .A(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 111 + + wire [2:0] A_buf; + wire EN_buf; + + sky130_fd_sc_hd__clkbuf_1 ABUF[2:0] (.X(A_buf), .A(A)); + sky130_fd_sc_hd__clkbuf_2 ENBUF (.X(EN_buf), .A(EN)); + + sky130_fd_sc_hd__nor4b_2 AND0 ( .Y(SEL[0]) , .A(A_buf[0]), .B(A_buf[1]) , .C(A_buf[2]), .D_N(EN_buf) ); // 000 + sky130_fd_sc_hd__and4bb_2 AND1 ( .X(SEL[1]) , .A_N(A_buf[2]), .B_N(A_buf[1]), .C(A_buf[0]) , .D(EN_buf) ); // 001 + sky130_fd_sc_hd__and4bb_2 AND2 ( .X(SEL[2]) , .A_N(A_buf[2]), .B_N(A_buf[0]), .C(A_buf[1]) , .D(EN_buf) ); // 010 + sky130_fd_sc_hd__and4b_2 AND3 ( .X(SEL[3]) , .A_N(A_buf[2]), .B(A_buf[1]), .C(A_buf[0]) , .D(EN_buf) ); // 011 + sky130_fd_sc_hd__and4bb_2 AND4 ( .X(SEL[4]) , .A_N(A_buf[0]), .B_N(A_buf[1]), .C(A_buf[2]) , .D(EN_buf) ); // 100 + sky130_fd_sc_hd__and4b_2 AND5 ( .X(SEL[5]) , .A_N(A_buf[1]), .B(A_buf[0]), .C(A_buf[2]) , .D(EN_buf) ); // 101 + sky130_fd_sc_hd__and4b_2 AND6 ( .X(SEL[6]) , .A_N(A_buf[0]), .B(A_buf[1]), .C(A_buf[2]) , .D(EN_buf) ); // 110 + sky130_fd_sc_hd__and4_2 AND7 ( .X(SEL[7]) , .A(A_buf[0]), .B(A_buf[1]), .C(A_buf[2]) , .D(EN_buf) ); // 111 endmodule - module DEC6x64 ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input EN, input [5:0] A, output [63:0] SEL @@ -279,87 +144,116 @@ wire [7:0] SEL0_w ; wire [2:0] A_buf; - DEC3x8 DEC_L0 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .EN(EN), .A(A[5:3]), .SEL(SEL0_w) ); + DEC3x8 DEC_L0 ( .EN(EN), .A(A[5:3]), .SEL(SEL0_w) ); - sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(A_buf), .A(A[2:0])); + sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (.X(A_buf), .A(A[2:0])); generate genvar i; for(i=0; i<8; i=i+1) begin : DEC_L1 - DEC3x8 U ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .EN(SEL0_w[i]), .A(A_buf), .SEL(SEL[7+8*i: 8*i]) ); + DEC3x8 U ( .EN(SEL0_w[i]), .A(A_buf), .SEL(SEL[7+8*i: 8*i]) ); end endgenerate endmodule module MUX2x1_32( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input [31:0] A0, A1, input [0:0] S, output [31:0] X ); - sky130_fd_sc_hd__mux2_1 MUX[31:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .A0(A0), .A1(A1), .S(S[0]), .X(X) ); + sky130_fd_sc_hd__mux2_1 MUX[31:0] (.A0(A0), .A1(A1), .S(S[0]), .X(X) ); endmodule module MUX4x1_32( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif input [31:0] A0, A1, A2, A3, input [1:0] S, output [31:0] X ); - sky130_fd_sc_hd__mux4_1 MUX[31:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) ); + sky130_fd_sc_hd__mux4_1 MUX[31:0] (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) ); endmodule -module PASS ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif - input [31:0] A, output [31:0] X); +module PASS (input [31:0] A, output [31:0] X); assign X = A; endmodule -module SRAM64x32( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif +module SRAM8x32 #(parameter USE_LATCH=0) ( + input CLK, + input [3:0] WE, + input EN, + input [31:0] Di, + output [31:0] Do, + input [2:0] A +); + + wire [7:0] SEL, SEL_buf, CLK_buf; + wire [3:0] WE_buf[7:0]; // WE_buf! + + DEC3x8 DEC (.EN(EN), .A(A), .SEL(SEL)); + sky130_fd_sc_hd__clkbuf_2 SELBUF[7:0] (.X(SEL_buf), .A(SEL)); + + generate + genvar i; + for (i=0; i< 8; i=i+1) begin : WORD + WORD32 #(.USE_LATCH(USE_LATCH)) W ( .CLK(CLK_buf[i]), .WE(WE_buf[i]), .SEL(SEL_buf[i]), .Di(Di), .Do(Do) ); + sky130_fd_sc_hd__clkbuf_1 CLKBUF (.X(CLK_buf[i]), .A(CLK)); + sky130_fd_sc_hd__clkbuf_1 WEBUF[3:0] (.X(WE_buf[i]), .A(WE)); + end + endgenerate + +endmodule + +module SRAM64x32 #(parameter USE_LATCH=0) ( + input CLK, + input [3:0] WE, + input EN, + input [31:0] Di, + output [31:0] Do, + input [5:0] A +); + wire [7:0] SEL; + wire [2:0] A_buf; + wire CLK_buf; + wire [3:0] WE_buf; + + wire [31:0] Do_pre; + wire [31:0] Di_buf; + + sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (.X(Di_buf), .A(Di)); + + sky130_fd_sc_hd__clkbuf_2 CLKBUF (.X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_2 WEBUF[3:0] (.X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_1 ABUF[2:0] (.X(A_buf), .A(A[2:0])); + + DEC3x8 DEC (.EN(EN), .A(A[5:3]), .SEL(SEL)); + + generate + genvar i; + for (i=0; i< 8; i=i+1) begin : SLICE + SRAM8x32 #(.USE_LATCH(USE_LATCH)) RAM8x32 (.CLK(CLK_buf), .WE(WE_buf),.EN(SEL[i]), .Di(Di_buf), .Do(Do_pre), .A(A_buf) ); + end + endgenerate + + // Ensure that the Do_pre lines are not floating when EN = 0 + wire [3:0] lo; + wire [3:0] float_buf_en; + sky130_fd_sc_hd__clkbuf_4 FBUFENBUF [3:0] ( .X(float_buf_en), .A(EN) ); + sky130_fd_sc_hd__conb_1 TIE [3:0] (.LO(lo), .HI()); + sky130_fd_sc_hd__ebufn_2 FLOATBUF_B0[7:0] ( .A( lo[0] ), .Z(Do_pre[7:0]), .TE_B(float_buf_en[0]) ); + sky130_fd_sc_hd__ebufn_2 FLOATBUF_B1[15:8] ( .A( lo[1] ), .Z(Do_pre[15:8]), .TE_B(float_buf_en[1]) ); + sky130_fd_sc_hd__ebufn_2 FLOATBUF_B2[23:16] ( .A( lo[2] ), .Z(Do_pre[23:16]), .TE_B(float_buf_en[2]) ); + sky130_fd_sc_hd__ebufn_2 FLOATBUF_B3[31:24] ( .A( lo[3] ), .Z(Do_pre[31:24]), .TE_B(float_buf_en[3]) ); + + generate + //genvar i; + for(i=0; i<32; i=i+1) begin : OUT + sky130_fd_sc_hd__dfxtp_1 FF ( .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) ); + end + endgenerate + +endmodule + +/* +module SRAM64x32 #(parameter USE_LATCH=0) ( input CLK, input [3:0] WE, input EN, @@ -374,100 +268,37 @@ wire CLK_buf; wire [3:0] WE_buf; - sky130_fd_sc_hd__clkbuf_16 CLKBUF ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(CLK_buf), .A(CLK)); - sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(WE_buf), .A(WE)); - sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(Di_buf), .A(Di)); + sky130_fd_sc_hd__clkbuf_16 CLKBUF (.X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (.X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (.X(Di_buf), .A(Di)); - DEC6x64 DEC ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .EN(EN), .A(A), .SEL(SEL) ); + DEC6x64 DEC ( .EN(EN), .A(A), .SEL(SEL) ); generate genvar i; for (i=0; i< 64; i=i+1) begin : WORD - WORD32 W ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) ); + WORD32 #(.USE_LATCH(USE_LATCH)) W ( .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) ); end endgenerate // Ensure that the Do_pre lines are not floating when EN = 0 wire lo; wire float_buf_en; - sky130_fd_sc_hd__clkbuf_4 FBUFENBUF( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(float_buf_en), .A(EN) ); - sky130_fd_sc_hd__conb_1 TIE ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .LO(lo), .HI()); - sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .A( lo ), .Z(Do_pre), .TE_B(float_buf_en) ); + sky130_fd_sc_hd__clkbuf_4 FBUFENBUF( .X(float_buf_en), .A(EN) ); + sky130_fd_sc_hd__conb_1 TIE (.LO(lo), .HI()); + sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( .A( lo ), .Z(Do_pre), .TE_B(float_buf_en) ); generate //genvar i; for(i=0; i<32; i=i+1) begin : OUT - sky130_fd_sc_hd__dfxtp_1 FF ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) ); + sky130_fd_sc_hd__dfxtp_1 FF ( .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) ); end endgenerate endmodule - -module DFFRAM_COL4 +*/ +module DFFRAM_COL4 #( parameter USE_LATCH=0 ) ( -`ifdef USE_POWER_PINS - VPWR, - VGND, -`endif CLK, WE, EN, @@ -475,11 +306,6 @@ Do, A ); - -`ifdef USE_POWER_PINS - input VPWR; - input VGND; -`endif input CLK; input [3:0] WE; input EN; @@ -487,12 +313,11 @@ output [31:0] Do; input [7:0] A; - wire [31:0] Di_buf; wire [31:0] Do_pre; wire CLK_buf; wire [3:0] WE_buf; - wire [5:3] A_buf; + wire [7:0] A_buf; wire [31:0] Do_B_0_0; wire [31:0] Do_B_0_1; @@ -501,79 +326,20 @@ wire [3:0] row_sel; - sky130_fd_sc_hd__clkbuf_8 CLKBUF ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif + sky130_fd_sc_hd__clkbuf_4 CLKBUF (.X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_4 WEBUF[3:0] (.X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (.X(Di_buf), .A(Di)); - .X(CLK_buf), .A(CLK)); - sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(WE_buf), .A(WE)); - sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(Di_buf), .A(Di)); + sky130_fd_sc_hd__clkbuf_8 ABUF[7:0] ( .X(A_buf), .A(A[7:0]) ); + + DEC2x4 DEC ( .EN(EN), .A(A[7:6]), .SEL(row_sel) ); - sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND), - `endif - .X(A_buf), .A(A[5:3]) ); - - DEC2x4 DEC ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .EN(EN), .A(A[7:6]), .SEL(row_sel) ); + SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_0 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A(A_buf[5:0]) ); + SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_1 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A(A_buf[5:0]) ); + SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_2 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A(A_buf[5:0]) ); + SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_3 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A(A_buf[5:0]) ); - SRAM64x32 B_0_0 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A({A_buf,A[2:0]}) ); - SRAM64x32 B_0_1 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A({A_buf,A[2:0]}) ); - SRAM64x32 B_0_2 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A({A_buf,A[2:0]}) ); - SRAM64x32 B_0_3 ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A({A_buf,A[2:0]}) ); - - MUX4x1_32 MUX ( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - `endif - .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do) ); + MUX4x1_32 MUX ( .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A_buf[7:6]), .X(Do) ); endmodule
diff --git a/verilog/rtl/DFFRAM_4KB.v b/verilog/rtl/DFFRAM_4KB-.v similarity index 100% rename from verilog/rtl/DFFRAM_4KB.v rename to verilog/rtl/DFFRAM_4KB-.v