commit: 0b4f5da0f4f58a5945f63215fdddb5a623506bc6
[log] [tgz]
author: Mohamed Shalan <mshalan@aucegypt.edu>
Wed Jan 20 16:06:05 2021 +0200
committer: Mohamed Shalan <mshalan@aucegypt.edu>
Wed Jan 20 16:06:05 2021 +0200
tree: 7e5e41f638182d238fe762f98a9b5badf1dff4aa
parent: e2a3da9ae85991c46eb7dbe972aa1302e7f091ad [diff]

Migrated to the latest DFFRAM

verilog/rtl/DFFRAM _4KB.v[Added - diff]
verilog/rtl/DFFRAM-.v[Added - diff]
verilog/rtl/DFFRAM.v[diff]
verilog/rtl/DFFRAMBB-.v[Added - diff]
verilog/rtl/DFFRAMBB.v[diff]
verilog/rtl/DFFRAM_4KB-.v[Renamed from verilog/rtl/DFFRAM_4KB.v - diff]

6 files changed

tree: 7e5e41f638182d238fe762f98a9b5badf1dff4aa

README.md

Caravel Plus

Caravel management SoC attached to the largest possible SRAM that can fit the user's area.