Fixed errors found during gatelevel simulation. Updated GDS.
diff --git a/def/efuse_ctrl.def.gz b/def/efuse_ctrl.def.gz index a414355..2b29f54 100644 --- a/def/efuse_ctrl.def.gz +++ b/def/efuse_ctrl.def.gz Binary files differ
diff --git a/def/fpga_struct_block.def.gz b/def/fpga_struct_block.def.gz index 1cfb286..b54585d 100644 --- a/def/fpga_struct_block.def.gz +++ b/def/fpga_struct_block.def.gz Binary files differ
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz index e263a57..99391fe 100644 --- a/def/user_project_wrapper.def.gz +++ b/def/user_project_wrapper.def.gz Binary files differ
diff --git a/gds/efuse_ctrl.gds.gz b/gds/efuse_ctrl.gds.gz index f0d894c..4fbd4e2 100644 --- a/gds/efuse_ctrl.gds.gz +++ b/gds/efuse_ctrl.gds.gz Binary files differ
diff --git a/gds/fpga_struct_block.gds.gz b/gds/fpga_struct_block.gds.gz index d6e26ef..ba41818 100644 --- a/gds/fpga_struct_block.gds.gz +++ b/gds/fpga_struct_block.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index b8ae994..e071acb 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/efuse_ctrl.lef b/lef/efuse_ctrl.lef index 70de3cb..8892c02 100644 --- a/lef/efuse_ctrl.lef +++ b/lef/efuse_ctrl.lef
@@ -6,429 +6,429 @@ CLASS BLOCK ; FOREIGN efuse_ctrl ; ORIGIN 0.000 0.000 ; - SIZE 2175.000 BY 2350.000 ; + SIZE 2175.000 BY 2370.000 ; PIN VDD DIRECTION INOUT ; USE POWER ; PORT LAYER Metal4 ; - RECT 25.920 15.380 27.520 2332.700 ; + RECT 25.920 15.380 27.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 215.920 15.380 217.520 29.720 ; + RECT 215.920 15.380 217.520 49.720 ; END PORT LAYER Metal4 ; - RECT 215.920 768.115 217.520 789.720 ; + RECT 215.920 788.115 217.520 809.720 ; END PORT LAYER Metal4 ; - RECT 215.920 1528.115 217.520 1549.720 ; + RECT 215.920 1548.115 217.520 1569.720 ; END PORT LAYER Metal4 ; - RECT 215.920 2288.115 217.520 2332.700 ; + RECT 215.920 2308.115 217.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 405.920 15.380 407.520 32.245 ; + RECT 405.920 15.380 407.520 52.245 ; END PORT LAYER Metal4 ; - RECT 405.920 767.505 407.520 792.245 ; + RECT 405.920 787.505 407.520 812.245 ; END PORT LAYER Metal4 ; - RECT 405.920 1527.505 407.520 1552.245 ; + RECT 405.920 1547.505 407.520 1572.245 ; END PORT LAYER Metal4 ; - RECT 405.920 2287.505 407.520 2332.700 ; + RECT 405.920 2307.505 407.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 595.920 15.380 597.520 32.270 ; + RECT 595.920 15.380 597.520 52.270 ; END PORT LAYER Metal4 ; - RECT 595.920 767.505 597.520 792.270 ; + RECT 595.920 787.505 597.520 812.270 ; END PORT LAYER Metal4 ; - RECT 595.920 1527.505 597.520 1552.270 ; + RECT 595.920 1547.505 597.520 1572.270 ; END PORT LAYER Metal4 ; - RECT 595.920 2287.505 597.520 2332.700 ; + RECT 595.920 2307.505 597.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 785.920 15.380 787.520 32.270 ; + RECT 785.920 15.380 787.520 52.270 ; END PORT LAYER Metal4 ; - RECT 785.920 767.530 787.520 792.270 ; + RECT 785.920 787.530 787.520 812.270 ; END PORT LAYER Metal4 ; - RECT 785.920 1527.530 787.520 1552.270 ; + RECT 785.920 1547.530 787.520 1572.270 ; END PORT LAYER Metal4 ; - RECT 785.920 2287.530 787.520 2332.700 ; + RECT 785.920 2307.530 787.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 975.920 15.380 977.520 32.245 ; + RECT 975.920 15.380 977.520 52.245 ; END PORT LAYER Metal4 ; - RECT 975.920 767.505 977.520 792.245 ; + RECT 975.920 787.505 977.520 812.245 ; END PORT LAYER Metal4 ; - RECT 975.920 1527.505 977.520 1552.245 ; + RECT 975.920 1547.505 977.520 1572.245 ; END PORT LAYER Metal4 ; - RECT 975.920 2287.505 977.520 2332.700 ; + RECT 975.920 2307.505 977.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 1165.920 15.380 1167.520 2332.700 ; + RECT 1165.920 15.380 1167.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 1355.920 15.380 1357.520 2332.700 ; + RECT 1355.920 15.380 1357.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 1545.920 15.380 1547.520 29.720 ; + RECT 1545.920 15.380 1547.520 49.720 ; END PORT LAYER Metal4 ; - RECT 1545.920 767.530 1547.520 789.720 ; + RECT 1545.920 787.530 1547.520 809.720 ; END PORT LAYER Metal4 ; - RECT 1545.920 1527.530 1547.520 1549.720 ; + RECT 1545.920 1547.530 1547.520 1569.720 ; END PORT LAYER Metal4 ; - RECT 1545.920 2287.530 1547.520 2332.700 ; + RECT 1545.920 2307.530 1547.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 1735.920 15.380 1737.520 32.270 ; + RECT 1735.920 15.380 1737.520 52.270 ; END PORT LAYER Metal4 ; - RECT 1735.920 767.505 1737.520 792.270 ; + RECT 1735.920 787.505 1737.520 812.270 ; END PORT LAYER Metal4 ; - RECT 1735.920 1527.505 1737.520 1552.270 ; + RECT 1735.920 1547.505 1737.520 1572.270 ; END PORT LAYER Metal4 ; - RECT 1735.920 2287.505 1737.520 2332.700 ; + RECT 1735.920 2307.505 1737.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 1925.920 15.380 1927.520 32.270 ; + RECT 1925.920 15.380 1927.520 52.270 ; END PORT LAYER Metal4 ; - RECT 1925.920 767.505 1927.520 792.270 ; + RECT 1925.920 787.505 1927.520 812.270 ; END PORT LAYER Metal4 ; - RECT 1925.920 1527.505 1927.520 1552.270 ; + RECT 1925.920 1547.505 1927.520 1572.270 ; END PORT LAYER Metal4 ; - RECT 1925.920 2287.505 1927.520 2332.700 ; + RECT 1925.920 2307.505 1927.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 2115.920 15.380 2117.520 32.245 ; + RECT 2115.920 15.380 2117.520 52.270 ; END PORT LAYER Metal4 ; - RECT 2115.920 767.530 2117.520 792.245 ; + RECT 2115.920 787.530 2117.520 812.270 ; END PORT LAYER Metal4 ; - RECT 2115.920 1527.530 2117.520 1552.245 ; + RECT 2115.920 1547.530 2117.520 1572.270 ; END PORT LAYER Metal4 ; - RECT 2115.920 2287.530 2117.520 2332.700 ; + RECT 2115.920 2307.530 2117.520 2352.300 ; END PORT LAYER Metal4 ; - RECT 110.360 23.220 111.960 772.540 ; + RECT 110.360 42.820 111.960 792.140 ; END PORT LAYER Metal4 ; - RECT 198.280 783.700 199.880 1533.020 ; + RECT 198.280 803.300 199.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 286.200 1544.180 287.800 2293.500 ; + RECT 286.200 1563.780 287.800 2313.100 ; END PORT LAYER Metal4 ; - RECT 110.360 783.700 111.960 1533.020 ; + RECT 110.360 803.300 111.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 198.280 23.220 199.880 772.540 ; + RECT 198.280 42.820 199.880 792.140 ; END PORT LAYER Metal4 ; - RECT 374.120 1544.180 375.720 2293.500 ; + RECT 374.120 1563.780 375.720 2313.100 ; END PORT LAYER Metal4 ; - RECT 110.360 1544.180 111.960 2293.500 ; + RECT 110.360 1563.780 111.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 286.200 23.220 287.800 772.540 ; + RECT 286.200 42.820 287.800 792.140 ; END PORT LAYER Metal4 ; - RECT 374.120 783.700 375.720 1533.020 ; + RECT 374.120 803.300 375.720 1552.620 ; END PORT LAYER Metal4 ; - RECT 198.280 1544.180 199.880 2293.500 ; + RECT 198.280 1563.780 199.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 286.200 783.700 287.800 1533.020 ; + RECT 286.200 803.300 287.800 1552.620 ; END PORT LAYER Metal4 ; - RECT 374.120 23.220 375.720 772.540 ; + RECT 374.120 42.820 375.720 792.140 ; END PORT LAYER Metal4 ; - RECT 462.040 23.220 463.640 772.540 ; + RECT 462.600 42.820 464.200 792.140 ; END PORT LAYER Metal4 ; - RECT 549.960 783.700 551.560 1533.020 ; + RECT 550.520 803.300 552.120 1552.620 ; END PORT LAYER Metal4 ; - RECT 638.440 1544.180 640.040 2293.500 ; + RECT 638.440 1563.780 640.040 2313.100 ; END PORT LAYER Metal4 ; - RECT 462.040 783.700 463.640 1533.020 ; + RECT 462.600 803.300 464.200 1552.620 ; END PORT LAYER Metal4 ; - RECT 549.960 23.220 551.560 772.540 ; + RECT 550.520 42.820 552.120 792.140 ; END PORT LAYER Metal4 ; - RECT 726.360 1544.180 727.960 2293.500 ; + RECT 726.360 1563.780 727.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 462.040 1544.180 463.640 2293.500 ; + RECT 462.600 1563.780 464.200 2313.100 ; END PORT LAYER Metal4 ; - RECT 638.440 23.220 640.040 772.540 ; + RECT 638.440 42.820 640.040 792.140 ; END PORT LAYER Metal4 ; - RECT 726.360 783.700 727.960 1533.020 ; + RECT 726.360 803.300 727.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 549.960 1544.180 551.560 2293.500 ; + RECT 550.520 1563.780 552.120 2313.100 ; END PORT LAYER Metal4 ; - RECT 638.440 783.700 640.040 1533.020 ; + RECT 638.440 803.300 640.040 1552.620 ; END PORT LAYER Metal4 ; - RECT 726.360 23.220 727.960 772.540 ; + RECT 726.360 42.820 727.960 792.140 ; END PORT LAYER Metal4 ; - RECT 814.280 23.220 815.880 772.540 ; + RECT 814.280 42.820 815.880 792.140 ; END PORT LAYER Metal4 ; - RECT 902.200 783.700 903.800 1533.020 ; + RECT 902.200 803.300 903.800 1552.620 ; END PORT LAYER Metal4 ; - RECT 990.120 1544.180 991.720 2293.500 ; + RECT 995.160 1563.780 996.760 2309.180 ; END PORT LAYER Metal4 ; - RECT 814.280 783.700 815.880 1533.020 ; + RECT 814.280 803.300 815.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 902.200 23.220 903.800 772.540 ; + RECT 902.200 42.820 903.800 792.140 ; END PORT LAYER Metal4 ; - RECT 1078.040 1544.180 1079.640 2293.500 ; + RECT 1078.600 1563.780 1080.200 2313.100 ; END PORT LAYER Metal4 ; - RECT 814.280 1544.180 815.880 2293.500 ; + RECT 814.280 1563.780 815.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 990.120 23.220 991.720 772.540 ; + RECT 995.160 42.820 996.760 788.220 ; END PORT LAYER Metal4 ; - RECT 1078.040 783.700 1079.640 1533.020 ; + RECT 1078.600 803.300 1080.200 1552.620 ; END PORT LAYER Metal4 ; - RECT 902.200 1544.180 903.800 2293.500 ; + RECT 902.200 1563.780 903.800 2313.100 ; END PORT LAYER Metal4 ; - RECT 990.120 783.700 991.720 1533.020 ; + RECT 995.160 803.300 996.760 1548.700 ; END PORT LAYER Metal4 ; - RECT 1078.040 23.220 1079.640 772.540 ; + RECT 1078.600 42.820 1080.200 792.140 ; END PORT LAYER Metal4 ; - RECT 1254.440 23.220 1256.040 772.540 ; + RECT 1254.440 42.820 1256.040 792.140 ; END PORT LAYER Metal4 ; - RECT 1430.280 1544.180 1431.880 2293.500 ; + RECT 1430.280 1563.780 1431.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 1254.440 783.700 1256.040 1533.020 ; + RECT 1254.440 803.300 1256.040 1552.620 ; END PORT LAYER Metal4 ; - RECT 1518.200 1544.180 1519.800 2293.500 ; + RECT 1518.200 1563.780 1519.800 2313.100 ; END PORT LAYER Metal4 ; - RECT 1254.440 1544.180 1256.040 2293.500 ; + RECT 1254.440 1563.780 1256.040 2313.100 ; END PORT LAYER Metal4 ; - RECT 1430.280 23.220 1431.880 772.540 ; + RECT 1430.280 42.820 1431.880 792.140 ; END PORT LAYER Metal4 ; - RECT 1518.200 783.700 1519.800 1533.020 ; + RECT 1518.200 803.300 1519.800 1552.620 ; END PORT LAYER Metal4 ; - RECT 1430.280 783.700 1431.880 1533.020 ; + RECT 1430.280 803.300 1431.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 1518.200 23.220 1519.800 772.540 ; + RECT 1518.200 42.820 1519.800 792.140 ; END PORT LAYER Metal4 ; - RECT 1606.120 23.220 1607.720 772.540 ; + RECT 1606.120 42.820 1607.720 792.140 ; END PORT LAYER Metal4 ; - RECT 1694.040 783.700 1695.640 1533.020 ; + RECT 1694.600 803.300 1696.200 1552.620 ; END PORT LAYER Metal4 ; - RECT 1781.960 1544.180 1783.560 2293.500 ; + RECT 1782.520 1563.780 1784.120 2313.100 ; END PORT LAYER Metal4 ; - RECT 1606.120 783.700 1607.720 1533.020 ; + RECT 1606.120 803.300 1607.720 1552.620 ; END PORT LAYER Metal4 ; - RECT 1694.040 23.220 1695.640 772.540 ; + RECT 1694.600 42.820 1696.200 792.140 ; END PORT LAYER Metal4 ; - RECT 1870.440 1544.180 1872.040 2293.500 ; + RECT 1870.440 1563.780 1872.040 2313.100 ; END PORT LAYER Metal4 ; - RECT 1606.120 1544.180 1607.720 2293.500 ; + RECT 1606.120 1563.780 1607.720 2313.100 ; END PORT LAYER Metal4 ; - RECT 1781.960 23.220 1783.560 772.540 ; + RECT 1782.520 42.820 1784.120 792.140 ; END PORT LAYER Metal4 ; - RECT 1870.440 783.700 1872.040 1533.020 ; + RECT 1870.440 803.300 1872.040 1552.620 ; END PORT LAYER Metal4 ; - RECT 1694.040 1544.180 1695.640 2293.500 ; + RECT 1694.600 1563.780 1696.200 2313.100 ; END PORT LAYER Metal4 ; - RECT 1781.960 783.700 1783.560 1533.020 ; + RECT 1782.520 803.300 1784.120 1552.620 ; END PORT LAYER Metal4 ; - RECT 1870.440 23.220 1872.040 772.540 ; + RECT 1870.440 42.820 1872.040 792.140 ; END PORT LAYER Metal4 ; - RECT 1958.360 23.220 1959.960 772.540 ; + RECT 1958.360 42.820 1959.960 792.140 ; END PORT LAYER Metal4 ; - RECT 2046.280 783.700 2047.880 1533.020 ; + RECT 2046.280 803.300 2047.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 2143.720 1544.180 2145.320 2293.500 ; + RECT 2142.600 1563.780 2144.200 2313.100 ; END PORT LAYER Metal4 ; - RECT 1958.360 783.700 1959.960 1533.020 ; + RECT 1958.360 803.300 1959.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 2046.280 23.220 2047.880 772.540 ; + RECT 2046.280 42.820 2047.880 792.140 ; END PORT LAYER Metal4 ; - RECT 1958.360 1544.180 1959.960 2293.500 ; + RECT 1958.360 1563.780 1959.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 2143.720 23.220 2145.320 772.540 ; + RECT 2142.600 42.820 2144.200 792.140 ; END PORT LAYER Metal4 ; - RECT 2046.280 1544.180 2047.880 2293.500 ; + RECT 2046.280 1563.780 2047.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 2143.720 783.700 2145.320 1533.020 ; + RECT 2142.600 803.300 2144.200 1552.620 ; END END VDD PIN VSS @@ -436,443 +436,431 @@ USE GROUND ; PORT LAYER Metal4 ; - RECT 35.520 15.380 37.120 2332.700 ; + RECT 35.520 15.380 37.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 225.520 15.380 227.120 29.720 ; + RECT 225.520 15.380 227.120 49.720 ; END PORT LAYER Metal4 ; - RECT 225.520 767.530 227.120 789.720 ; + RECT 225.520 787.530 227.120 809.720 ; END PORT LAYER Metal4 ; - RECT 225.520 1527.530 227.120 1549.720 ; + RECT 225.520 1547.530 227.120 1569.720 ; END PORT LAYER Metal4 ; - RECT 225.520 2287.530 227.120 2332.700 ; + RECT 225.520 2307.530 227.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 415.520 15.380 417.120 32.270 ; + RECT 415.520 15.380 417.120 52.270 ; END PORT LAYER Metal4 ; - RECT 415.520 767.505 417.120 792.270 ; + RECT 415.520 787.505 417.120 812.270 ; END PORT LAYER Metal4 ; - RECT 415.520 1527.505 417.120 1552.270 ; + RECT 415.520 1547.505 417.120 1572.270 ; END PORT LAYER Metal4 ; - RECT 415.520 2287.505 417.120 2332.700 ; + RECT 415.520 2307.505 417.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 605.520 15.380 607.120 32.270 ; + RECT 605.520 15.380 607.120 52.270 ; END PORT LAYER Metal4 ; - RECT 605.520 767.505 607.120 792.270 ; + RECT 605.520 787.505 607.120 812.270 ; END PORT LAYER Metal4 ; - RECT 605.520 1527.505 607.120 1552.270 ; + RECT 605.520 1547.505 607.120 1572.270 ; END PORT LAYER Metal4 ; - RECT 605.520 2287.505 607.120 2332.700 ; + RECT 605.520 2307.505 607.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 795.520 15.380 797.120 32.270 ; + RECT 795.520 15.380 797.120 52.270 ; END PORT LAYER Metal4 ; - RECT 795.520 767.530 797.120 792.270 ; + RECT 795.520 787.530 797.120 812.270 ; END PORT LAYER Metal4 ; - RECT 795.520 1527.530 797.120 1552.270 ; + RECT 795.520 1547.530 797.120 1572.270 ; END PORT LAYER Metal4 ; - RECT 795.520 2287.530 797.120 2332.700 ; + RECT 795.520 2307.530 797.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 985.520 15.380 987.120 2332.700 ; + RECT 985.520 15.380 987.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 1175.520 15.380 1177.120 2332.700 ; + RECT 1175.520 15.380 1177.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 1365.520 15.380 1367.120 29.720 ; + RECT 1365.520 15.380 1367.120 49.720 ; END PORT LAYER Metal4 ; - RECT 1365.520 767.530 1367.120 789.720 ; + RECT 1365.520 787.530 1367.120 809.720 ; END PORT LAYER Metal4 ; - RECT 1365.520 1527.530 1367.120 1549.720 ; + RECT 1365.520 1547.530 1367.120 1569.720 ; END PORT LAYER Metal4 ; - RECT 1365.520 2287.530 1367.120 2332.700 ; + RECT 1365.520 2307.530 1367.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 1555.520 15.380 1557.120 32.270 ; + RECT 1555.520 15.380 1557.120 52.270 ; END PORT LAYER Metal4 ; - RECT 1555.520 767.505 1557.120 792.270 ; + RECT 1555.520 787.505 1557.120 812.270 ; END PORT LAYER Metal4 ; - RECT 1555.520 1527.505 1557.120 1552.270 ; + RECT 1555.520 1547.505 1557.120 1572.270 ; END PORT LAYER Metal4 ; - RECT 1555.520 2287.505 1557.120 2332.700 ; + RECT 1555.520 2307.505 1557.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 1745.520 15.380 1747.120 32.270 ; + RECT 1745.520 15.380 1747.120 52.270 ; END PORT LAYER Metal4 ; - RECT 1745.520 767.505 1747.120 792.270 ; + RECT 1745.520 787.505 1747.120 812.270 ; END PORT LAYER Metal4 ; - RECT 1745.520 1527.505 1747.120 1552.270 ; + RECT 1745.520 1547.505 1747.120 1572.270 ; END PORT LAYER Metal4 ; - RECT 1745.520 2287.505 1747.120 2332.700 ; + RECT 1745.520 2307.505 1747.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 1935.520 15.380 1937.120 32.270 ; + RECT 1935.520 15.380 1937.120 52.270 ; END PORT LAYER Metal4 ; - RECT 1935.520 767.530 1937.120 792.270 ; + RECT 1935.520 787.530 1937.120 812.270 ; END PORT LAYER Metal4 ; - RECT 1935.520 1527.530 1937.120 1552.270 ; + RECT 1935.520 1547.530 1937.120 1572.270 ; END PORT LAYER Metal4 ; - RECT 1935.520 2287.530 1937.120 2332.700 ; + RECT 1935.520 2307.530 1937.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 2125.520 15.380 2127.120 30.510 ; + RECT 2125.520 15.380 2127.120 50.510 ; END PORT LAYER Metal4 ; - RECT 2125.520 768.115 2127.120 790.510 ; + RECT 2125.520 788.115 2127.120 810.510 ; END PORT LAYER Metal4 ; - RECT 2125.520 1528.115 2127.120 1550.510 ; + RECT 2125.520 1548.115 2127.120 1570.510 ; END PORT LAYER Metal4 ; - RECT 2125.520 2288.115 2127.120 2332.700 ; + RECT 2125.520 2308.115 2127.120 2352.300 ; END PORT LAYER Metal4 ; - RECT 120.440 23.220 122.040 772.540 ; + RECT 120.440 42.820 122.040 792.140 ; END PORT LAYER Metal4 ; - RECT 208.360 783.700 209.960 1533.020 ; + RECT 208.360 803.300 209.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 296.280 1544.180 297.880 2293.500 ; + RECT 296.280 1563.780 297.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 120.440 783.700 122.040 1533.020 ; + RECT 120.440 803.300 122.040 1552.620 ; END PORT LAYER Metal4 ; - RECT 208.360 23.220 209.960 772.540 ; + RECT 208.360 42.820 209.960 792.140 ; END PORT LAYER Metal4 ; - RECT 384.200 1544.180 385.800 2293.500 ; + RECT 384.200 1563.780 385.800 2313.100 ; END PORT LAYER Metal4 ; - RECT 120.440 1544.180 122.040 2293.500 ; + RECT 120.440 1563.780 122.040 2313.100 ; END PORT LAYER Metal4 ; - RECT 296.280 23.220 297.880 772.540 ; + RECT 296.280 42.820 297.880 792.140 ; END PORT LAYER Metal4 ; - RECT 384.200 783.700 385.800 1533.020 ; + RECT 384.200 803.300 385.800 1552.620 ; END PORT LAYER Metal4 ; - RECT 208.360 1544.180 209.960 2293.500 ; + RECT 208.360 1563.780 209.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 296.280 783.700 297.880 1533.020 ; + RECT 296.280 803.300 297.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 384.200 23.220 385.800 772.540 ; + RECT 384.200 42.820 385.800 792.140 ; END PORT LAYER Metal4 ; - RECT 472.120 23.220 473.720 772.540 ; + RECT 472.680 42.820 474.280 792.140 ; END PORT LAYER Metal4 ; - RECT 560.040 783.700 561.640 1533.020 ; + RECT 560.600 803.300 562.200 1552.620 ; END PORT LAYER Metal4 ; - RECT 648.520 1544.180 650.120 2293.500 ; + RECT 648.520 1563.780 650.120 2313.100 ; END PORT LAYER Metal4 ; - RECT 472.120 783.700 473.720 1533.020 ; + RECT 472.680 803.300 474.280 1552.620 ; END PORT LAYER Metal4 ; - RECT 560.040 23.220 561.640 772.540 ; - END - PORT - LAYER Metal4 ; - RECT 736.440 1544.180 738.040 2293.500 ; - END - PORT - LAYER Metal4 ; - RECT 472.120 1544.180 473.720 2293.500 ; - END - PORT - LAYER Metal4 ; - RECT 648.520 23.220 650.120 772.540 ; + RECT 560.600 42.820 562.200 792.140 ; END PORT LAYER Metal4 ; - RECT 736.440 783.700 738.040 1533.020 ; + RECT 736.440 1563.780 738.040 2313.100 ; END PORT LAYER Metal4 ; - RECT 560.040 1544.180 561.640 2293.500 ; + RECT 472.680 1563.780 474.280 2313.100 ; END PORT LAYER Metal4 ; - RECT 648.520 783.700 650.120 1533.020 ; + RECT 648.520 42.820 650.120 792.140 ; END PORT LAYER Metal4 ; - RECT 736.440 23.220 738.040 772.540 ; + RECT 736.440 803.300 738.040 1552.620 ; END PORT LAYER Metal4 ; - RECT 824.360 23.220 825.960 772.540 ; + RECT 560.600 1563.780 562.200 2313.100 ; END PORT LAYER Metal4 ; - RECT 912.280 783.700 913.880 1533.020 ; + RECT 648.520 803.300 650.120 1552.620 ; END PORT LAYER Metal4 ; - RECT 1000.200 1544.180 1001.800 2293.500 ; + RECT 736.440 42.820 738.040 792.140 ; END PORT LAYER Metal4 ; - RECT 824.360 783.700 825.960 1533.020 ; + RECT 824.360 42.820 825.960 792.140 ; END PORT LAYER Metal4 ; - RECT 912.280 23.220 913.880 772.540 ; + RECT 912.280 803.300 913.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 1088.120 1544.180 1089.720 2293.500 ; + RECT 824.360 803.300 825.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 824.360 1544.180 825.960 2293.500 ; + RECT 912.280 42.820 913.880 792.140 ; END PORT LAYER Metal4 ; - RECT 1000.200 23.220 1001.800 772.540 ; + RECT 1088.680 1563.780 1090.280 2313.100 ; END PORT LAYER Metal4 ; - RECT 1088.120 783.700 1089.720 1533.020 ; + RECT 824.360 1563.780 825.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 912.280 1544.180 913.880 2293.500 ; + RECT 1088.680 803.300 1090.280 1552.620 ; END PORT LAYER Metal4 ; - RECT 1000.200 783.700 1001.800 1533.020 ; + RECT 912.280 1563.780 913.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 1088.120 23.220 1089.720 772.540 ; + RECT 1088.680 42.820 1090.280 792.140 ; END PORT LAYER Metal4 ; - RECT 1264.520 23.220 1266.120 772.540 ; + RECT 1264.520 42.820 1266.120 792.140 ; END PORT LAYER Metal4 ; - RECT 1347.400 783.700 1349.000 1529.100 ; + RECT 1346.840 807.220 1348.440 1552.620 ; END PORT LAYER Metal4 ; - RECT 1440.360 1544.180 1441.960 2293.500 ; + RECT 1440.360 1563.780 1441.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 1264.520 783.700 1266.120 1533.020 ; + RECT 1264.520 803.300 1266.120 1552.620 ; END PORT LAYER Metal4 ; - RECT 1347.400 23.220 1349.000 768.620 ; + RECT 1346.840 46.740 1348.440 792.140 ; END PORT LAYER Metal4 ; - RECT 1528.280 1544.180 1529.880 2293.500 ; + RECT 1528.280 1563.780 1529.880 2313.100 ; END PORT LAYER Metal4 ; - RECT 1264.520 1544.180 1266.120 2293.500 ; + RECT 1264.520 1563.780 1266.120 2313.100 ; END PORT LAYER Metal4 ; - RECT 1440.360 23.220 1441.960 772.540 ; + RECT 1440.360 42.820 1441.960 792.140 ; END PORT LAYER Metal4 ; - RECT 1528.280 783.700 1529.880 1533.020 ; + RECT 1528.280 803.300 1529.880 1552.620 ; END PORT LAYER Metal4 ; - RECT 1347.400 1544.180 1349.000 2289.580 ; + RECT 1346.840 1567.700 1348.440 2313.100 ; END PORT LAYER Metal4 ; - RECT 1440.360 783.700 1441.960 1533.020 ; + RECT 1440.360 803.300 1441.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 1528.280 23.220 1529.880 772.540 ; + RECT 1528.280 42.820 1529.880 792.140 ; END PORT LAYER Metal4 ; - RECT 1616.200 23.220 1617.800 772.540 ; + RECT 1616.200 42.820 1617.800 792.140 ; END PORT LAYER Metal4 ; - RECT 1704.120 783.700 1705.720 1533.020 ; + RECT 1704.680 803.300 1706.280 1552.620 ; END PORT LAYER Metal4 ; - RECT 1792.040 1544.180 1793.640 2293.500 ; + RECT 1792.600 1563.780 1794.200 2313.100 ; END PORT LAYER Metal4 ; - RECT 1616.200 783.700 1617.800 1533.020 ; + RECT 1616.200 803.300 1617.800 1552.620 ; END PORT LAYER Metal4 ; - RECT 1704.120 23.220 1705.720 772.540 ; + RECT 1704.680 42.820 1706.280 792.140 ; END PORT LAYER Metal4 ; - RECT 1880.520 1544.180 1882.120 2293.500 ; + RECT 1880.520 1563.780 1882.120 2313.100 ; END PORT LAYER Metal4 ; - RECT 1616.200 1544.180 1617.800 2293.500 ; + RECT 1616.200 1563.780 1617.800 2313.100 ; END PORT LAYER Metal4 ; - RECT 1792.040 23.220 1793.640 772.540 ; + RECT 1792.600 42.820 1794.200 792.140 ; END PORT LAYER Metal4 ; - RECT 1880.520 783.700 1882.120 1533.020 ; + RECT 1880.520 803.300 1882.120 1552.620 ; END PORT LAYER Metal4 ; - RECT 1704.120 1544.180 1705.720 2293.500 ; + RECT 1704.680 1563.780 1706.280 2313.100 ; END PORT LAYER Metal4 ; - RECT 1792.040 783.700 1793.640 1533.020 ; + RECT 1792.600 803.300 1794.200 1552.620 ; END PORT LAYER Metal4 ; - RECT 1880.520 23.220 1882.120 772.540 ; + RECT 1880.520 42.820 1882.120 792.140 ; END PORT LAYER Metal4 ; - RECT 1968.440 23.220 1970.040 772.540 ; + RECT 1968.440 42.820 1970.040 792.140 ; END PORT LAYER Metal4 ; - RECT 2056.360 783.700 2057.960 1533.020 ; + RECT 2056.360 803.300 2057.960 1552.620 ; END PORT LAYER Metal4 ; - RECT 2153.800 1544.180 2155.400 2293.500 ; + RECT 2152.680 1563.780 2154.280 2313.100 ; END PORT LAYER Metal4 ; - RECT 1968.440 783.700 1970.040 1533.020 ; + RECT 1968.440 803.300 1970.040 1552.620 ; END PORT LAYER Metal4 ; - RECT 2056.360 23.220 2057.960 772.540 ; + RECT 2056.360 42.820 2057.960 792.140 ; END PORT LAYER Metal4 ; - RECT 1968.440 1544.180 1970.040 2293.500 ; + RECT 1968.440 1563.780 1970.040 2313.100 ; END PORT LAYER Metal4 ; - RECT 2153.800 23.220 2155.400 772.540 ; + RECT 2152.680 42.820 2154.280 792.140 ; END PORT LAYER Metal4 ; - RECT 2056.360 1544.180 2057.960 2293.500 ; + RECT 2056.360 1563.780 2057.960 2313.100 ; END PORT LAYER Metal4 ; - RECT 2153.800 783.700 2155.400 1533.020 ; + RECT 2152.680 803.300 2154.280 1552.620 ; END END VSS PIN wb_ack_o DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 547.680 4.000 548.240 ; + LAYER Metal2 ; + RECT 1884.960 0.000 1885.520 4.000 ; END END wb_ack_o PIN wb_adr_i[0] @@ -880,15 +868,23 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 2039.520 2346.000 2040.080 2349.000 ; + RECT 33.600 0.000 34.160 4.000 ; END END wb_adr_i[0] + PIN wb_adr_i[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER Metal2 ; + RECT 672.000 0.000 672.560 4.000 ; + END + END wb_adr_i[10] PIN wb_adr_i[1] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1095.360 1.000 1095.920 4.000 ; + RECT 97.440 0.000 98.000 4.000 ; END END wb_adr_i[1] PIN wb_adr_i[2] @@ -896,23 +892,23 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 665.280 2346.000 665.840 2349.000 ; + RECT 161.280 0.000 161.840 4.000 ; END END wb_adr_i[2] PIN wb_adr_i[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 823.200 4.000 823.760 ; + LAYER Metal2 ; + RECT 225.120 0.000 225.680 4.000 ; END END wb_adr_i[3] PIN wb_adr_i[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 840.000 2174.000 840.560 ; + LAYER Metal2 ; + RECT 288.960 0.000 289.520 4.000 ; END END wb_adr_i[4] PIN wb_adr_i[5] @@ -920,23 +916,23 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1216.320 2346.000 1216.880 2349.000 ; + RECT 352.800 0.000 353.360 4.000 ; END END wb_adr_i[5] PIN wb_adr_i[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 16.800 2174.000 17.360 ; + LAYER Metal2 ; + RECT 416.640 0.000 417.200 4.000 ; END END wb_adr_i[6] PIN wb_adr_i[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 1391.040 2174.000 1391.600 ; + LAYER Metal2 ; + RECT 480.480 0.000 481.040 4.000 ; END END wb_adr_i[7] PIN wb_adr_i[8] @@ -944,23 +940,23 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1918.560 1.000 1919.120 4.000 ; + RECT 544.320 0.000 544.880 4.000 ; END END wb_adr_i[8] PIN wb_adr_i[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 1663.200 2174.000 1663.760 ; + LAYER Metal2 ; + RECT 608.160 0.000 608.720 4.000 ; END END wb_adr_i[9] PIN wb_clk_i DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 272.160 4.000 272.720 ; + LAYER Metal2 ; + RECT 2076.480 0.000 2077.040 4.000 ; END END wb_clk_i PIN wb_cyc_i @@ -968,7 +964,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 0.000 1.000 0.560 4.000 ; + RECT 2012.640 0.000 2013.200 4.000 ; END END wb_cyc_i PIN wb_dat_i[0] @@ -976,7 +972,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1488.480 2346.000 1489.040 2349.000 ; + RECT 1246.560 0.000 1247.120 4.000 ; END END wb_dat_i[0] PIN wb_dat_i[1] @@ -984,15 +980,15 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1764.000 2346.000 1764.560 2349.000 ; + RECT 1310.400 0.000 1310.960 4.000 ; END END wb_dat_i[1] PIN wb_dat_i[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 1646.400 4.000 1646.960 ; + LAYER Metal2 ; + RECT 1374.240 0.000 1374.800 4.000 ; END END wb_dat_i[2] PIN wb_dat_i[3] @@ -1000,7 +996,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 389.760 2346.000 390.320 2349.000 ; + RECT 1438.080 0.000 1438.640 4.000 ; END END wb_dat_i[3] PIN wb_dat_i[4] @@ -1008,23 +1004,23 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1646.400 1.000 1646.960 4.000 ; + RECT 1501.920 0.000 1502.480 4.000 ; END END wb_dat_i[4] PIN wb_dat_i[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 1918.560 4.000 1919.120 ; + LAYER Metal2 ; + RECT 1565.760 0.000 1566.320 4.000 ; END END wb_dat_i[5] PIN wb_dat_i[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 292.320 2174.000 292.880 ; + LAYER Metal2 ; + RECT 1629.600 0.000 1630.160 4.000 ; END END wb_dat_i[6] PIN wb_dat_i[7] @@ -1032,7 +1028,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 272.160 1.000 272.720 4.000 ; + RECT 1693.440 0.000 1694.000 4.000 ; END END wb_dat_i[7] PIN wb_dat_o[0] @@ -1040,7 +1036,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 547.680 1.000 548.240 4.000 ; + RECT 735.840 0.000 736.400 4.000 ; END END wb_dat_o[0] PIN wb_dat_o[1] @@ -1048,15 +1044,15 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 117.600 2346.000 118.160 2349.000 ; + RECT 799.680 0.000 800.240 4.000 ; END END wb_dat_o[1] PIN wb_dat_o[2] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 564.480 2174.000 565.040 ; + LAYER Metal2 ; + RECT 863.520 0.000 864.080 4.000 ; END END wb_dat_o[2] PIN wb_dat_o[3] @@ -1064,31 +1060,31 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 823.200 1.000 823.760 4.000 ; + RECT 927.360 0.000 927.920 4.000 ; END END wb_dat_o[3] PIN wb_dat_o[4] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 1938.720 2174.000 1939.280 ; + LAYER Metal2 ; + RECT 991.200 0.000 991.760 4.000 ; END END wb_dat_o[4] PIN wb_dat_o[5] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 2214.240 2174.000 2214.800 ; + LAYER Metal2 ; + RECT 1055.040 0.000 1055.600 4.000 ; END END wb_dat_o[5] PIN wb_dat_o[6] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 1370.880 4.000 1371.440 ; + LAYER Metal2 ; + RECT 1118.880 0.000 1119.440 4.000 ; END END wb_dat_o[6] PIN wb_dat_o[7] @@ -1096,7 +1092,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 940.800 2346.000 941.360 2349.000 ; + RECT 1182.720 0.000 1183.280 4.000 ; END END wb_dat_o[7] PIN wb_rst_i @@ -1104,460 +1100,390 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 1370.880 1.000 1371.440 4.000 ; + RECT 2140.320 0.000 2140.880 4.000 ; END END wb_rst_i PIN wb_sel_i DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 1095.360 4.000 1095.920 ; + LAYER Metal2 ; + RECT 1948.800 0.000 1949.360 4.000 ; END END wb_sel_i PIN wb_stb_i DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 1.000 2194.080 4.000 2194.640 ; + LAYER Metal2 ; + RECT 1821.120 0.000 1821.680 4.000 ; END END wb_stb_i PIN wb_we_i DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER Metal3 ; - RECT 2171.000 1115.520 2174.000 1116.080 ; + LAYER Metal2 ; + RECT 1757.280 0.000 1757.840 4.000 ; END END wb_we_i OBS LAYER Metal1 ; - RECT 6.720 15.380 2167.760 2332.700 ; + RECT 6.720 15.380 2167.760 2352.300 ; LAYER Metal2 ; - RECT 8.540 2345.700 117.300 2346.000 ; - RECT 118.460 2345.700 389.460 2346.000 ; - RECT 390.620 2345.700 664.980 2346.000 ; - RECT 666.140 2345.700 940.500 2346.000 ; - RECT 941.660 2345.700 1216.020 2346.000 ; - RECT 1217.180 2345.700 1488.180 2346.000 ; - RECT 1489.340 2345.700 1763.700 2346.000 ; - RECT 1764.860 2345.700 2039.220 2346.000 ; - RECT 2040.380 2345.700 2165.380 2346.000 ; - RECT 8.540 4.300 2165.380 2345.700 ; - RECT 8.540 1.770 271.860 4.300 ; - RECT 273.020 1.770 547.380 4.300 ; - RECT 548.540 1.770 822.900 4.300 ; - RECT 824.060 1.770 1095.060 4.300 ; - RECT 1096.220 1.770 1370.580 4.300 ; - RECT 1371.740 1.770 1646.100 4.300 ; - RECT 1647.260 1.770 1918.260 4.300 ; - RECT 1919.420 1.770 2165.380 4.300 ; + RECT 24.780 4.300 2154.140 2352.190 ; + RECT 24.780 3.500 33.300 4.300 ; + RECT 34.460 3.500 97.140 4.300 ; + RECT 98.300 3.500 160.980 4.300 ; + RECT 162.140 3.500 224.820 4.300 ; + RECT 225.980 3.500 288.660 4.300 ; + RECT 289.820 3.500 352.500 4.300 ; + RECT 353.660 3.500 416.340 4.300 ; + RECT 417.500 3.500 480.180 4.300 ; + RECT 481.340 3.500 544.020 4.300 ; + RECT 545.180 3.500 607.860 4.300 ; + RECT 609.020 3.500 671.700 4.300 ; + RECT 672.860 3.500 735.540 4.300 ; + RECT 736.700 3.500 799.380 4.300 ; + RECT 800.540 3.500 863.220 4.300 ; + RECT 864.380 3.500 927.060 4.300 ; + RECT 928.220 3.500 990.900 4.300 ; + RECT 992.060 3.500 1054.740 4.300 ; + RECT 1055.900 3.500 1118.580 4.300 ; + RECT 1119.740 3.500 1182.420 4.300 ; + RECT 1183.580 3.500 1246.260 4.300 ; + RECT 1247.420 3.500 1310.100 4.300 ; + RECT 1311.260 3.500 1373.940 4.300 ; + RECT 1375.100 3.500 1437.780 4.300 ; + RECT 1438.940 3.500 1501.620 4.300 ; + RECT 1502.780 3.500 1565.460 4.300 ; + RECT 1566.620 3.500 1629.300 4.300 ; + RECT 1630.460 3.500 1693.140 4.300 ; + RECT 1694.300 3.500 1756.980 4.300 ; + RECT 1758.140 3.500 1820.820 4.300 ; + RECT 1821.980 3.500 1884.660 4.300 ; + RECT 1885.820 3.500 1948.500 4.300 ; + RECT 1949.660 3.500 2012.340 4.300 ; + RECT 2013.500 3.500 2076.180 4.300 ; + RECT 2077.340 3.500 2140.020 4.300 ; + RECT 2141.180 3.500 2154.140 4.300 ; LAYER Metal3 ; - RECT 4.000 2215.100 2171.000 2332.540 ; - RECT 4.000 2213.940 2170.700 2215.100 ; - RECT 4.000 2194.940 2171.000 2213.940 ; - RECT 4.300 2193.780 2171.000 2194.940 ; - RECT 4.000 1939.580 2171.000 2193.780 ; - RECT 4.000 1938.420 2170.700 1939.580 ; - RECT 4.000 1919.420 2171.000 1938.420 ; - RECT 4.300 1918.260 2171.000 1919.420 ; - RECT 4.000 1664.060 2171.000 1918.260 ; - RECT 4.000 1662.900 2170.700 1664.060 ; - RECT 4.000 1647.260 2171.000 1662.900 ; - RECT 4.300 1646.100 2171.000 1647.260 ; - RECT 4.000 1391.900 2171.000 1646.100 ; - RECT 4.000 1390.740 2170.700 1391.900 ; - RECT 4.000 1371.740 2171.000 1390.740 ; - RECT 4.300 1370.580 2171.000 1371.740 ; - RECT 4.000 1116.380 2171.000 1370.580 ; - RECT 4.000 1115.220 2170.700 1116.380 ; - RECT 4.000 1096.220 2171.000 1115.220 ; - RECT 4.300 1095.060 2171.000 1096.220 ; - RECT 4.000 840.860 2171.000 1095.060 ; - RECT 4.000 839.700 2170.700 840.860 ; - RECT 4.000 824.060 2171.000 839.700 ; - RECT 4.300 822.900 2171.000 824.060 ; - RECT 4.000 565.340 2171.000 822.900 ; - RECT 4.000 564.180 2170.700 565.340 ; - RECT 4.000 548.540 2171.000 564.180 ; - RECT 4.300 547.380 2171.000 548.540 ; - RECT 4.000 293.180 2171.000 547.380 ; - RECT 4.000 292.020 2170.700 293.180 ; - RECT 4.000 273.020 2171.000 292.020 ; - RECT 4.300 271.860 2171.000 273.020 ; - RECT 4.000 17.660 2171.000 271.860 ; - RECT 4.000 16.500 2170.700 17.660 ; - RECT 4.000 1.260 2171.000 16.500 ; + RECT 24.170 15.540 2154.190 2352.140 ; LAYER Metal4 ; - RECT 16.940 15.080 25.620 2330.070 ; - RECT 27.820 15.080 35.220 2330.070 ; - RECT 37.420 2293.800 215.620 2330.070 ; - RECT 37.420 1543.880 110.060 2293.800 ; - RECT 112.260 1543.880 120.140 2293.800 ; - RECT 122.340 1543.880 197.980 2293.800 ; - RECT 200.180 1543.880 208.060 2293.800 ; - RECT 210.260 2287.815 215.620 2293.800 ; - RECT 217.820 2287.815 225.220 2330.070 ; - RECT 210.260 2287.230 225.220 2287.815 ; - RECT 227.420 2293.800 405.620 2330.070 ; - RECT 227.420 2287.230 285.900 2293.800 ; - RECT 210.260 1550.020 285.900 2287.230 ; - RECT 210.260 1543.880 215.620 1550.020 ; - RECT 37.420 1533.320 215.620 1543.880 ; - RECT 37.420 783.400 110.060 1533.320 ; - RECT 112.260 783.400 120.140 1533.320 ; - RECT 122.340 783.400 197.980 1533.320 ; - RECT 200.180 783.400 208.060 1533.320 ; - RECT 210.260 1527.815 215.620 1533.320 ; - RECT 217.820 1527.815 225.220 1550.020 ; - RECT 210.260 1527.230 225.220 1527.815 ; - RECT 227.420 1543.880 285.900 1550.020 ; - RECT 288.100 1543.880 295.980 2293.800 ; - RECT 298.180 1543.880 373.820 2293.800 ; - RECT 376.020 1543.880 383.900 2293.800 ; - RECT 386.100 2287.205 405.620 2293.800 ; - RECT 407.820 2287.205 415.220 2330.070 ; - RECT 417.420 2293.800 595.620 2330.070 ; - RECT 417.420 2287.205 461.740 2293.800 ; - RECT 386.100 1552.570 461.740 2287.205 ; - RECT 386.100 1552.545 415.220 1552.570 ; - RECT 386.100 1543.880 405.620 1552.545 ; - RECT 227.420 1533.320 405.620 1543.880 ; - RECT 227.420 1527.230 285.900 1533.320 ; - RECT 210.260 790.020 285.900 1527.230 ; - RECT 210.260 783.400 215.620 790.020 ; - RECT 37.420 772.840 215.620 783.400 ; - RECT 37.420 22.920 110.060 772.840 ; - RECT 112.260 22.920 120.140 772.840 ; - RECT 122.340 22.920 197.980 772.840 ; - RECT 200.180 22.920 208.060 772.840 ; - RECT 210.260 767.815 215.620 772.840 ; - RECT 217.820 767.815 225.220 790.020 ; - RECT 210.260 767.230 225.220 767.815 ; - RECT 227.420 783.400 285.900 790.020 ; - RECT 288.100 783.400 295.980 1533.320 ; - RECT 298.180 783.400 373.820 1533.320 ; - RECT 376.020 783.400 383.900 1533.320 ; - RECT 386.100 1527.205 405.620 1533.320 ; - RECT 407.820 1527.205 415.220 1552.545 ; - RECT 417.420 1543.880 461.740 1552.570 ; - RECT 463.940 1543.880 471.820 2293.800 ; - RECT 474.020 1543.880 549.660 2293.800 ; - RECT 551.860 1543.880 559.740 2293.800 ; - RECT 561.940 2287.205 595.620 2293.800 ; - RECT 597.820 2287.205 605.220 2330.070 ; - RECT 607.420 2293.800 785.620 2330.070 ; - RECT 607.420 2287.205 638.140 2293.800 ; - RECT 561.940 1552.570 638.140 2287.205 ; - RECT 561.940 1543.880 595.620 1552.570 ; - RECT 417.420 1533.320 595.620 1543.880 ; - RECT 417.420 1527.205 461.740 1533.320 ; - RECT 386.100 792.570 461.740 1527.205 ; - RECT 386.100 792.545 415.220 792.570 ; - RECT 386.100 783.400 405.620 792.545 ; - RECT 227.420 772.840 405.620 783.400 ; - RECT 227.420 767.230 285.900 772.840 ; - RECT 210.260 30.020 285.900 767.230 ; - RECT 210.260 22.920 215.620 30.020 ; - RECT 37.420 15.080 215.620 22.920 ; - RECT 217.820 15.080 225.220 30.020 ; - RECT 227.420 22.920 285.900 30.020 ; - RECT 288.100 22.920 295.980 772.840 ; - RECT 298.180 22.920 373.820 772.840 ; - RECT 376.020 22.920 383.900 772.840 ; - RECT 386.100 767.205 405.620 772.840 ; - RECT 407.820 767.205 415.220 792.545 ; - RECT 417.420 783.400 461.740 792.570 ; - RECT 463.940 783.400 471.820 1533.320 ; - RECT 474.020 783.400 549.660 1533.320 ; - RECT 551.860 783.400 559.740 1533.320 ; - RECT 561.940 1527.205 595.620 1533.320 ; - RECT 597.820 1527.205 605.220 1552.570 ; - RECT 607.420 1543.880 638.140 1552.570 ; - RECT 640.340 1543.880 648.220 2293.800 ; - RECT 650.420 1543.880 726.060 2293.800 ; - RECT 728.260 1543.880 736.140 2293.800 ; - RECT 738.340 2287.230 785.620 2293.800 ; - RECT 787.820 2287.230 795.220 2330.070 ; - RECT 797.420 2293.800 975.620 2330.070 ; - RECT 797.420 2287.230 813.980 2293.800 ; - RECT 738.340 1552.570 813.980 2287.230 ; - RECT 738.340 1543.880 785.620 1552.570 ; - RECT 607.420 1533.320 785.620 1543.880 ; - RECT 607.420 1527.205 638.140 1533.320 ; - RECT 561.940 792.570 638.140 1527.205 ; - RECT 561.940 783.400 595.620 792.570 ; - RECT 417.420 772.840 595.620 783.400 ; - RECT 417.420 767.205 461.740 772.840 ; - RECT 386.100 32.570 461.740 767.205 ; - RECT 386.100 32.545 415.220 32.570 ; - RECT 386.100 22.920 405.620 32.545 ; - RECT 227.420 15.080 405.620 22.920 ; - RECT 407.820 15.080 415.220 32.545 ; - RECT 417.420 22.920 461.740 32.570 ; - RECT 463.940 22.920 471.820 772.840 ; - RECT 474.020 22.920 549.660 772.840 ; - RECT 551.860 22.920 559.740 772.840 ; - RECT 561.940 767.205 595.620 772.840 ; - RECT 597.820 767.205 605.220 792.570 ; - RECT 607.420 783.400 638.140 792.570 ; - RECT 640.340 783.400 648.220 1533.320 ; - RECT 650.420 783.400 726.060 1533.320 ; - RECT 728.260 783.400 736.140 1533.320 ; - RECT 738.340 1527.230 785.620 1533.320 ; - RECT 787.820 1527.230 795.220 1552.570 ; - RECT 797.420 1543.880 813.980 1552.570 ; - RECT 816.180 1543.880 824.060 2293.800 ; - RECT 826.260 1543.880 901.900 2293.800 ; - RECT 904.100 1543.880 911.980 2293.800 ; - RECT 914.180 2287.205 975.620 2293.800 ; - RECT 977.820 2287.205 985.220 2330.070 ; - RECT 914.180 1552.545 985.220 2287.205 ; - RECT 914.180 1543.880 975.620 1552.545 ; - RECT 797.420 1533.320 975.620 1543.880 ; - RECT 797.420 1527.230 813.980 1533.320 ; - RECT 738.340 792.570 813.980 1527.230 ; - RECT 738.340 783.400 785.620 792.570 ; - RECT 607.420 772.840 785.620 783.400 ; - RECT 607.420 767.205 638.140 772.840 ; - RECT 561.940 32.570 638.140 767.205 ; - RECT 561.940 22.920 595.620 32.570 ; - RECT 417.420 15.080 595.620 22.920 ; - RECT 597.820 15.080 605.220 32.570 ; - RECT 607.420 22.920 638.140 32.570 ; - RECT 640.340 22.920 648.220 772.840 ; - RECT 650.420 22.920 726.060 772.840 ; - RECT 728.260 22.920 736.140 772.840 ; - RECT 738.340 767.230 785.620 772.840 ; - RECT 787.820 767.230 795.220 792.570 ; - RECT 797.420 783.400 813.980 792.570 ; - RECT 816.180 783.400 824.060 1533.320 ; - RECT 826.260 783.400 901.900 1533.320 ; - RECT 904.100 783.400 911.980 1533.320 ; - RECT 914.180 1527.205 975.620 1533.320 ; - RECT 977.820 1527.205 985.220 1552.545 ; - RECT 914.180 792.545 985.220 1527.205 ; - RECT 914.180 783.400 975.620 792.545 ; - RECT 797.420 772.840 975.620 783.400 ; - RECT 797.420 767.230 813.980 772.840 ; - RECT 738.340 32.570 813.980 767.230 ; - RECT 738.340 22.920 785.620 32.570 ; - RECT 607.420 15.080 785.620 22.920 ; - RECT 787.820 15.080 795.220 32.570 ; - RECT 797.420 22.920 813.980 32.570 ; - RECT 816.180 22.920 824.060 772.840 ; - RECT 826.260 22.920 901.900 772.840 ; - RECT 904.100 22.920 911.980 772.840 ; - RECT 914.180 767.205 975.620 772.840 ; - RECT 977.820 767.205 985.220 792.545 ; - RECT 914.180 32.545 985.220 767.205 ; - RECT 914.180 22.920 975.620 32.545 ; - RECT 797.420 15.080 975.620 22.920 ; - RECT 977.820 15.080 985.220 32.545 ; - RECT 987.420 2293.800 1165.620 2330.070 ; - RECT 987.420 1543.880 989.820 2293.800 ; - RECT 992.020 1543.880 999.900 2293.800 ; - RECT 1002.100 1543.880 1077.740 2293.800 ; - RECT 1079.940 1543.880 1087.820 2293.800 ; - RECT 1090.020 1543.880 1165.620 2293.800 ; - RECT 987.420 1533.320 1165.620 1543.880 ; - RECT 987.420 783.400 989.820 1533.320 ; - RECT 992.020 783.400 999.900 1533.320 ; - RECT 1002.100 783.400 1077.740 1533.320 ; - RECT 1079.940 783.400 1087.820 1533.320 ; - RECT 1090.020 783.400 1165.620 1533.320 ; - RECT 987.420 772.840 1165.620 783.400 ; - RECT 987.420 22.920 989.820 772.840 ; - RECT 992.020 22.920 999.900 772.840 ; - RECT 1002.100 22.920 1077.740 772.840 ; - RECT 1079.940 22.920 1087.820 772.840 ; - RECT 1090.020 22.920 1165.620 772.840 ; - RECT 987.420 15.080 1165.620 22.920 ; - RECT 1167.820 15.080 1175.220 2330.070 ; - RECT 1177.420 2293.800 1355.620 2330.070 ; - RECT 1177.420 1543.880 1254.140 2293.800 ; - RECT 1256.340 1543.880 1264.220 2293.800 ; - RECT 1266.420 2289.880 1355.620 2293.800 ; - RECT 1266.420 1543.880 1347.100 2289.880 ; - RECT 1349.300 1543.880 1355.620 2289.880 ; - RECT 1177.420 1533.320 1355.620 1543.880 ; - RECT 1177.420 783.400 1254.140 1533.320 ; - RECT 1256.340 783.400 1264.220 1533.320 ; - RECT 1266.420 1529.400 1355.620 1533.320 ; - RECT 1266.420 783.400 1347.100 1529.400 ; - RECT 1349.300 783.400 1355.620 1529.400 ; - RECT 1177.420 772.840 1355.620 783.400 ; - RECT 1177.420 22.920 1254.140 772.840 ; - RECT 1256.340 22.920 1264.220 772.840 ; - RECT 1266.420 768.920 1355.620 772.840 ; - RECT 1266.420 22.920 1347.100 768.920 ; - RECT 1349.300 22.920 1355.620 768.920 ; - RECT 1177.420 15.080 1355.620 22.920 ; - RECT 1357.820 2287.230 1365.220 2330.070 ; - RECT 1367.420 2293.800 1545.620 2330.070 ; - RECT 1367.420 2287.230 1429.980 2293.800 ; - RECT 1357.820 1550.020 1429.980 2287.230 ; - RECT 1357.820 1527.230 1365.220 1550.020 ; - RECT 1367.420 1543.880 1429.980 1550.020 ; - RECT 1432.180 1543.880 1440.060 2293.800 ; - RECT 1442.260 1543.880 1517.900 2293.800 ; - RECT 1520.100 1543.880 1527.980 2293.800 ; - RECT 1530.180 2287.230 1545.620 2293.800 ; - RECT 1547.820 2287.230 1555.220 2330.070 ; - RECT 1530.180 2287.205 1555.220 2287.230 ; - RECT 1557.420 2293.800 1735.620 2330.070 ; - RECT 1557.420 2287.205 1605.820 2293.800 ; - RECT 1530.180 1552.570 1605.820 2287.205 ; - RECT 1530.180 1550.020 1555.220 1552.570 ; - RECT 1530.180 1543.880 1545.620 1550.020 ; - RECT 1367.420 1533.320 1545.620 1543.880 ; - RECT 1367.420 1527.230 1429.980 1533.320 ; - RECT 1357.820 790.020 1429.980 1527.230 ; - RECT 1357.820 767.230 1365.220 790.020 ; - RECT 1367.420 783.400 1429.980 790.020 ; - RECT 1432.180 783.400 1440.060 1533.320 ; - RECT 1442.260 783.400 1517.900 1533.320 ; - RECT 1520.100 783.400 1527.980 1533.320 ; - RECT 1530.180 1527.230 1545.620 1533.320 ; - RECT 1547.820 1527.230 1555.220 1550.020 ; - RECT 1530.180 1527.205 1555.220 1527.230 ; - RECT 1557.420 1543.880 1605.820 1552.570 ; - RECT 1608.020 1543.880 1615.900 2293.800 ; - RECT 1618.100 1543.880 1693.740 2293.800 ; - RECT 1695.940 1543.880 1703.820 2293.800 ; - RECT 1706.020 2287.205 1735.620 2293.800 ; - RECT 1737.820 2287.205 1745.220 2330.070 ; - RECT 1747.420 2293.800 1925.620 2330.070 ; - RECT 1747.420 2287.205 1781.660 2293.800 ; - RECT 1706.020 1552.570 1781.660 2287.205 ; - RECT 1706.020 1543.880 1735.620 1552.570 ; - RECT 1557.420 1533.320 1735.620 1543.880 ; - RECT 1557.420 1527.205 1605.820 1533.320 ; - RECT 1530.180 792.570 1605.820 1527.205 ; - RECT 1530.180 790.020 1555.220 792.570 ; - RECT 1530.180 783.400 1545.620 790.020 ; - RECT 1367.420 772.840 1545.620 783.400 ; - RECT 1367.420 767.230 1429.980 772.840 ; - RECT 1357.820 30.020 1429.980 767.230 ; - RECT 1357.820 15.080 1365.220 30.020 ; - RECT 1367.420 22.920 1429.980 30.020 ; - RECT 1432.180 22.920 1440.060 772.840 ; - RECT 1442.260 22.920 1517.900 772.840 ; - RECT 1520.100 22.920 1527.980 772.840 ; - RECT 1530.180 767.230 1545.620 772.840 ; - RECT 1547.820 767.230 1555.220 790.020 ; - RECT 1530.180 767.205 1555.220 767.230 ; - RECT 1557.420 783.400 1605.820 792.570 ; - RECT 1608.020 783.400 1615.900 1533.320 ; - RECT 1618.100 783.400 1693.740 1533.320 ; - RECT 1695.940 783.400 1703.820 1533.320 ; - RECT 1706.020 1527.205 1735.620 1533.320 ; - RECT 1737.820 1527.205 1745.220 1552.570 ; - RECT 1747.420 1543.880 1781.660 1552.570 ; - RECT 1783.860 1543.880 1791.740 2293.800 ; - RECT 1793.940 1543.880 1870.140 2293.800 ; - RECT 1872.340 1543.880 1880.220 2293.800 ; - RECT 1882.420 2287.205 1925.620 2293.800 ; - RECT 1927.820 2287.230 1935.220 2330.070 ; - RECT 1937.420 2293.800 2115.620 2330.070 ; - RECT 1937.420 2287.230 1958.060 2293.800 ; - RECT 1927.820 2287.205 1958.060 2287.230 ; - RECT 1882.420 1552.570 1958.060 2287.205 ; - RECT 1882.420 1543.880 1925.620 1552.570 ; - RECT 1747.420 1533.320 1925.620 1543.880 ; - RECT 1747.420 1527.205 1781.660 1533.320 ; - RECT 1706.020 792.570 1781.660 1527.205 ; - RECT 1706.020 783.400 1735.620 792.570 ; - RECT 1557.420 772.840 1735.620 783.400 ; - RECT 1557.420 767.205 1605.820 772.840 ; - RECT 1530.180 32.570 1605.820 767.205 ; - RECT 1530.180 30.020 1555.220 32.570 ; - RECT 1530.180 22.920 1545.620 30.020 ; - RECT 1367.420 15.080 1545.620 22.920 ; - RECT 1547.820 15.080 1555.220 30.020 ; - RECT 1557.420 22.920 1605.820 32.570 ; - RECT 1608.020 22.920 1615.900 772.840 ; - RECT 1618.100 22.920 1693.740 772.840 ; - RECT 1695.940 22.920 1703.820 772.840 ; - RECT 1706.020 767.205 1735.620 772.840 ; - RECT 1737.820 767.205 1745.220 792.570 ; - RECT 1747.420 783.400 1781.660 792.570 ; - RECT 1783.860 783.400 1791.740 1533.320 ; - RECT 1793.940 783.400 1870.140 1533.320 ; - RECT 1872.340 783.400 1880.220 1533.320 ; - RECT 1882.420 1527.205 1925.620 1533.320 ; - RECT 1927.820 1527.230 1935.220 1552.570 ; - RECT 1937.420 1543.880 1958.060 1552.570 ; - RECT 1960.260 1543.880 1968.140 2293.800 ; - RECT 1970.340 1543.880 2045.980 2293.800 ; - RECT 2048.180 1543.880 2056.060 2293.800 ; - RECT 2058.260 2287.230 2115.620 2293.800 ; - RECT 2117.820 2287.815 2125.220 2330.070 ; - RECT 2127.420 2293.800 2147.460 2330.070 ; - RECT 2127.420 2287.815 2143.420 2293.800 ; - RECT 2117.820 2287.230 2143.420 2287.815 ; - RECT 2058.260 1552.545 2143.420 2287.230 ; - RECT 2058.260 1543.880 2115.620 1552.545 ; - RECT 1937.420 1533.320 2115.620 1543.880 ; - RECT 1937.420 1527.230 1958.060 1533.320 ; - RECT 1927.820 1527.205 1958.060 1527.230 ; - RECT 1882.420 792.570 1958.060 1527.205 ; - RECT 1882.420 783.400 1925.620 792.570 ; - RECT 1747.420 772.840 1925.620 783.400 ; - RECT 1747.420 767.205 1781.660 772.840 ; - RECT 1706.020 32.570 1781.660 767.205 ; - RECT 1706.020 22.920 1735.620 32.570 ; - RECT 1557.420 15.080 1735.620 22.920 ; - RECT 1737.820 15.080 1745.220 32.570 ; - RECT 1747.420 22.920 1781.660 32.570 ; - RECT 1783.860 22.920 1791.740 772.840 ; - RECT 1793.940 22.920 1870.140 772.840 ; - RECT 1872.340 22.920 1880.220 772.840 ; - RECT 1882.420 767.205 1925.620 772.840 ; - RECT 1927.820 767.230 1935.220 792.570 ; - RECT 1937.420 783.400 1958.060 792.570 ; - RECT 1960.260 783.400 1968.140 1533.320 ; - RECT 1970.340 783.400 2045.980 1533.320 ; - RECT 2048.180 783.400 2056.060 1533.320 ; - RECT 2058.260 1527.230 2115.620 1533.320 ; - RECT 2117.820 1550.810 2143.420 1552.545 ; - RECT 2117.820 1527.815 2125.220 1550.810 ; - RECT 2127.420 1543.880 2143.420 1550.810 ; - RECT 2145.620 1543.880 2147.460 2293.800 ; - RECT 2127.420 1533.320 2147.460 1543.880 ; - RECT 2127.420 1527.815 2143.420 1533.320 ; - RECT 2117.820 1527.230 2143.420 1527.815 ; - RECT 2058.260 792.545 2143.420 1527.230 ; - RECT 2058.260 783.400 2115.620 792.545 ; - RECT 1937.420 772.840 2115.620 783.400 ; - RECT 1937.420 767.230 1958.060 772.840 ; - RECT 1927.820 767.205 1958.060 767.230 ; - RECT 1882.420 32.570 1958.060 767.205 ; - RECT 1882.420 22.920 1925.620 32.570 ; - RECT 1747.420 15.080 1925.620 22.920 ; - RECT 1927.820 15.080 1935.220 32.570 ; - RECT 1937.420 22.920 1958.060 32.570 ; - RECT 1960.260 22.920 1968.140 772.840 ; - RECT 1970.340 22.920 2045.980 772.840 ; - RECT 2048.180 22.920 2056.060 772.840 ; - RECT 2058.260 767.230 2115.620 772.840 ; - RECT 2117.820 790.810 2143.420 792.545 ; - RECT 2117.820 767.815 2125.220 790.810 ; - RECT 2127.420 783.400 2143.420 790.810 ; - RECT 2145.620 783.400 2147.460 1533.320 ; - RECT 2127.420 772.840 2147.460 783.400 ; - RECT 2127.420 767.815 2143.420 772.840 ; - RECT 2117.820 767.230 2143.420 767.815 ; - RECT 2058.260 32.545 2143.420 767.230 ; - RECT 2058.260 22.920 2115.620 32.545 ; - RECT 1937.420 15.080 2115.620 22.920 ; - RECT 2117.820 30.810 2143.420 32.545 ; - RECT 2117.820 15.080 2125.220 30.810 ; - RECT 2127.420 22.920 2143.420 30.810 ; - RECT 2145.620 22.920 2147.460 772.840 ; - RECT 2127.420 15.080 2147.460 22.920 ; - RECT 16.940 1.210 2147.460 15.080 ; + RECT 24.220 18.010 25.620 2297.835 ; + RECT 27.820 18.010 35.220 2297.835 ; + RECT 37.420 1563.480 110.060 2297.835 ; + RECT 112.260 1563.480 120.140 2297.835 ; + RECT 122.340 1563.480 197.980 2297.835 ; + RECT 200.180 1563.480 208.060 2297.835 ; + RECT 210.260 1570.020 285.900 2297.835 ; + RECT 210.260 1563.480 215.620 1570.020 ; + RECT 37.420 1552.920 215.620 1563.480 ; + RECT 37.420 803.000 110.060 1552.920 ; + RECT 112.260 803.000 120.140 1552.920 ; + RECT 122.340 803.000 197.980 1552.920 ; + RECT 200.180 803.000 208.060 1552.920 ; + RECT 210.260 1547.815 215.620 1552.920 ; + RECT 217.820 1547.815 225.220 1570.020 ; + RECT 210.260 1547.230 225.220 1547.815 ; + RECT 227.420 1563.480 285.900 1570.020 ; + RECT 288.100 1563.480 295.980 2297.835 ; + RECT 298.180 1563.480 373.820 2297.835 ; + RECT 376.020 1563.480 383.900 2297.835 ; + RECT 386.100 1572.570 462.300 2297.835 ; + RECT 386.100 1572.545 415.220 1572.570 ; + RECT 386.100 1563.480 405.620 1572.545 ; + RECT 227.420 1552.920 405.620 1563.480 ; + RECT 227.420 1547.230 285.900 1552.920 ; + RECT 210.260 810.020 285.900 1547.230 ; + RECT 210.260 803.000 215.620 810.020 ; + RECT 37.420 792.440 215.620 803.000 ; + RECT 37.420 42.520 110.060 792.440 ; + RECT 112.260 42.520 120.140 792.440 ; + RECT 122.340 42.520 197.980 792.440 ; + RECT 200.180 42.520 208.060 792.440 ; + RECT 210.260 787.815 215.620 792.440 ; + RECT 217.820 787.815 225.220 810.020 ; + RECT 210.260 787.230 225.220 787.815 ; + RECT 227.420 803.000 285.900 810.020 ; + RECT 288.100 803.000 295.980 1552.920 ; + RECT 298.180 803.000 373.820 1552.920 ; + RECT 376.020 803.000 383.900 1552.920 ; + RECT 386.100 1547.205 405.620 1552.920 ; + RECT 407.820 1547.205 415.220 1572.545 ; + RECT 417.420 1563.480 462.300 1572.570 ; + RECT 464.500 1563.480 472.380 2297.835 ; + RECT 474.580 1563.480 550.220 2297.835 ; + RECT 552.420 1563.480 560.300 2297.835 ; + RECT 562.500 1572.570 638.140 2297.835 ; + RECT 562.500 1563.480 595.620 1572.570 ; + RECT 417.420 1552.920 595.620 1563.480 ; + RECT 417.420 1547.205 462.300 1552.920 ; + RECT 386.100 812.570 462.300 1547.205 ; + RECT 386.100 812.545 415.220 812.570 ; + RECT 386.100 803.000 405.620 812.545 ; + RECT 227.420 792.440 405.620 803.000 ; + RECT 227.420 787.230 285.900 792.440 ; + RECT 210.260 50.020 285.900 787.230 ; + RECT 210.260 42.520 215.620 50.020 ; + RECT 37.420 18.010 215.620 42.520 ; + RECT 217.820 18.010 225.220 50.020 ; + RECT 227.420 42.520 285.900 50.020 ; + RECT 288.100 42.520 295.980 792.440 ; + RECT 298.180 42.520 373.820 792.440 ; + RECT 376.020 42.520 383.900 792.440 ; + RECT 386.100 787.205 405.620 792.440 ; + RECT 407.820 787.205 415.220 812.545 ; + RECT 417.420 803.000 462.300 812.570 ; + RECT 464.500 803.000 472.380 1552.920 ; + RECT 474.580 803.000 550.220 1552.920 ; + RECT 552.420 803.000 560.300 1552.920 ; + RECT 562.500 1547.205 595.620 1552.920 ; + RECT 597.820 1547.205 605.220 1572.570 ; + RECT 607.420 1563.480 638.140 1572.570 ; + RECT 640.340 1563.480 648.220 2297.835 ; + RECT 650.420 1563.480 726.060 2297.835 ; + RECT 728.260 1563.480 736.140 2297.835 ; + RECT 738.340 1572.570 813.980 2297.835 ; + RECT 738.340 1563.480 785.620 1572.570 ; + RECT 607.420 1552.920 785.620 1563.480 ; + RECT 607.420 1547.205 638.140 1552.920 ; + RECT 562.500 812.570 638.140 1547.205 ; + RECT 562.500 803.000 595.620 812.570 ; + RECT 417.420 792.440 595.620 803.000 ; + RECT 417.420 787.205 462.300 792.440 ; + RECT 386.100 52.570 462.300 787.205 ; + RECT 386.100 52.545 415.220 52.570 ; + RECT 386.100 42.520 405.620 52.545 ; + RECT 227.420 18.010 405.620 42.520 ; + RECT 407.820 18.010 415.220 52.545 ; + RECT 417.420 42.520 462.300 52.570 ; + RECT 464.500 42.520 472.380 792.440 ; + RECT 474.580 42.520 550.220 792.440 ; + RECT 552.420 42.520 560.300 792.440 ; + RECT 562.500 787.205 595.620 792.440 ; + RECT 597.820 787.205 605.220 812.570 ; + RECT 607.420 803.000 638.140 812.570 ; + RECT 640.340 803.000 648.220 1552.920 ; + RECT 650.420 803.000 726.060 1552.920 ; + RECT 728.260 803.000 736.140 1552.920 ; + RECT 738.340 1547.230 785.620 1552.920 ; + RECT 787.820 1547.230 795.220 1572.570 ; + RECT 797.420 1563.480 813.980 1572.570 ; + RECT 816.180 1563.480 824.060 2297.835 ; + RECT 826.260 1563.480 901.900 2297.835 ; + RECT 904.100 1563.480 911.980 2297.835 ; + RECT 914.180 1572.545 985.220 2297.835 ; + RECT 914.180 1563.480 975.620 1572.545 ; + RECT 797.420 1552.920 975.620 1563.480 ; + RECT 797.420 1547.230 813.980 1552.920 ; + RECT 738.340 812.570 813.980 1547.230 ; + RECT 738.340 803.000 785.620 812.570 ; + RECT 607.420 792.440 785.620 803.000 ; + RECT 607.420 787.205 638.140 792.440 ; + RECT 562.500 52.570 638.140 787.205 ; + RECT 562.500 42.520 595.620 52.570 ; + RECT 417.420 18.010 595.620 42.520 ; + RECT 597.820 18.010 605.220 52.570 ; + RECT 607.420 42.520 638.140 52.570 ; + RECT 640.340 42.520 648.220 792.440 ; + RECT 650.420 42.520 726.060 792.440 ; + RECT 728.260 42.520 736.140 792.440 ; + RECT 738.340 787.230 785.620 792.440 ; + RECT 787.820 787.230 795.220 812.570 ; + RECT 797.420 803.000 813.980 812.570 ; + RECT 816.180 803.000 824.060 1552.920 ; + RECT 826.260 803.000 901.900 1552.920 ; + RECT 904.100 803.000 911.980 1552.920 ; + RECT 914.180 1547.205 975.620 1552.920 ; + RECT 977.820 1547.205 985.220 1572.545 ; + RECT 914.180 812.545 985.220 1547.205 ; + RECT 914.180 803.000 975.620 812.545 ; + RECT 797.420 792.440 975.620 803.000 ; + RECT 797.420 787.230 813.980 792.440 ; + RECT 738.340 52.570 813.980 787.230 ; + RECT 738.340 42.520 785.620 52.570 ; + RECT 607.420 18.010 785.620 42.520 ; + RECT 787.820 18.010 795.220 52.570 ; + RECT 797.420 42.520 813.980 52.570 ; + RECT 816.180 42.520 824.060 792.440 ; + RECT 826.260 42.520 901.900 792.440 ; + RECT 904.100 42.520 911.980 792.440 ; + RECT 914.180 787.205 975.620 792.440 ; + RECT 977.820 787.205 985.220 812.545 ; + RECT 914.180 52.545 985.220 787.205 ; + RECT 914.180 42.520 975.620 52.545 ; + RECT 797.420 18.010 975.620 42.520 ; + RECT 977.820 18.010 985.220 52.545 ; + RECT 987.420 1563.480 994.860 2297.835 ; + RECT 997.060 1563.480 1078.300 2297.835 ; + RECT 1080.500 1563.480 1088.380 2297.835 ; + RECT 1090.580 1563.480 1165.620 2297.835 ; + RECT 987.420 1552.920 1165.620 1563.480 ; + RECT 987.420 1549.000 1078.300 1552.920 ; + RECT 987.420 803.000 994.860 1549.000 ; + RECT 997.060 803.000 1078.300 1549.000 ; + RECT 1080.500 803.000 1088.380 1552.920 ; + RECT 1090.580 803.000 1165.620 1552.920 ; + RECT 987.420 792.440 1165.620 803.000 ; + RECT 987.420 788.520 1078.300 792.440 ; + RECT 987.420 42.520 994.860 788.520 ; + RECT 997.060 42.520 1078.300 788.520 ; + RECT 1080.500 42.520 1088.380 792.440 ; + RECT 1090.580 42.520 1165.620 792.440 ; + RECT 987.420 18.010 1165.620 42.520 ; + RECT 1167.820 18.010 1175.220 2297.835 ; + RECT 1177.420 1563.480 1254.140 2297.835 ; + RECT 1256.340 1563.480 1264.220 2297.835 ; + RECT 1266.420 1567.400 1346.540 2297.835 ; + RECT 1348.740 1567.400 1355.620 2297.835 ; + RECT 1266.420 1563.480 1355.620 1567.400 ; + RECT 1177.420 1552.920 1355.620 1563.480 ; + RECT 1177.420 803.000 1254.140 1552.920 ; + RECT 1256.340 803.000 1264.220 1552.920 ; + RECT 1266.420 806.920 1346.540 1552.920 ; + RECT 1348.740 806.920 1355.620 1552.920 ; + RECT 1266.420 803.000 1355.620 806.920 ; + RECT 1177.420 792.440 1355.620 803.000 ; + RECT 1177.420 42.520 1254.140 792.440 ; + RECT 1256.340 42.520 1264.220 792.440 ; + RECT 1266.420 46.440 1346.540 792.440 ; + RECT 1348.740 46.440 1355.620 792.440 ; + RECT 1266.420 42.520 1355.620 46.440 ; + RECT 1177.420 18.010 1355.620 42.520 ; + RECT 1357.820 1570.020 1429.980 2297.835 ; + RECT 1357.820 1547.230 1365.220 1570.020 ; + RECT 1367.420 1563.480 1429.980 1570.020 ; + RECT 1432.180 1563.480 1440.060 2297.835 ; + RECT 1442.260 1563.480 1517.900 2297.835 ; + RECT 1520.100 1563.480 1527.980 2297.835 ; + RECT 1530.180 1572.570 1605.820 2297.835 ; + RECT 1530.180 1570.020 1555.220 1572.570 ; + RECT 1530.180 1563.480 1545.620 1570.020 ; + RECT 1367.420 1552.920 1545.620 1563.480 ; + RECT 1367.420 1547.230 1429.980 1552.920 ; + RECT 1357.820 810.020 1429.980 1547.230 ; + RECT 1357.820 787.230 1365.220 810.020 ; + RECT 1367.420 803.000 1429.980 810.020 ; + RECT 1432.180 803.000 1440.060 1552.920 ; + RECT 1442.260 803.000 1517.900 1552.920 ; + RECT 1520.100 803.000 1527.980 1552.920 ; + RECT 1530.180 1547.230 1545.620 1552.920 ; + RECT 1547.820 1547.230 1555.220 1570.020 ; + RECT 1530.180 1547.205 1555.220 1547.230 ; + RECT 1557.420 1563.480 1605.820 1572.570 ; + RECT 1608.020 1563.480 1615.900 2297.835 ; + RECT 1618.100 1563.480 1694.300 2297.835 ; + RECT 1696.500 1563.480 1704.380 2297.835 ; + RECT 1706.580 1572.570 1782.220 2297.835 ; + RECT 1706.580 1563.480 1735.620 1572.570 ; + RECT 1557.420 1552.920 1735.620 1563.480 ; + RECT 1557.420 1547.205 1605.820 1552.920 ; + RECT 1530.180 812.570 1605.820 1547.205 ; + RECT 1530.180 810.020 1555.220 812.570 ; + RECT 1530.180 803.000 1545.620 810.020 ; + RECT 1367.420 792.440 1545.620 803.000 ; + RECT 1367.420 787.230 1429.980 792.440 ; + RECT 1357.820 50.020 1429.980 787.230 ; + RECT 1357.820 18.010 1365.220 50.020 ; + RECT 1367.420 42.520 1429.980 50.020 ; + RECT 1432.180 42.520 1440.060 792.440 ; + RECT 1442.260 42.520 1517.900 792.440 ; + RECT 1520.100 42.520 1527.980 792.440 ; + RECT 1530.180 787.230 1545.620 792.440 ; + RECT 1547.820 787.230 1555.220 810.020 ; + RECT 1530.180 787.205 1555.220 787.230 ; + RECT 1557.420 803.000 1605.820 812.570 ; + RECT 1608.020 803.000 1615.900 1552.920 ; + RECT 1618.100 803.000 1694.300 1552.920 ; + RECT 1696.500 803.000 1704.380 1552.920 ; + RECT 1706.580 1547.205 1735.620 1552.920 ; + RECT 1737.820 1547.205 1745.220 1572.570 ; + RECT 1747.420 1563.480 1782.220 1572.570 ; + RECT 1784.420 1563.480 1792.300 2297.835 ; + RECT 1794.500 1563.480 1870.140 2297.835 ; + RECT 1872.340 1563.480 1880.220 2297.835 ; + RECT 1882.420 1572.570 1958.060 2297.835 ; + RECT 1882.420 1563.480 1925.620 1572.570 ; + RECT 1747.420 1552.920 1925.620 1563.480 ; + RECT 1747.420 1547.205 1782.220 1552.920 ; + RECT 1706.580 812.570 1782.220 1547.205 ; + RECT 1706.580 803.000 1735.620 812.570 ; + RECT 1557.420 792.440 1735.620 803.000 ; + RECT 1557.420 787.205 1605.820 792.440 ; + RECT 1530.180 52.570 1605.820 787.205 ; + RECT 1530.180 50.020 1555.220 52.570 ; + RECT 1530.180 42.520 1545.620 50.020 ; + RECT 1367.420 18.010 1545.620 42.520 ; + RECT 1547.820 18.010 1555.220 50.020 ; + RECT 1557.420 42.520 1605.820 52.570 ; + RECT 1608.020 42.520 1615.900 792.440 ; + RECT 1618.100 42.520 1694.300 792.440 ; + RECT 1696.500 42.520 1704.380 792.440 ; + RECT 1706.580 787.205 1735.620 792.440 ; + RECT 1737.820 787.205 1745.220 812.570 ; + RECT 1747.420 803.000 1782.220 812.570 ; + RECT 1784.420 803.000 1792.300 1552.920 ; + RECT 1794.500 803.000 1870.140 1552.920 ; + RECT 1872.340 803.000 1880.220 1552.920 ; + RECT 1882.420 1547.205 1925.620 1552.920 ; + RECT 1927.820 1547.230 1935.220 1572.570 ; + RECT 1937.420 1563.480 1958.060 1572.570 ; + RECT 1960.260 1563.480 1968.140 2297.835 ; + RECT 1970.340 1563.480 2045.980 2297.835 ; + RECT 2048.180 1563.480 2056.060 2297.835 ; + RECT 2058.260 1572.570 2134.020 2297.835 ; + RECT 2058.260 1563.480 2115.620 1572.570 ; + RECT 1937.420 1552.920 2115.620 1563.480 ; + RECT 1937.420 1547.230 1958.060 1552.920 ; + RECT 1927.820 1547.205 1958.060 1547.230 ; + RECT 1882.420 812.570 1958.060 1547.205 ; + RECT 1882.420 803.000 1925.620 812.570 ; + RECT 1747.420 792.440 1925.620 803.000 ; + RECT 1747.420 787.205 1782.220 792.440 ; + RECT 1706.580 52.570 1782.220 787.205 ; + RECT 1706.580 42.520 1735.620 52.570 ; + RECT 1557.420 18.010 1735.620 42.520 ; + RECT 1737.820 18.010 1745.220 52.570 ; + RECT 1747.420 42.520 1782.220 52.570 ; + RECT 1784.420 42.520 1792.300 792.440 ; + RECT 1794.500 42.520 1870.140 792.440 ; + RECT 1872.340 42.520 1880.220 792.440 ; + RECT 1882.420 787.205 1925.620 792.440 ; + RECT 1927.820 787.230 1935.220 812.570 ; + RECT 1937.420 803.000 1958.060 812.570 ; + RECT 1960.260 803.000 1968.140 1552.920 ; + RECT 1970.340 803.000 2045.980 1552.920 ; + RECT 2048.180 803.000 2056.060 1552.920 ; + RECT 2058.260 1547.230 2115.620 1552.920 ; + RECT 2117.820 1570.810 2134.020 1572.570 ; + RECT 2117.820 1547.815 2125.220 1570.810 ; + RECT 2127.420 1547.815 2134.020 1570.810 ; + RECT 2117.820 1547.230 2134.020 1547.815 ; + RECT 2058.260 812.570 2134.020 1547.230 ; + RECT 2058.260 803.000 2115.620 812.570 ; + RECT 1937.420 792.440 2115.620 803.000 ; + RECT 1937.420 787.230 1958.060 792.440 ; + RECT 1927.820 787.205 1958.060 787.230 ; + RECT 1882.420 52.570 1958.060 787.205 ; + RECT 1882.420 42.520 1925.620 52.570 ; + RECT 1747.420 18.010 1925.620 42.520 ; + RECT 1927.820 18.010 1935.220 52.570 ; + RECT 1937.420 42.520 1958.060 52.570 ; + RECT 1960.260 42.520 1968.140 792.440 ; + RECT 1970.340 42.520 2045.980 792.440 ; + RECT 2048.180 42.520 2056.060 792.440 ; + RECT 2058.260 787.230 2115.620 792.440 ; + RECT 2117.820 810.810 2134.020 812.570 ; + RECT 2117.820 787.815 2125.220 810.810 ; + RECT 2127.420 787.815 2134.020 810.810 ; + RECT 2117.820 787.230 2134.020 787.815 ; + RECT 2058.260 52.570 2134.020 787.230 ; + RECT 2058.260 42.520 2115.620 52.570 ; + RECT 1937.420 18.010 2115.620 42.520 ; + RECT 2117.820 50.810 2134.020 52.570 ; + RECT 2117.820 18.010 2125.220 50.810 ; + RECT 2127.420 18.010 2134.020 50.810 ; LAYER Metal5 ; RECT 10 0 2165 34.5 ; RECT 10 49.5 2165 79.5 ;
diff --git a/lef/fpga_struct_block.lef b/lef/fpga_struct_block.lef index 4148b33..e8ba8a5 100644 --- a/lef/fpga_struct_block.lef +++ b/lef/fpga_struct_block.lef
@@ -6,33 +6,29 @@ CLASS BLOCK ; FOREIGN fpga_struct_block ; ORIGIN 0.000 0.000 ; - SIZE 288.390 BY 301.830 ; + SIZE 250.000 BY 310.000 ; PIN VDD DIRECTION INOUT ; USE POWER ; PORT LAYER Metal4 ; - RECT 16.640 7.540 18.240 290.380 ; + RECT 16.640 7.540 18.240 302.140 ; END PORT LAYER Metal4 ; - RECT 66.640 7.540 68.240 290.380 ; + RECT 66.640 7.540 68.240 302.140 ; END PORT LAYER Metal4 ; - RECT 116.640 7.540 118.240 290.380 ; + RECT 116.640 7.540 118.240 302.140 ; END PORT LAYER Metal4 ; - RECT 166.640 7.540 168.240 290.380 ; + RECT 166.640 7.540 168.240 302.140 ; END PORT LAYER Metal4 ; - RECT 216.640 7.540 218.240 290.380 ; - END - PORT - LAYER Metal4 ; - RECT 266.640 7.540 268.240 290.380 ; + RECT 216.640 7.540 218.240 302.140 ; END END VDD PIN VSS @@ -40,23 +36,23 @@ USE GROUND ; PORT LAYER Metal4 ; - RECT 41.640 7.540 43.240 290.380 ; + RECT 41.640 7.540 43.240 302.140 ; END PORT LAYER Metal4 ; - RECT 91.640 7.540 93.240 290.380 ; + RECT 91.640 7.540 93.240 302.140 ; END PORT LAYER Metal4 ; - RECT 141.640 7.540 143.240 290.380 ; + RECT 141.640 7.540 143.240 302.140 ; END PORT LAYER Metal4 ; - RECT 191.640 7.540 193.240 290.380 ; + RECT 191.640 7.540 193.240 302.140 ; END PORT LAYER Metal4 ; - RECT 241.640 7.540 243.240 290.380 ; + RECT 241.640 7.540 243.240 302.140 ; END END VSS PIN clk_i @@ -64,7 +60,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 7.840 288.390 8.400 ; + RECT 246.000 11.760 250.000 12.320 ; END END clk_i PIN config_clk_i @@ -72,7 +68,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 8.960 297.830 9.520 301.830 ; + RECT 10.640 306.000 11.200 310.000 ; END END config_clk_i PIN config_ena_i @@ -80,7 +76,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 16.240 297.830 16.800 301.830 ; + RECT 16.800 306.000 17.360 310.000 ; END END config_ena_i PIN config_shift_i @@ -88,7 +84,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 23.520 297.830 24.080 301.830 ; + RECT 22.960 306.000 23.520 310.000 ; END END config_shift_i PIN config_shift_o @@ -96,7 +92,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 10.640 0.000 11.200 4.000 ; + RECT 10.080 0.000 10.640 4.000 ; END END config_shift_o PIN glb_rstn_i @@ -104,7 +100,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 30.800 297.830 31.360 301.830 ; + RECT 29.120 306.000 29.680 310.000 ; END END glb_rstn_i PIN inputs_down_i[0] @@ -112,7 +108,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 34.160 0.000 34.720 4.000 ; + RECT 30.240 0.000 30.800 4.000 ; END END inputs_down_i[0] PIN inputs_down_i[10] @@ -120,7 +116,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 112.560 0.000 113.120 4.000 ; + RECT 97.440 0.000 98.000 4.000 ; END END inputs_down_i[10] PIN inputs_down_i[11] @@ -128,7 +124,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 120.400 0.000 120.960 4.000 ; + RECT 104.160 0.000 104.720 4.000 ; END END inputs_down_i[11] PIN inputs_down_i[12] @@ -136,7 +132,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 128.240 0.000 128.800 4.000 ; + RECT 110.880 0.000 111.440 4.000 ; END END inputs_down_i[12] PIN inputs_down_i[13] @@ -144,7 +140,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 136.080 0.000 136.640 4.000 ; + RECT 117.600 0.000 118.160 4.000 ; END END inputs_down_i[13] PIN inputs_down_i[14] @@ -152,7 +148,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 143.920 0.000 144.480 4.000 ; + RECT 124.320 0.000 124.880 4.000 ; END END inputs_down_i[14] PIN inputs_down_i[15] @@ -160,7 +156,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 151.760 0.000 152.320 4.000 ; + RECT 131.040 0.000 131.600 4.000 ; END END inputs_down_i[15] PIN inputs_down_i[16] @@ -168,7 +164,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 159.600 0.000 160.160 4.000 ; + RECT 137.760 0.000 138.320 4.000 ; END END inputs_down_i[16] PIN inputs_down_i[17] @@ -176,7 +172,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 167.440 0.000 168.000 4.000 ; + RECT 144.480 0.000 145.040 4.000 ; END END inputs_down_i[17] PIN inputs_down_i[18] @@ -184,7 +180,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 175.280 0.000 175.840 4.000 ; + RECT 151.200 0.000 151.760 4.000 ; END END inputs_down_i[18] PIN inputs_down_i[19] @@ -192,7 +188,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 183.120 0.000 183.680 4.000 ; + RECT 157.920 0.000 158.480 4.000 ; END END inputs_down_i[19] PIN inputs_down_i[1] @@ -200,7 +196,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 42.000 0.000 42.560 4.000 ; + RECT 36.960 0.000 37.520 4.000 ; END END inputs_down_i[1] PIN inputs_down_i[20] @@ -208,7 +204,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 190.960 0.000 191.520 4.000 ; + RECT 164.640 0.000 165.200 4.000 ; END END inputs_down_i[20] PIN inputs_down_i[21] @@ -216,7 +212,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 198.800 0.000 199.360 4.000 ; + RECT 171.360 0.000 171.920 4.000 ; END END inputs_down_i[21] PIN inputs_down_i[22] @@ -224,7 +220,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 206.640 0.000 207.200 4.000 ; + RECT 178.080 0.000 178.640 4.000 ; END END inputs_down_i[22] PIN inputs_down_i[23] @@ -232,7 +228,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 214.480 0.000 215.040 4.000 ; + RECT 184.800 0.000 185.360 4.000 ; END END inputs_down_i[23] PIN inputs_down_i[24] @@ -240,7 +236,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 222.320 0.000 222.880 4.000 ; + RECT 191.520 0.000 192.080 4.000 ; END END inputs_down_i[24] PIN inputs_down_i[25] @@ -248,7 +244,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 230.160 0.000 230.720 4.000 ; + RECT 198.240 0.000 198.800 4.000 ; END END inputs_down_i[25] PIN inputs_down_i[26] @@ -256,7 +252,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 238.000 0.000 238.560 4.000 ; + RECT 204.960 0.000 205.520 4.000 ; END END inputs_down_i[26] PIN inputs_down_i[27] @@ -264,7 +260,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 245.840 0.000 246.400 4.000 ; + RECT 211.680 0.000 212.240 4.000 ; END END inputs_down_i[27] PIN inputs_down_i[28] @@ -272,7 +268,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 253.680 0.000 254.240 4.000 ; + RECT 218.400 0.000 218.960 4.000 ; END END inputs_down_i[28] PIN inputs_down_i[29] @@ -280,7 +276,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 261.520 0.000 262.080 4.000 ; + RECT 225.120 0.000 225.680 4.000 ; END END inputs_down_i[29] PIN inputs_down_i[2] @@ -288,7 +284,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 49.840 0.000 50.400 4.000 ; + RECT 43.680 0.000 44.240 4.000 ; END END inputs_down_i[2] PIN inputs_down_i[30] @@ -296,7 +292,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 269.360 0.000 269.920 4.000 ; + RECT 231.840 0.000 232.400 4.000 ; END END inputs_down_i[30] PIN inputs_down_i[31] @@ -304,7 +300,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 277.200 0.000 277.760 4.000 ; + RECT 238.560 0.000 239.120 4.000 ; END END inputs_down_i[31] PIN inputs_down_i[3] @@ -312,7 +308,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 57.680 0.000 58.240 4.000 ; + RECT 50.400 0.000 50.960 4.000 ; END END inputs_down_i[3] PIN inputs_down_i[4] @@ -320,7 +316,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 65.520 0.000 66.080 4.000 ; + RECT 57.120 0.000 57.680 4.000 ; END END inputs_down_i[4] PIN inputs_down_i[5] @@ -328,7 +324,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 73.360 0.000 73.920 4.000 ; + RECT 63.840 0.000 64.400 4.000 ; END END inputs_down_i[5] PIN inputs_down_i[6] @@ -336,7 +332,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 81.200 0.000 81.760 4.000 ; + RECT 70.560 0.000 71.120 4.000 ; END END inputs_down_i[6] PIN inputs_down_i[7] @@ -344,7 +340,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 89.040 0.000 89.600 4.000 ; + RECT 77.280 0.000 77.840 4.000 ; END END inputs_down_i[7] PIN inputs_down_i[8] @@ -352,7 +348,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 96.880 0.000 97.440 4.000 ; + RECT 84.000 0.000 84.560 4.000 ; END END inputs_down_i[8] PIN inputs_down_i[9] @@ -360,7 +356,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 104.720 0.000 105.280 4.000 ; + RECT 90.720 0.000 91.280 4.000 ; END END inputs_down_i[9] PIN inputs_left_i[0] @@ -368,7 +364,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 28.560 4.000 29.120 ; + RECT 0.000 24.640 4.000 25.200 ; END END inputs_left_i[0] PIN inputs_left_i[10] @@ -376,7 +372,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 112.560 4.000 113.120 ; + RECT 0.000 114.240 4.000 114.800 ; END END inputs_left_i[10] PIN inputs_left_i[11] @@ -384,7 +380,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 120.960 4.000 121.520 ; + RECT 0.000 123.200 4.000 123.760 ; END END inputs_left_i[11] PIN inputs_left_i[12] @@ -392,7 +388,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 129.360 4.000 129.920 ; + RECT 0.000 132.160 4.000 132.720 ; END END inputs_left_i[12] PIN inputs_left_i[13] @@ -400,7 +396,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 137.760 4.000 138.320 ; + RECT 0.000 141.120 4.000 141.680 ; END END inputs_left_i[13] PIN inputs_left_i[14] @@ -408,7 +404,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 146.160 4.000 146.720 ; + RECT 0.000 150.080 4.000 150.640 ; END END inputs_left_i[14] PIN inputs_left_i[15] @@ -416,7 +412,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 154.560 4.000 155.120 ; + RECT 0.000 159.040 4.000 159.600 ; END END inputs_left_i[15] PIN inputs_left_i[16] @@ -424,7 +420,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 162.960 4.000 163.520 ; + RECT 0.000 168.000 4.000 168.560 ; END END inputs_left_i[16] PIN inputs_left_i[17] @@ -432,7 +428,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 171.360 4.000 171.920 ; + RECT 0.000 176.960 4.000 177.520 ; END END inputs_left_i[17] PIN inputs_left_i[18] @@ -440,7 +436,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 179.760 4.000 180.320 ; + RECT 0.000 185.920 4.000 186.480 ; END END inputs_left_i[18] PIN inputs_left_i[19] @@ -448,7 +444,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 188.160 4.000 188.720 ; + RECT 0.000 194.880 4.000 195.440 ; END END inputs_left_i[19] PIN inputs_left_i[1] @@ -456,7 +452,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 36.960 4.000 37.520 ; + RECT 0.000 33.600 4.000 34.160 ; END END inputs_left_i[1] PIN inputs_left_i[20] @@ -464,7 +460,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 196.560 4.000 197.120 ; + RECT 0.000 203.840 4.000 204.400 ; END END inputs_left_i[20] PIN inputs_left_i[21] @@ -472,7 +468,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 204.960 4.000 205.520 ; + RECT 0.000 212.800 4.000 213.360 ; END END inputs_left_i[21] PIN inputs_left_i[22] @@ -480,7 +476,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 213.360 4.000 213.920 ; + RECT 0.000 221.760 4.000 222.320 ; END END inputs_left_i[22] PIN inputs_left_i[23] @@ -488,7 +484,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 221.760 4.000 222.320 ; + RECT 0.000 230.720 4.000 231.280 ; END END inputs_left_i[23] PIN inputs_left_i[24] @@ -496,7 +492,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 230.160 4.000 230.720 ; + RECT 0.000 239.680 4.000 240.240 ; END END inputs_left_i[24] PIN inputs_left_i[25] @@ -504,7 +500,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 238.560 4.000 239.120 ; + RECT 0.000 248.640 4.000 249.200 ; END END inputs_left_i[25] PIN inputs_left_i[26] @@ -512,7 +508,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 246.960 4.000 247.520 ; + RECT 0.000 257.600 4.000 258.160 ; END END inputs_left_i[26] PIN inputs_left_i[27] @@ -520,7 +516,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 255.360 4.000 255.920 ; + RECT 0.000 266.560 4.000 267.120 ; END END inputs_left_i[27] PIN inputs_left_i[28] @@ -528,7 +524,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 263.760 4.000 264.320 ; + RECT 0.000 275.520 4.000 276.080 ; END END inputs_left_i[28] PIN inputs_left_i[29] @@ -536,7 +532,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 272.160 4.000 272.720 ; + RECT 0.000 284.480 4.000 285.040 ; END END inputs_left_i[29] PIN inputs_left_i[2] @@ -544,7 +540,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 45.360 4.000 45.920 ; + RECT 0.000 42.560 4.000 43.120 ; END END inputs_left_i[2] PIN inputs_left_i[30] @@ -552,7 +548,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 280.560 4.000 281.120 ; + RECT 0.000 293.440 4.000 294.000 ; END END inputs_left_i[30] PIN inputs_left_i[31] @@ -560,7 +556,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 288.960 4.000 289.520 ; + RECT 0.000 302.400 4.000 302.960 ; END END inputs_left_i[31] PIN inputs_left_i[3] @@ -568,7 +564,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 53.760 4.000 54.320 ; + RECT 0.000 51.520 4.000 52.080 ; END END inputs_left_i[3] PIN inputs_left_i[4] @@ -576,7 +572,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 62.160 4.000 62.720 ; + RECT 0.000 60.480 4.000 61.040 ; END END inputs_left_i[4] PIN inputs_left_i[5] @@ -584,7 +580,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 70.560 4.000 71.120 ; + RECT 0.000 69.440 4.000 70.000 ; END END inputs_left_i[5] PIN inputs_left_i[6] @@ -592,7 +588,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 78.960 4.000 79.520 ; + RECT 0.000 78.400 4.000 78.960 ; END END inputs_left_i[6] PIN inputs_left_i[7] @@ -608,7 +604,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 95.760 4.000 96.320 ; + RECT 0.000 96.320 4.000 96.880 ; END END inputs_left_i[8] PIN inputs_left_i[9] @@ -616,7 +612,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 104.160 4.000 104.720 ; + RECT 0.000 105.280 4.000 105.840 ; END END inputs_left_i[9] PIN inputs_right_i[0] @@ -624,7 +620,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 33.040 288.390 33.600 ; + RECT 246.000 36.960 250.000 37.520 ; END END inputs_right_i[0] PIN inputs_right_i[10] @@ -632,7 +628,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 117.040 288.390 117.600 ; + RECT 246.000 120.960 250.000 121.520 ; END END inputs_right_i[10] PIN inputs_right_i[11] @@ -640,7 +636,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 125.440 288.390 126.000 ; + RECT 246.000 129.360 250.000 129.920 ; END END inputs_right_i[11] PIN inputs_right_i[12] @@ -648,7 +644,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 133.840 288.390 134.400 ; + RECT 246.000 137.760 250.000 138.320 ; END END inputs_right_i[12] PIN inputs_right_i[13] @@ -656,7 +652,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 142.240 288.390 142.800 ; + RECT 246.000 146.160 250.000 146.720 ; END END inputs_right_i[13] PIN inputs_right_i[14] @@ -664,7 +660,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 150.640 288.390 151.200 ; + RECT 246.000 154.560 250.000 155.120 ; END END inputs_right_i[14] PIN inputs_right_i[15] @@ -672,7 +668,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 159.040 288.390 159.600 ; + RECT 246.000 162.960 250.000 163.520 ; END END inputs_right_i[15] PIN inputs_right_i[16] @@ -680,7 +676,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 167.440 288.390 168.000 ; + RECT 246.000 171.360 250.000 171.920 ; END END inputs_right_i[16] PIN inputs_right_i[17] @@ -688,7 +684,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 175.840 288.390 176.400 ; + RECT 246.000 179.760 250.000 180.320 ; END END inputs_right_i[17] PIN inputs_right_i[18] @@ -696,7 +692,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 184.240 288.390 184.800 ; + RECT 246.000 188.160 250.000 188.720 ; END END inputs_right_i[18] PIN inputs_right_i[19] @@ -704,7 +700,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 192.640 288.390 193.200 ; + RECT 246.000 196.560 250.000 197.120 ; END END inputs_right_i[19] PIN inputs_right_i[1] @@ -712,7 +708,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 41.440 288.390 42.000 ; + RECT 246.000 45.360 250.000 45.920 ; END END inputs_right_i[1] PIN inputs_right_i[20] @@ -720,7 +716,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 201.040 288.390 201.600 ; + RECT 246.000 204.960 250.000 205.520 ; END END inputs_right_i[20] PIN inputs_right_i[21] @@ -728,7 +724,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 209.440 288.390 210.000 ; + RECT 246.000 213.360 250.000 213.920 ; END END inputs_right_i[21] PIN inputs_right_i[22] @@ -736,7 +732,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 217.840 288.390 218.400 ; + RECT 246.000 221.760 250.000 222.320 ; END END inputs_right_i[22] PIN inputs_right_i[23] @@ -744,7 +740,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 226.240 288.390 226.800 ; + RECT 246.000 230.160 250.000 230.720 ; END END inputs_right_i[23] PIN inputs_right_i[24] @@ -752,7 +748,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 234.640 288.390 235.200 ; + RECT 246.000 238.560 250.000 239.120 ; END END inputs_right_i[24] PIN inputs_right_i[25] @@ -760,7 +756,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 243.040 288.390 243.600 ; + RECT 246.000 246.960 250.000 247.520 ; END END inputs_right_i[25] PIN inputs_right_i[26] @@ -768,7 +764,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 251.440 288.390 252.000 ; + RECT 246.000 255.360 250.000 255.920 ; END END inputs_right_i[26] PIN inputs_right_i[27] @@ -776,7 +772,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 259.840 288.390 260.400 ; + RECT 246.000 263.760 250.000 264.320 ; END END inputs_right_i[27] PIN inputs_right_i[28] @@ -784,7 +780,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 268.240 288.390 268.800 ; + RECT 246.000 272.160 250.000 272.720 ; END END inputs_right_i[28] PIN inputs_right_i[29] @@ -792,7 +788,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 276.640 288.390 277.200 ; + RECT 246.000 280.560 250.000 281.120 ; END END inputs_right_i[29] PIN inputs_right_i[2] @@ -800,7 +796,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 49.840 288.390 50.400 ; + RECT 246.000 53.760 250.000 54.320 ; END END inputs_right_i[2] PIN inputs_right_i[30] @@ -808,7 +804,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 285.040 288.390 285.600 ; + RECT 246.000 288.960 250.000 289.520 ; END END inputs_right_i[30] PIN inputs_right_i[31] @@ -816,7 +812,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 293.440 288.390 294.000 ; + RECT 246.000 297.360 250.000 297.920 ; END END inputs_right_i[31] PIN inputs_right_i[3] @@ -824,7 +820,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 58.240 288.390 58.800 ; + RECT 246.000 62.160 250.000 62.720 ; END END inputs_right_i[3] PIN inputs_right_i[4] @@ -832,7 +828,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 66.640 288.390 67.200 ; + RECT 246.000 70.560 250.000 71.120 ; END END inputs_right_i[4] PIN inputs_right_i[5] @@ -840,7 +836,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 75.040 288.390 75.600 ; + RECT 246.000 78.960 250.000 79.520 ; END END inputs_right_i[5] PIN inputs_right_i[6] @@ -848,7 +844,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 83.440 288.390 84.000 ; + RECT 246.000 87.360 250.000 87.920 ; END END inputs_right_i[6] PIN inputs_right_i[7] @@ -856,7 +852,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 91.840 288.390 92.400 ; + RECT 246.000 95.760 250.000 96.320 ; END END inputs_right_i[7] PIN inputs_right_i[8] @@ -864,7 +860,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 100.240 288.390 100.800 ; + RECT 246.000 104.160 250.000 104.720 ; END END inputs_right_i[8] PIN inputs_right_i[9] @@ -872,7 +868,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 108.640 288.390 109.200 ; + RECT 246.000 112.560 250.000 113.120 ; END END inputs_right_i[9] PIN inputs_up_i[0] @@ -880,7 +876,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 52.640 297.830 53.200 301.830 ; + RECT 47.600 306.000 48.160 310.000 ; END END inputs_up_i[0] PIN inputs_up_i[10] @@ -888,7 +884,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 125.440 297.830 126.000 301.830 ; + RECT 109.200 306.000 109.760 310.000 ; END END inputs_up_i[10] PIN inputs_up_i[11] @@ -896,7 +892,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 132.720 297.830 133.280 301.830 ; + RECT 115.360 306.000 115.920 310.000 ; END END inputs_up_i[11] PIN inputs_up_i[12] @@ -904,7 +900,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 140.000 297.830 140.560 301.830 ; + RECT 121.520 306.000 122.080 310.000 ; END END inputs_up_i[12] PIN inputs_up_i[13] @@ -912,7 +908,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 147.280 297.830 147.840 301.830 ; + RECT 127.680 306.000 128.240 310.000 ; END END inputs_up_i[13] PIN inputs_up_i[14] @@ -920,7 +916,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 154.560 297.830 155.120 301.830 ; + RECT 133.840 306.000 134.400 310.000 ; END END inputs_up_i[14] PIN inputs_up_i[15] @@ -928,7 +924,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 161.840 297.830 162.400 301.830 ; + RECT 140.000 306.000 140.560 310.000 ; END END inputs_up_i[15] PIN inputs_up_i[16] @@ -936,7 +932,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 169.120 297.830 169.680 301.830 ; + RECT 146.160 306.000 146.720 310.000 ; END END inputs_up_i[16] PIN inputs_up_i[17] @@ -944,7 +940,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 176.400 297.830 176.960 301.830 ; + RECT 152.320 306.000 152.880 310.000 ; END END inputs_up_i[17] PIN inputs_up_i[18] @@ -952,7 +948,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 183.680 297.830 184.240 301.830 ; + RECT 158.480 306.000 159.040 310.000 ; END END inputs_up_i[18] PIN inputs_up_i[19] @@ -960,7 +956,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 190.960 297.830 191.520 301.830 ; + RECT 164.640 306.000 165.200 310.000 ; END END inputs_up_i[19] PIN inputs_up_i[1] @@ -968,7 +964,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 59.920 297.830 60.480 301.830 ; + RECT 53.760 306.000 54.320 310.000 ; END END inputs_up_i[1] PIN inputs_up_i[20] @@ -976,7 +972,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 198.240 297.830 198.800 301.830 ; + RECT 170.800 306.000 171.360 310.000 ; END END inputs_up_i[20] PIN inputs_up_i[21] @@ -984,7 +980,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 205.520 297.830 206.080 301.830 ; + RECT 176.960 306.000 177.520 310.000 ; END END inputs_up_i[21] PIN inputs_up_i[22] @@ -992,7 +988,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 212.800 297.830 213.360 301.830 ; + RECT 183.120 306.000 183.680 310.000 ; END END inputs_up_i[22] PIN inputs_up_i[23] @@ -1000,7 +996,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 220.080 297.830 220.640 301.830 ; + RECT 189.280 306.000 189.840 310.000 ; END END inputs_up_i[23] PIN inputs_up_i[24] @@ -1008,7 +1004,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 227.360 297.830 227.920 301.830 ; + RECT 195.440 306.000 196.000 310.000 ; END END inputs_up_i[24] PIN inputs_up_i[25] @@ -1016,7 +1012,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 234.640 297.830 235.200 301.830 ; + RECT 201.600 306.000 202.160 310.000 ; END END inputs_up_i[25] PIN inputs_up_i[26] @@ -1024,7 +1020,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 241.920 297.830 242.480 301.830 ; + RECT 207.760 306.000 208.320 310.000 ; END END inputs_up_i[26] PIN inputs_up_i[27] @@ -1032,7 +1028,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 249.200 297.830 249.760 301.830 ; + RECT 213.920 306.000 214.480 310.000 ; END END inputs_up_i[27] PIN inputs_up_i[28] @@ -1040,7 +1036,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 256.480 297.830 257.040 301.830 ; + RECT 220.080 306.000 220.640 310.000 ; END END inputs_up_i[28] PIN inputs_up_i[29] @@ -1048,7 +1044,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 263.760 297.830 264.320 301.830 ; + RECT 226.240 306.000 226.800 310.000 ; END END inputs_up_i[29] PIN inputs_up_i[2] @@ -1056,7 +1052,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 67.200 297.830 67.760 301.830 ; + RECT 59.920 306.000 60.480 310.000 ; END END inputs_up_i[2] PIN inputs_up_i[30] @@ -1064,7 +1060,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 271.040 297.830 271.600 301.830 ; + RECT 232.400 306.000 232.960 310.000 ; END END inputs_up_i[30] PIN inputs_up_i[31] @@ -1072,7 +1068,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 278.320 297.830 278.880 301.830 ; + RECT 238.560 306.000 239.120 310.000 ; END END inputs_up_i[31] PIN inputs_up_i[3] @@ -1080,7 +1076,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 74.480 297.830 75.040 301.830 ; + RECT 66.080 306.000 66.640 310.000 ; END END inputs_up_i[3] PIN inputs_up_i[4] @@ -1088,7 +1084,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 81.760 297.830 82.320 301.830 ; + RECT 72.240 306.000 72.800 310.000 ; END END inputs_up_i[4] PIN inputs_up_i[5] @@ -1096,7 +1092,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 89.040 297.830 89.600 301.830 ; + RECT 78.400 306.000 78.960 310.000 ; END END inputs_up_i[5] PIN inputs_up_i[6] @@ -1104,7 +1100,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 96.320 297.830 96.880 301.830 ; + RECT 84.560 306.000 85.120 310.000 ; END END inputs_up_i[6] PIN inputs_up_i[7] @@ -1112,7 +1108,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 103.600 297.830 104.160 301.830 ; + RECT 90.720 306.000 91.280 310.000 ; END END inputs_up_i[7] PIN inputs_up_i[8] @@ -1120,7 +1116,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 110.880 297.830 111.440 301.830 ; + RECT 96.880 306.000 97.440 310.000 ; END END inputs_up_i[8] PIN inputs_up_i[9] @@ -1128,7 +1124,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 118.160 297.830 118.720 301.830 ; + RECT 103.040 306.000 103.600 310.000 ; END END inputs_up_i[9] PIN outputs_o[0] @@ -1136,7 +1132,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 38.080 297.830 38.640 301.830 ; + RECT 35.280 306.000 35.840 310.000 ; END END outputs_o[0] PIN outputs_o[1] @@ -1144,7 +1140,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 16.240 288.390 16.800 ; + RECT 246.000 20.160 250.000 20.720 ; END END outputs_o[1] PIN outputs_o[2] @@ -1152,7 +1148,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 18.480 0.000 19.040 4.000 ; + RECT 16.800 0.000 17.360 4.000 ; END END outputs_o[2] PIN outputs_o[3] @@ -1160,7 +1156,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 11.760 4.000 12.320 ; + RECT 0.000 6.720 4.000 7.280 ; END END outputs_o[3] PIN outputs_o[4] @@ -1168,7 +1164,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 45.360 297.830 45.920 301.830 ; + RECT 41.440 306.000 42.000 310.000 ; END END outputs_o[4] PIN outputs_o[5] @@ -1176,7 +1172,7 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 284.390 24.640 288.390 25.200 ; + RECT 246.000 28.560 250.000 29.120 ; END END outputs_o[5] PIN outputs_o[6] @@ -1184,7 +1180,7 @@ USE SIGNAL ; PORT LAYER Metal2 ; - RECT 26.320 0.000 26.880 4.000 ; + RECT 23.520 0.000 24.080 4.000 ; END END outputs_o[6] PIN outputs_o[7] @@ -1192,242 +1188,239 @@ USE SIGNAL ; PORT LAYER Metal3 ; - RECT 0.000 20.160 4.000 20.720 ; + RECT 0.000 15.680 4.000 16.240 ; END END outputs_o[7] OBS LAYER Metal1 ; - RECT 1.120 7.540 286.720 293.290 ; + RECT 1.120 7.540 248.640 303.370 ; LAYER Metal2 ; - RECT 0.700 297.530 8.660 298.340 ; - RECT 9.820 297.530 15.940 298.340 ; - RECT 17.100 297.530 23.220 298.340 ; - RECT 24.380 297.530 30.500 298.340 ; - RECT 31.660 297.530 37.780 298.340 ; - RECT 38.940 297.530 45.060 298.340 ; - RECT 46.220 297.530 52.340 298.340 ; - RECT 53.500 297.530 59.620 298.340 ; - RECT 60.780 297.530 66.900 298.340 ; - RECT 68.060 297.530 74.180 298.340 ; - RECT 75.340 297.530 81.460 298.340 ; - RECT 82.620 297.530 88.740 298.340 ; - RECT 89.900 297.530 96.020 298.340 ; - RECT 97.180 297.530 103.300 298.340 ; - RECT 104.460 297.530 110.580 298.340 ; - RECT 111.740 297.530 117.860 298.340 ; - RECT 119.020 297.530 125.140 298.340 ; - RECT 126.300 297.530 132.420 298.340 ; - RECT 133.580 297.530 139.700 298.340 ; - RECT 140.860 297.530 146.980 298.340 ; - RECT 148.140 297.530 154.260 298.340 ; - RECT 155.420 297.530 161.540 298.340 ; - RECT 162.700 297.530 168.820 298.340 ; - RECT 169.980 297.530 176.100 298.340 ; - RECT 177.260 297.530 183.380 298.340 ; - RECT 184.540 297.530 190.660 298.340 ; - RECT 191.820 297.530 197.940 298.340 ; - RECT 199.100 297.530 205.220 298.340 ; - RECT 206.380 297.530 212.500 298.340 ; - RECT 213.660 297.530 219.780 298.340 ; - RECT 220.940 297.530 227.060 298.340 ; - RECT 228.220 297.530 234.340 298.340 ; - RECT 235.500 297.530 241.620 298.340 ; - RECT 242.780 297.530 248.900 298.340 ; - RECT 250.060 297.530 256.180 298.340 ; - RECT 257.340 297.530 263.460 298.340 ; - RECT 264.620 297.530 270.740 298.340 ; - RECT 271.900 297.530 278.020 298.340 ; - RECT 279.180 297.530 288.260 298.340 ; - RECT 0.700 4.300 288.260 297.530 ; - RECT 0.700 0.090 10.340 4.300 ; - RECT 11.500 0.090 18.180 4.300 ; - RECT 19.340 0.090 26.020 4.300 ; - RECT 27.180 0.090 33.860 4.300 ; - RECT 35.020 0.090 41.700 4.300 ; - RECT 42.860 0.090 49.540 4.300 ; - RECT 50.700 0.090 57.380 4.300 ; - RECT 58.540 0.090 65.220 4.300 ; - RECT 66.380 0.090 73.060 4.300 ; - RECT 74.220 0.090 80.900 4.300 ; - RECT 82.060 0.090 88.740 4.300 ; - RECT 89.900 0.090 96.580 4.300 ; - RECT 97.740 0.090 104.420 4.300 ; - RECT 105.580 0.090 112.260 4.300 ; - RECT 113.420 0.090 120.100 4.300 ; - RECT 121.260 0.090 127.940 4.300 ; - RECT 129.100 0.090 135.780 4.300 ; - RECT 136.940 0.090 143.620 4.300 ; - RECT 144.780 0.090 151.460 4.300 ; - RECT 152.620 0.090 159.300 4.300 ; - RECT 160.460 0.090 167.140 4.300 ; - RECT 168.300 0.090 174.980 4.300 ; - RECT 176.140 0.090 182.820 4.300 ; - RECT 183.980 0.090 190.660 4.300 ; - RECT 191.820 0.090 198.500 4.300 ; - RECT 199.660 0.090 206.340 4.300 ; - RECT 207.500 0.090 214.180 4.300 ; - RECT 215.340 0.090 222.020 4.300 ; - RECT 223.180 0.090 229.860 4.300 ; - RECT 231.020 0.090 237.700 4.300 ; - RECT 238.860 0.090 245.540 4.300 ; - RECT 246.700 0.090 253.380 4.300 ; - RECT 254.540 0.090 261.220 4.300 ; - RECT 262.380 0.090 269.060 4.300 ; - RECT 270.220 0.090 276.900 4.300 ; - RECT 278.060 0.090 288.260 4.300 ; + RECT 0.140 305.700 10.340 306.740 ; + RECT 11.500 305.700 16.500 306.740 ; + RECT 17.660 305.700 22.660 306.740 ; + RECT 23.820 305.700 28.820 306.740 ; + RECT 29.980 305.700 34.980 306.740 ; + RECT 36.140 305.700 41.140 306.740 ; + RECT 42.300 305.700 47.300 306.740 ; + RECT 48.460 305.700 53.460 306.740 ; + RECT 54.620 305.700 59.620 306.740 ; + RECT 60.780 305.700 65.780 306.740 ; + RECT 66.940 305.700 71.940 306.740 ; + RECT 73.100 305.700 78.100 306.740 ; + RECT 79.260 305.700 84.260 306.740 ; + RECT 85.420 305.700 90.420 306.740 ; + RECT 91.580 305.700 96.580 306.740 ; + RECT 97.740 305.700 102.740 306.740 ; + RECT 103.900 305.700 108.900 306.740 ; + RECT 110.060 305.700 115.060 306.740 ; + RECT 116.220 305.700 121.220 306.740 ; + RECT 122.380 305.700 127.380 306.740 ; + RECT 128.540 305.700 133.540 306.740 ; + RECT 134.700 305.700 139.700 306.740 ; + RECT 140.860 305.700 145.860 306.740 ; + RECT 147.020 305.700 152.020 306.740 ; + RECT 153.180 305.700 158.180 306.740 ; + RECT 159.340 305.700 164.340 306.740 ; + RECT 165.500 305.700 170.500 306.740 ; + RECT 171.660 305.700 176.660 306.740 ; + RECT 177.820 305.700 182.820 306.740 ; + RECT 183.980 305.700 188.980 306.740 ; + RECT 190.140 305.700 195.140 306.740 ; + RECT 196.300 305.700 201.300 306.740 ; + RECT 202.460 305.700 207.460 306.740 ; + RECT 208.620 305.700 213.620 306.740 ; + RECT 214.780 305.700 219.780 306.740 ; + RECT 220.940 305.700 225.940 306.740 ; + RECT 227.100 305.700 232.100 306.740 ; + RECT 233.260 305.700 238.260 306.740 ; + RECT 239.420 305.700 249.620 306.740 ; + RECT 0.140 4.300 249.620 305.700 ; + RECT 0.140 0.090 9.780 4.300 ; + RECT 10.940 0.090 16.500 4.300 ; + RECT 17.660 0.090 23.220 4.300 ; + RECT 24.380 0.090 29.940 4.300 ; + RECT 31.100 0.090 36.660 4.300 ; + RECT 37.820 0.090 43.380 4.300 ; + RECT 44.540 0.090 50.100 4.300 ; + RECT 51.260 0.090 56.820 4.300 ; + RECT 57.980 0.090 63.540 4.300 ; + RECT 64.700 0.090 70.260 4.300 ; + RECT 71.420 0.090 76.980 4.300 ; + RECT 78.140 0.090 83.700 4.300 ; + RECT 84.860 0.090 90.420 4.300 ; + RECT 91.580 0.090 97.140 4.300 ; + RECT 98.300 0.090 103.860 4.300 ; + RECT 105.020 0.090 110.580 4.300 ; + RECT 111.740 0.090 117.300 4.300 ; + RECT 118.460 0.090 124.020 4.300 ; + RECT 125.180 0.090 130.740 4.300 ; + RECT 131.900 0.090 137.460 4.300 ; + RECT 138.620 0.090 144.180 4.300 ; + RECT 145.340 0.090 150.900 4.300 ; + RECT 152.060 0.090 157.620 4.300 ; + RECT 158.780 0.090 164.340 4.300 ; + RECT 165.500 0.090 171.060 4.300 ; + RECT 172.220 0.090 177.780 4.300 ; + RECT 178.940 0.090 184.500 4.300 ; + RECT 185.660 0.090 191.220 4.300 ; + RECT 192.380 0.090 197.940 4.300 ; + RECT 199.100 0.090 204.660 4.300 ; + RECT 205.820 0.090 211.380 4.300 ; + RECT 212.540 0.090 218.100 4.300 ; + RECT 219.260 0.090 224.820 4.300 ; + RECT 225.980 0.090 231.540 4.300 ; + RECT 232.700 0.090 238.260 4.300 ; + RECT 239.420 0.090 249.620 4.300 ; LAYER Metal3 ; - RECT 0.650 294.300 288.310 296.100 ; - RECT 0.650 293.140 284.090 294.300 ; - RECT 0.650 289.820 288.310 293.140 ; - RECT 4.300 288.660 288.310 289.820 ; - RECT 0.650 285.900 288.310 288.660 ; - RECT 0.650 284.740 284.090 285.900 ; - RECT 0.650 281.420 288.310 284.740 ; - RECT 4.300 280.260 288.310 281.420 ; - RECT 0.650 277.500 288.310 280.260 ; - RECT 0.650 276.340 284.090 277.500 ; - RECT 0.650 273.020 288.310 276.340 ; - RECT 4.300 271.860 288.310 273.020 ; - RECT 0.650 269.100 288.310 271.860 ; - RECT 0.650 267.940 284.090 269.100 ; - RECT 0.650 264.620 288.310 267.940 ; - RECT 4.300 263.460 288.310 264.620 ; - RECT 0.650 260.700 288.310 263.460 ; - RECT 0.650 259.540 284.090 260.700 ; - RECT 0.650 256.220 288.310 259.540 ; - RECT 4.300 255.060 288.310 256.220 ; - RECT 0.650 252.300 288.310 255.060 ; - RECT 0.650 251.140 284.090 252.300 ; - RECT 0.650 247.820 288.310 251.140 ; - RECT 4.300 246.660 288.310 247.820 ; - RECT 0.650 243.900 288.310 246.660 ; - RECT 0.650 242.740 284.090 243.900 ; - RECT 0.650 239.420 288.310 242.740 ; - RECT 4.300 238.260 288.310 239.420 ; - RECT 0.650 235.500 288.310 238.260 ; - RECT 0.650 234.340 284.090 235.500 ; - RECT 0.650 231.020 288.310 234.340 ; - RECT 4.300 229.860 288.310 231.020 ; - RECT 0.650 227.100 288.310 229.860 ; - RECT 0.650 225.940 284.090 227.100 ; - RECT 0.650 222.620 288.310 225.940 ; - RECT 4.300 221.460 288.310 222.620 ; - RECT 0.650 218.700 288.310 221.460 ; - RECT 0.650 217.540 284.090 218.700 ; - RECT 0.650 214.220 288.310 217.540 ; - RECT 4.300 213.060 288.310 214.220 ; - RECT 0.650 210.300 288.310 213.060 ; - RECT 0.650 209.140 284.090 210.300 ; - RECT 0.650 205.820 288.310 209.140 ; - RECT 4.300 204.660 288.310 205.820 ; - RECT 0.650 201.900 288.310 204.660 ; - RECT 0.650 200.740 284.090 201.900 ; - RECT 0.650 197.420 288.310 200.740 ; - RECT 4.300 196.260 288.310 197.420 ; - RECT 0.650 193.500 288.310 196.260 ; - RECT 0.650 192.340 284.090 193.500 ; - RECT 0.650 189.020 288.310 192.340 ; - RECT 4.300 187.860 288.310 189.020 ; - RECT 0.650 185.100 288.310 187.860 ; - RECT 0.650 183.940 284.090 185.100 ; - RECT 0.650 180.620 288.310 183.940 ; - RECT 4.300 179.460 288.310 180.620 ; - RECT 0.650 176.700 288.310 179.460 ; - RECT 0.650 175.540 284.090 176.700 ; - RECT 0.650 172.220 288.310 175.540 ; - RECT 4.300 171.060 288.310 172.220 ; - RECT 0.650 168.300 288.310 171.060 ; - RECT 0.650 167.140 284.090 168.300 ; - RECT 0.650 163.820 288.310 167.140 ; - RECT 4.300 162.660 288.310 163.820 ; - RECT 0.650 159.900 288.310 162.660 ; - RECT 0.650 158.740 284.090 159.900 ; - RECT 0.650 155.420 288.310 158.740 ; - RECT 4.300 154.260 288.310 155.420 ; - RECT 0.650 151.500 288.310 154.260 ; - RECT 0.650 150.340 284.090 151.500 ; - RECT 0.650 147.020 288.310 150.340 ; - RECT 4.300 145.860 288.310 147.020 ; - RECT 0.650 143.100 288.310 145.860 ; - RECT 0.650 141.940 284.090 143.100 ; - RECT 0.650 138.620 288.310 141.940 ; - RECT 4.300 137.460 288.310 138.620 ; - RECT 0.650 134.700 288.310 137.460 ; - RECT 0.650 133.540 284.090 134.700 ; - RECT 0.650 130.220 288.310 133.540 ; - RECT 4.300 129.060 288.310 130.220 ; - RECT 0.650 126.300 288.310 129.060 ; - RECT 0.650 125.140 284.090 126.300 ; - RECT 0.650 121.820 288.310 125.140 ; - RECT 4.300 120.660 288.310 121.820 ; - RECT 0.650 117.900 288.310 120.660 ; - RECT 0.650 116.740 284.090 117.900 ; - RECT 0.650 113.420 288.310 116.740 ; - RECT 4.300 112.260 288.310 113.420 ; - RECT 0.650 109.500 288.310 112.260 ; - RECT 0.650 108.340 284.090 109.500 ; - RECT 0.650 105.020 288.310 108.340 ; - RECT 4.300 103.860 288.310 105.020 ; - RECT 0.650 101.100 288.310 103.860 ; - RECT 0.650 99.940 284.090 101.100 ; - RECT 0.650 96.620 288.310 99.940 ; - RECT 4.300 95.460 288.310 96.620 ; - RECT 0.650 92.700 288.310 95.460 ; - RECT 0.650 91.540 284.090 92.700 ; - RECT 0.650 88.220 288.310 91.540 ; - RECT 4.300 87.060 288.310 88.220 ; - RECT 0.650 84.300 288.310 87.060 ; - RECT 0.650 83.140 284.090 84.300 ; - RECT 0.650 79.820 288.310 83.140 ; - RECT 4.300 78.660 288.310 79.820 ; - RECT 0.650 75.900 288.310 78.660 ; - RECT 0.650 74.740 284.090 75.900 ; - RECT 0.650 71.420 288.310 74.740 ; - RECT 4.300 70.260 288.310 71.420 ; - RECT 0.650 67.500 288.310 70.260 ; - RECT 0.650 66.340 284.090 67.500 ; - RECT 0.650 63.020 288.310 66.340 ; - RECT 4.300 61.860 288.310 63.020 ; - RECT 0.650 59.100 288.310 61.860 ; - RECT 0.650 57.940 284.090 59.100 ; - RECT 0.650 54.620 288.310 57.940 ; - RECT 4.300 53.460 288.310 54.620 ; - RECT 0.650 50.700 288.310 53.460 ; - RECT 0.650 49.540 284.090 50.700 ; - RECT 0.650 46.220 288.310 49.540 ; - RECT 4.300 45.060 288.310 46.220 ; - RECT 0.650 42.300 288.310 45.060 ; - RECT 0.650 41.140 284.090 42.300 ; - RECT 0.650 37.820 288.310 41.140 ; - RECT 4.300 36.660 288.310 37.820 ; - RECT 0.650 33.900 288.310 36.660 ; - RECT 0.650 32.740 284.090 33.900 ; - RECT 0.650 29.420 288.310 32.740 ; - RECT 4.300 28.260 288.310 29.420 ; - RECT 0.650 25.500 288.310 28.260 ; - RECT 0.650 24.340 284.090 25.500 ; - RECT 0.650 21.020 288.310 24.340 ; - RECT 4.300 19.860 288.310 21.020 ; - RECT 0.650 17.100 288.310 19.860 ; - RECT 0.650 15.940 284.090 17.100 ; - RECT 0.650 12.620 288.310 15.940 ; - RECT 4.300 11.460 288.310 12.620 ; - RECT 0.650 8.700 288.310 11.460 ; - RECT 0.650 7.540 284.090 8.700 ; - RECT 0.650 0.140 288.310 7.540 ; + RECT 0.090 303.260 249.670 305.620 ; + RECT 4.300 302.100 249.670 303.260 ; + RECT 0.090 298.220 249.670 302.100 ; + RECT 0.090 297.060 245.700 298.220 ; + RECT 0.090 294.300 249.670 297.060 ; + RECT 4.300 293.140 249.670 294.300 ; + RECT 0.090 289.820 249.670 293.140 ; + RECT 0.090 288.660 245.700 289.820 ; + RECT 0.090 285.340 249.670 288.660 ; + RECT 4.300 284.180 249.670 285.340 ; + RECT 0.090 281.420 249.670 284.180 ; + RECT 0.090 280.260 245.700 281.420 ; + RECT 0.090 276.380 249.670 280.260 ; + RECT 4.300 275.220 249.670 276.380 ; + RECT 0.090 273.020 249.670 275.220 ; + RECT 0.090 271.860 245.700 273.020 ; + RECT 0.090 267.420 249.670 271.860 ; + RECT 4.300 266.260 249.670 267.420 ; + RECT 0.090 264.620 249.670 266.260 ; + RECT 0.090 263.460 245.700 264.620 ; + RECT 0.090 258.460 249.670 263.460 ; + RECT 4.300 257.300 249.670 258.460 ; + RECT 0.090 256.220 249.670 257.300 ; + RECT 0.090 255.060 245.700 256.220 ; + RECT 0.090 249.500 249.670 255.060 ; + RECT 4.300 248.340 249.670 249.500 ; + RECT 0.090 247.820 249.670 248.340 ; + RECT 0.090 246.660 245.700 247.820 ; + RECT 0.090 240.540 249.670 246.660 ; + RECT 4.300 239.420 249.670 240.540 ; + RECT 4.300 239.380 245.700 239.420 ; + RECT 0.090 238.260 245.700 239.380 ; + RECT 0.090 231.580 249.670 238.260 ; + RECT 4.300 231.020 249.670 231.580 ; + RECT 4.300 230.420 245.700 231.020 ; + RECT 0.090 229.860 245.700 230.420 ; + RECT 0.090 222.620 249.670 229.860 ; + RECT 4.300 221.460 245.700 222.620 ; + RECT 0.090 214.220 249.670 221.460 ; + RECT 0.090 213.660 245.700 214.220 ; + RECT 4.300 213.060 245.700 213.660 ; + RECT 4.300 212.500 249.670 213.060 ; + RECT 0.090 205.820 249.670 212.500 ; + RECT 0.090 204.700 245.700 205.820 ; + RECT 4.300 204.660 245.700 204.700 ; + RECT 4.300 203.540 249.670 204.660 ; + RECT 0.090 197.420 249.670 203.540 ; + RECT 0.090 196.260 245.700 197.420 ; + RECT 0.090 195.740 249.670 196.260 ; + RECT 4.300 194.580 249.670 195.740 ; + RECT 0.090 189.020 249.670 194.580 ; + RECT 0.090 187.860 245.700 189.020 ; + RECT 0.090 186.780 249.670 187.860 ; + RECT 4.300 185.620 249.670 186.780 ; + RECT 0.090 180.620 249.670 185.620 ; + RECT 0.090 179.460 245.700 180.620 ; + RECT 0.090 177.820 249.670 179.460 ; + RECT 4.300 176.660 249.670 177.820 ; + RECT 0.090 172.220 249.670 176.660 ; + RECT 0.090 171.060 245.700 172.220 ; + RECT 0.090 168.860 249.670 171.060 ; + RECT 4.300 167.700 249.670 168.860 ; + RECT 0.090 163.820 249.670 167.700 ; + RECT 0.090 162.660 245.700 163.820 ; + RECT 0.090 159.900 249.670 162.660 ; + RECT 4.300 158.740 249.670 159.900 ; + RECT 0.090 155.420 249.670 158.740 ; + RECT 0.090 154.260 245.700 155.420 ; + RECT 0.090 150.940 249.670 154.260 ; + RECT 4.300 149.780 249.670 150.940 ; + RECT 0.090 147.020 249.670 149.780 ; + RECT 0.090 145.860 245.700 147.020 ; + RECT 0.090 141.980 249.670 145.860 ; + RECT 4.300 140.820 249.670 141.980 ; + RECT 0.090 138.620 249.670 140.820 ; + RECT 0.090 137.460 245.700 138.620 ; + RECT 0.090 133.020 249.670 137.460 ; + RECT 4.300 131.860 249.670 133.020 ; + RECT 0.090 130.220 249.670 131.860 ; + RECT 0.090 129.060 245.700 130.220 ; + RECT 0.090 124.060 249.670 129.060 ; + RECT 4.300 122.900 249.670 124.060 ; + RECT 0.090 121.820 249.670 122.900 ; + RECT 0.090 120.660 245.700 121.820 ; + RECT 0.090 115.100 249.670 120.660 ; + RECT 4.300 113.940 249.670 115.100 ; + RECT 0.090 113.420 249.670 113.940 ; + RECT 0.090 112.260 245.700 113.420 ; + RECT 0.090 106.140 249.670 112.260 ; + RECT 4.300 105.020 249.670 106.140 ; + RECT 4.300 104.980 245.700 105.020 ; + RECT 0.090 103.860 245.700 104.980 ; + RECT 0.090 97.180 249.670 103.860 ; + RECT 4.300 96.620 249.670 97.180 ; + RECT 4.300 96.020 245.700 96.620 ; + RECT 0.090 95.460 245.700 96.020 ; + RECT 0.090 88.220 249.670 95.460 ; + RECT 4.300 87.060 245.700 88.220 ; + RECT 0.090 79.820 249.670 87.060 ; + RECT 0.090 79.260 245.700 79.820 ; + RECT 4.300 78.660 245.700 79.260 ; + RECT 4.300 78.100 249.670 78.660 ; + RECT 0.090 71.420 249.670 78.100 ; + RECT 0.090 70.300 245.700 71.420 ; + RECT 4.300 70.260 245.700 70.300 ; + RECT 4.300 69.140 249.670 70.260 ; + RECT 0.090 63.020 249.670 69.140 ; + RECT 0.090 61.860 245.700 63.020 ; + RECT 0.090 61.340 249.670 61.860 ; + RECT 4.300 60.180 249.670 61.340 ; + RECT 0.090 54.620 249.670 60.180 ; + RECT 0.090 53.460 245.700 54.620 ; + RECT 0.090 52.380 249.670 53.460 ; + RECT 4.300 51.220 249.670 52.380 ; + RECT 0.090 46.220 249.670 51.220 ; + RECT 0.090 45.060 245.700 46.220 ; + RECT 0.090 43.420 249.670 45.060 ; + RECT 4.300 42.260 249.670 43.420 ; + RECT 0.090 37.820 249.670 42.260 ; + RECT 0.090 36.660 245.700 37.820 ; + RECT 0.090 34.460 249.670 36.660 ; + RECT 4.300 33.300 249.670 34.460 ; + RECT 0.090 29.420 249.670 33.300 ; + RECT 0.090 28.260 245.700 29.420 ; + RECT 0.090 25.500 249.670 28.260 ; + RECT 4.300 24.340 249.670 25.500 ; + RECT 0.090 21.020 249.670 24.340 ; + RECT 0.090 19.860 245.700 21.020 ; + RECT 0.090 16.540 249.670 19.860 ; + RECT 4.300 15.380 249.670 16.540 ; + RECT 0.090 12.620 249.670 15.380 ; + RECT 0.090 11.460 245.700 12.620 ; + RECT 0.090 7.580 249.670 11.460 ; + RECT 4.300 6.420 249.670 7.580 ; + RECT 0.090 0.140 249.670 6.420 ; LAYER Metal4 ; - RECT 5.180 8.490 16.340 288.310 ; - RECT 18.540 8.490 41.340 288.310 ; - RECT 43.540 8.490 66.340 288.310 ; - RECT 68.540 8.490 91.340 288.310 ; - RECT 93.540 8.490 116.340 288.310 ; - RECT 118.540 8.490 141.340 288.310 ; - RECT 143.540 8.490 166.340 288.310 ; - RECT 168.540 8.490 191.340 288.310 ; - RECT 193.540 8.490 216.340 288.310 ; - RECT 218.540 8.490 241.340 288.310 ; - RECT 243.540 8.490 266.340 288.310 ; - RECT 268.540 8.490 284.340 288.310 ; + RECT 4.060 302.440 249.620 305.670 ; + RECT 4.060 7.240 16.340 302.440 ; + RECT 18.540 7.240 41.340 302.440 ; + RECT 43.540 7.240 66.340 302.440 ; + RECT 68.540 7.240 91.340 302.440 ; + RECT 93.540 7.240 116.340 302.440 ; + RECT 118.540 7.240 141.340 302.440 ; + RECT 143.540 7.240 166.340 302.440 ; + RECT 168.540 7.240 191.340 302.440 ; + RECT 193.540 7.240 216.340 302.440 ; + RECT 218.540 7.240 241.340 302.440 ; + RECT 243.540 7.240 249.620 302.440 ; + RECT 4.060 6.250 249.620 7.240 ; END END fpga_struct_block END LIBRARY
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef index 1d15bec..43bb533 100644 --- a/lef/user_project_wrapper.lef +++ b/lef/user_project_wrapper.lef
@@ -2512,423 +2512,299 @@ END PORT LAYER Metal4 ; - RECT 105.770 -8.220 108.870 103.210 ; + RECT 125.770 -8.220 128.870 80.970 ; END PORT LAYER Metal4 ; - RECT 105.770 393.590 108.870 517.210 ; + RECT 125.770 390.950 128.870 500.970 ; END PORT LAYER Metal4 ; - RECT 105.770 807.590 108.870 931.210 ; + RECT 125.770 810.950 128.870 920.970 ; END PORT LAYER Metal4 ; - RECT 105.770 1221.590 108.870 1345.210 ; + RECT 125.770 1230.950 128.870 1340.970 ; END PORT LAYER Metal4 ; - RECT 105.770 1635.590 108.870 1759.210 ; + RECT 125.770 1650.950 128.870 1760.970 ; END PORT LAYER Metal4 ; - RECT 105.770 2049.590 108.870 2173.210 ; + RECT 125.770 2070.950 128.870 2180.970 ; END PORT LAYER Metal4 ; - RECT 105.770 2463.590 108.870 2587.210 ; + RECT 125.770 2490.950 128.870 2600.970 ; END PORT LAYER Metal4 ; - RECT 105.770 2877.590 108.870 2991.340 ; + RECT 125.770 2910.950 128.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 195.770 -8.220 198.870 103.210 ; + RECT 235.770 -8.220 238.870 80.970 ; END PORT LAYER Metal4 ; - RECT 195.770 393.590 198.870 517.210 ; + RECT 235.770 390.950 238.870 500.970 ; END PORT LAYER Metal4 ; - RECT 195.770 807.590 198.870 931.210 ; + RECT 235.770 810.950 238.870 920.970 ; END PORT LAYER Metal4 ; - RECT 195.770 1221.590 198.870 1345.210 ; + RECT 235.770 1230.950 238.870 1340.970 ; END PORT LAYER Metal4 ; - RECT 195.770 1635.590 198.870 1759.210 ; + RECT 235.770 1650.950 238.870 1760.970 ; END PORT LAYER Metal4 ; - RECT 195.770 2049.590 198.870 2173.210 ; + RECT 235.770 2070.950 238.870 2180.970 ; END PORT LAYER Metal4 ; - RECT 195.770 2463.590 198.870 2587.210 ; + RECT 235.770 2490.950 238.870 2600.970 ; END PORT LAYER Metal4 ; - RECT 195.770 2877.590 198.870 2991.340 ; + RECT 235.770 2910.950 238.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 285.770 -8.220 288.870 103.210 ; + RECT 345.770 -8.220 348.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 285.770 393.590 288.870 517.210 ; + RECT 455.770 -8.220 458.870 80.970 ; END PORT LAYER Metal4 ; - RECT 285.770 807.590 288.870 931.210 ; + RECT 455.770 390.950 458.870 500.970 ; END PORT LAYER Metal4 ; - RECT 285.770 1221.590 288.870 1345.210 ; + RECT 455.770 810.950 458.870 920.970 ; END PORT LAYER Metal4 ; - RECT 285.770 1635.590 288.870 1759.210 ; + RECT 455.770 1230.950 458.870 1340.970 ; END PORT LAYER Metal4 ; - RECT 285.770 2049.590 288.870 2173.210 ; + RECT 455.770 1650.950 458.870 1760.970 ; END PORT LAYER Metal4 ; - RECT 285.770 2463.590 288.870 2587.210 ; + RECT 455.770 2070.950 458.870 2180.970 ; END PORT LAYER Metal4 ; - RECT 285.770 2877.590 288.870 2991.340 ; + RECT 455.770 2490.950 458.870 2600.970 ; END PORT LAYER Metal4 ; - RECT 375.770 -8.220 378.870 103.210 ; + RECT 455.770 2910.950 458.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 375.770 393.590 378.870 517.210 ; + RECT 565.770 -8.220 568.870 80.970 ; END PORT LAYER Metal4 ; - RECT 375.770 807.590 378.870 931.210 ; + RECT 565.770 390.950 568.870 500.970 ; END PORT LAYER Metal4 ; - RECT 375.770 1221.590 378.870 1345.210 ; + RECT 565.770 810.950 568.870 920.970 ; END PORT LAYER Metal4 ; - RECT 375.770 1635.590 378.870 1759.210 ; + RECT 565.770 1230.950 568.870 1340.970 ; END PORT LAYER Metal4 ; - RECT 375.770 2049.590 378.870 2173.210 ; + RECT 565.770 1650.950 568.870 1760.970 ; END PORT LAYER Metal4 ; - RECT 375.770 2463.590 378.870 2587.210 ; + RECT 565.770 2070.950 568.870 2180.970 ; END PORT LAYER Metal4 ; - RECT 375.770 2877.590 378.870 2991.340 ; + RECT 565.770 2490.950 568.870 2600.970 ; END PORT LAYER Metal4 ; - RECT 465.770 -8.220 468.870 103.210 ; + RECT 565.770 2910.950 568.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 465.770 393.590 468.870 517.210 ; + RECT 675.770 -8.220 678.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 465.770 807.590 468.870 931.210 ; + RECT 785.770 -8.220 788.870 574.430 ; END PORT LAYER Metal4 ; - RECT 465.770 1221.590 468.870 1345.210 ; + RECT 785.770 2864.815 788.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 465.770 1635.590 468.870 1759.210 ; + RECT 895.770 -8.220 898.870 574.430 ; END PORT LAYER Metal4 ; - RECT 465.770 2049.590 468.870 2173.210 ; + RECT 895.770 2864.815 898.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 465.770 2463.590 468.870 2587.210 ; + RECT 1005.770 -8.220 1008.870 574.430 ; END PORT LAYER Metal4 ; - RECT 465.770 2877.590 468.870 2991.340 ; + RECT 1005.770 2864.815 1008.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 555.770 -8.220 558.870 103.210 ; + RECT 1115.770 -8.220 1118.870 574.430 ; END PORT LAYER Metal4 ; - RECT 555.770 393.590 558.870 517.210 ; + RECT 1115.770 2880.080 1118.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 555.770 807.590 558.870 931.210 ; + RECT 1225.770 -8.220 1228.870 574.430 ; END PORT LAYER Metal4 ; - RECT 555.770 1221.590 558.870 1345.210 ; + RECT 1225.770 2864.815 1228.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 555.770 1635.590 558.870 1759.210 ; + RECT 1335.770 -8.220 1338.870 571.800 ; END PORT LAYER Metal4 ; - RECT 555.770 2049.590 558.870 2173.210 ; + RECT 1335.770 2919.280 1338.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 555.770 2463.590 558.870 2587.210 ; + RECT 1445.770 -8.220 1448.870 574.430 ; END PORT LAYER Metal4 ; - RECT 555.770 2877.590 558.870 2991.340 ; + RECT 1445.770 2864.815 1448.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 645.770 -8.220 648.870 103.210 ; + RECT 1555.770 -8.220 1558.870 574.430 ; END PORT LAYER Metal4 ; - RECT 645.770 393.590 648.870 517.210 ; + RECT 1555.770 2880.080 1558.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 645.770 807.590 648.870 931.210 ; + RECT 1665.770 -8.220 1668.870 574.430 ; END PORT LAYER Metal4 ; - RECT 645.770 1221.590 648.870 1345.210 ; + RECT 1665.770 2864.815 1668.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 645.770 1635.590 648.870 1759.210 ; + RECT 1775.770 -8.220 1778.870 574.430 ; END PORT LAYER Metal4 ; - RECT 645.770 2049.590 648.870 2173.210 ; + RECT 1775.770 2864.815 1778.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 645.770 2463.590 648.870 2587.210 ; + RECT 1885.770 -8.220 1888.870 574.430 ; END PORT LAYER Metal4 ; - RECT 645.770 2877.590 648.870 2991.340 ; + RECT 1885.770 2864.815 1888.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 735.770 -8.220 738.870 2991.340 ; + RECT 1995.770 -8.220 1998.870 574.430 ; END PORT LAYER Metal4 ; - RECT 825.770 -8.220 828.870 332.630 ; + RECT 1995.770 2880.080 1998.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 825.770 2672.050 828.870 2991.340 ; + RECT 2105.770 -8.220 2108.870 574.430 ; END PORT LAYER Metal4 ; - RECT 915.770 -8.220 918.870 332.630 ; + RECT 2105.770 2864.815 2108.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 915.770 2672.050 918.870 2991.340 ; + RECT 2215.770 -8.220 2218.870 574.430 ; END PORT LAYER Metal4 ; - RECT 1005.770 -8.220 1008.870 332.630 ; + RECT 2215.770 2864.815 2218.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 1005.770 2672.050 1008.870 2991.340 ; + RECT 2325.770 -8.220 2328.870 574.430 ; END PORT LAYER Metal4 ; - RECT 1095.770 -8.220 1098.870 332.630 ; + RECT 2325.770 2864.815 2328.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 1095.770 2672.050 1098.870 2991.340 ; + RECT 2435.770 -8.220 2438.870 574.430 ; END PORT LAYER Metal4 ; - RECT 1185.770 -8.220 1188.870 332.630 ; + RECT 2435.770 2880.080 2438.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 1185.770 2674.680 1188.870 2991.340 ; + RECT 2545.770 -8.220 2548.870 574.430 ; END PORT LAYER Metal4 ; - RECT 1275.770 -8.220 1278.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1275.770 2672.050 1278.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1365.770 -8.220 1368.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1365.770 2674.680 1368.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1455.770 -8.220 1458.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1455.770 2672.050 1458.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1545.770 -8.220 1548.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1545.770 2672.050 1548.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1635.770 -8.220 1638.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1635.770 2672.050 1638.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1725.770 -8.220 1728.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1725.770 2672.050 1728.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1815.770 -8.220 1818.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1815.770 2672.050 1818.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1905.770 -8.220 1908.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1905.770 2672.050 1908.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1995.770 -8.220 1998.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1995.770 2672.050 1998.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2085.770 -8.220 2088.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2085.770 2672.050 2088.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2175.770 -8.220 2178.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2175.770 2672.050 2178.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2265.770 -8.220 2268.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2265.770 2672.050 2268.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2355.770 -8.220 2358.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2355.770 2672.050 2358.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2445.770 -8.220 2448.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2445.770 2672.050 2448.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2535.770 -8.220 2538.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2535.770 2672.050 2538.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2625.770 -8.220 2628.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2625.770 2672.050 2628.870 2991.340 ; + RECT 2545.770 2864.815 2548.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 2715.770 -8.220 2718.870 332.630 ; + RECT 2655.770 -8.220 2658.870 571.800 ; END PORT LAYER Metal4 ; - RECT 2715.770 2672.050 2718.870 2991.340 ; + RECT 2655.770 2919.280 2658.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 2805.770 -8.220 2808.870 332.630 ; + RECT 2765.770 -8.220 2768.870 574.430 ; END PORT LAYER Metal4 ; - RECT 2805.770 2672.050 2808.870 2991.340 ; + RECT 2765.770 2864.815 2768.870 2991.340 ; END PORT LAYER Metal4 ; - RECT 2895.770 -8.220 2898.870 332.630 ; + RECT 2875.770 -8.220 2878.870 599.240 ; END PORT LAYER Metal4 ; - RECT 2895.770 2674.680 2898.870 2991.340 ; + RECT 2875.770 2880.080 2878.870 2991.340 ; END PORT LAYER Metal5 ; @@ -2956,7 +2832,7 @@ END PORT LAYER Metal5 ; - RECT -9.580 557.130 2989.900 560.230 ; + RECT -9.580 557.130 736.240 560.230 ; END PORT LAYER Metal5 ; @@ -3063,36 +2939,12 @@ RECT -9.580 2897.130 2989.900 2900.230 ; END PORT - LAYER Metal4 ; - RECT 410.330 82.020 413.430 419.740 ; + LAYER Metal5 ; + RECT 2902.160 557.130 2989.900 560.230 ; END PORT LAYER Metal4 ; - RECT 410.330 497.540 413.430 827.465 ; - END - PORT - LAYER Metal4 ; - RECT 410.330 913.060 413.430 1242.940 ; - END - PORT - LAYER Metal4 ; - RECT 410.330 1328.580 413.430 1658.460 ; - END - PORT - LAYER Metal4 ; - RECT 410.330 1744.100 413.430 2073.980 ; - END - PORT - LAYER Metal4 ; - RECT 410.330 2159.620 413.430 2489.500 ; - END - PORT - LAYER Metal4 ; - RECT 410.330 2567.300 413.430 2897.180 ; - END - PORT - LAYER Metal4 ; - RECT 2958.890 321.140 2961.990 2701.180 ; + RECT 2934.250 544.580 2937.350 2948.140 ; END END vdd PIN vss @@ -3116,399 +2968,299 @@ END PORT LAYER Metal4 ; - RECT 60.770 -8.220 63.870 2991.340 ; + RECT 28.870 -8.220 31.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 150.770 -8.220 153.870 103.210 ; + RECT 138.870 -8.220 141.970 80.970 ; END PORT LAYER Metal4 ; - RECT 150.770 393.590 153.870 517.210 ; + RECT 138.870 390.950 141.970 500.970 ; END PORT LAYER Metal4 ; - RECT 150.770 807.590 153.870 931.210 ; + RECT 138.870 810.950 141.970 920.970 ; END PORT LAYER Metal4 ; - RECT 150.770 1221.590 153.870 1345.210 ; + RECT 138.870 1230.950 141.970 1340.970 ; END PORT LAYER Metal4 ; - RECT 150.770 1635.590 153.870 1759.210 ; + RECT 138.870 1650.950 141.970 1760.970 ; END PORT LAYER Metal4 ; - RECT 150.770 2049.590 153.870 2173.210 ; + RECT 138.870 2070.950 141.970 2180.970 ; END PORT LAYER Metal4 ; - RECT 150.770 2463.590 153.870 2587.210 ; + RECT 138.870 2490.950 141.970 2600.970 ; END PORT LAYER Metal4 ; - RECT 150.770 2877.590 153.870 2991.340 ; + RECT 138.870 2910.950 141.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 240.770 -8.220 243.870 102.260 ; + RECT 248.870 -8.220 251.970 80.970 ; END PORT LAYER Metal4 ; - RECT 240.770 395.660 243.870 516.260 ; + RECT 248.870 390.950 251.970 500.970 ; END PORT LAYER Metal4 ; - RECT 240.770 809.660 243.870 930.260 ; + RECT 248.870 810.950 251.970 920.970 ; END PORT LAYER Metal4 ; - RECT 240.770 1223.660 243.870 1344.260 ; + RECT 248.870 1230.950 251.970 1340.970 ; END PORT LAYER Metal4 ; - RECT 240.770 1637.660 243.870 1758.260 ; + RECT 248.870 1650.950 251.970 1760.970 ; END PORT LAYER Metal4 ; - RECT 240.770 2051.660 243.870 2172.260 ; + RECT 248.870 2070.950 251.970 2180.970 ; END PORT LAYER Metal4 ; - RECT 240.770 2465.660 243.870 2586.260 ; + RECT 248.870 2490.950 251.970 2600.970 ; END PORT LAYER Metal4 ; - RECT 240.770 2879.660 243.870 2991.340 ; + RECT 248.870 2910.950 251.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 330.770 -8.220 333.870 103.210 ; + RECT 358.870 -8.220 361.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 330.770 393.590 333.870 517.210 ; + RECT 468.870 -8.220 471.970 80.970 ; END PORT LAYER Metal4 ; - RECT 330.770 807.590 333.870 931.210 ; + RECT 468.870 390.950 471.970 500.970 ; END PORT LAYER Metal4 ; - RECT 330.770 1221.590 333.870 1345.210 ; + RECT 468.870 810.950 471.970 920.970 ; END PORT LAYER Metal4 ; - RECT 330.770 1635.590 333.870 1759.210 ; + RECT 468.870 1230.950 471.970 1340.970 ; END PORT LAYER Metal4 ; - RECT 330.770 2049.590 333.870 2173.210 ; + RECT 468.870 1650.950 471.970 1760.970 ; END PORT LAYER Metal4 ; - RECT 330.770 2463.590 333.870 2587.210 ; + RECT 468.870 2070.950 471.970 2180.970 ; END PORT LAYER Metal4 ; - RECT 330.770 2877.590 333.870 2991.340 ; + RECT 468.870 2490.950 471.970 2600.970 ; END PORT LAYER Metal4 ; - RECT 420.770 -8.220 423.870 2991.340 ; + RECT 468.870 2910.950 471.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 510.770 -8.220 513.870 103.210 ; + RECT 578.870 -8.220 581.970 80.970 ; END PORT LAYER Metal4 ; - RECT 510.770 393.590 513.870 517.210 ; + RECT 578.870 390.950 581.970 500.970 ; END PORT LAYER Metal4 ; - RECT 510.770 807.590 513.870 931.210 ; + RECT 578.870 810.950 581.970 920.970 ; END PORT LAYER Metal4 ; - RECT 510.770 1221.590 513.870 1345.210 ; + RECT 578.870 1230.950 581.970 1340.970 ; END PORT LAYER Metal4 ; - RECT 510.770 1635.590 513.870 1759.210 ; + RECT 578.870 1650.950 581.970 1760.970 ; END PORT LAYER Metal4 ; - RECT 510.770 2049.590 513.870 2173.210 ; + RECT 578.870 2070.950 581.970 2180.970 ; END PORT LAYER Metal4 ; - RECT 510.770 2463.590 513.870 2587.210 ; + RECT 578.870 2490.950 581.970 2600.970 ; END PORT LAYER Metal4 ; - RECT 510.770 2877.590 513.870 2991.340 ; + RECT 578.870 2910.950 581.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 600.770 -8.220 603.870 102.260 ; + RECT 688.870 -8.220 691.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 600.770 395.660 603.870 516.260 ; + RECT 798.870 -8.220 801.970 574.430 ; END PORT LAYER Metal4 ; - RECT 600.770 809.660 603.870 930.260 ; + RECT 798.870 2864.815 801.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 600.770 1223.660 603.870 1344.260 ; + RECT 908.870 -8.220 911.970 574.430 ; END PORT LAYER Metal4 ; - RECT 600.770 1637.660 603.870 1758.260 ; + RECT 908.870 2864.815 911.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 600.770 2051.660 603.870 2172.260 ; + RECT 1018.870 -8.220 1021.970 574.430 ; END PORT LAYER Metal4 ; - RECT 600.770 2465.660 603.870 2586.260 ; + RECT 1018.870 2880.080 1021.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 600.770 2879.660 603.870 2991.340 ; + RECT 1128.870 -8.220 1131.970 574.430 ; END PORT LAYER Metal4 ; - RECT 690.770 -8.220 693.870 103.210 ; + RECT 1128.870 2864.815 1131.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 690.770 393.590 693.870 517.210 ; + RECT 1238.870 -8.220 1241.970 574.430 ; END PORT LAYER Metal4 ; - RECT 690.770 807.590 693.870 931.210 ; + RECT 1238.870 2864.815 1241.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 690.770 1221.590 693.870 1345.210 ; + RECT 1348.870 -8.220 1351.970 574.430 ; END PORT LAYER Metal4 ; - RECT 690.770 1635.590 693.870 1759.210 ; + RECT 1348.870 2864.815 1351.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 690.770 2049.590 693.870 2173.210 ; + RECT 1458.870 -8.220 1461.970 574.430 ; END PORT LAYER Metal4 ; - RECT 690.770 2463.590 693.870 2587.210 ; + RECT 1458.870 2880.080 1461.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 690.770 2877.590 693.870 2991.340 ; + RECT 1568.870 -8.220 1571.970 574.430 ; END PORT LAYER Metal4 ; - RECT 780.770 -8.220 783.870 332.630 ; + RECT 1568.870 2864.815 1571.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 780.770 2672.050 783.870 2991.340 ; + RECT 1678.870 -8.220 1681.970 574.430 ; END PORT LAYER Metal4 ; - RECT 870.770 -8.220 873.870 332.630 ; + RECT 1678.870 2864.815 1681.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 870.770 2672.050 873.870 2991.340 ; + RECT 1788.870 -8.220 1791.970 574.430 ; END PORT LAYER Metal4 ; - RECT 960.770 -8.220 963.870 332.630 ; + RECT 1788.870 2864.815 1791.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 960.770 2672.050 963.870 2991.340 ; + RECT 1898.870 -8.220 1901.970 571.800 ; END PORT LAYER Metal4 ; - RECT 1050.770 -8.220 1053.870 332.630 ; + RECT 1898.870 2919.280 1901.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 1050.770 2672.050 1053.870 2991.340 ; + RECT 2008.870 -8.220 2011.970 574.430 ; END PORT LAYER Metal4 ; - RECT 1140.770 -8.220 1143.870 332.630 ; + RECT 2008.870 2864.815 2011.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 1140.770 2672.050 1143.870 2991.340 ; + RECT 2118.870 -8.220 2121.970 574.430 ; END PORT LAYER Metal4 ; - RECT 1230.770 -8.220 1233.870 332.630 ; + RECT 2118.870 2864.815 2121.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 1230.770 2672.050 1233.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1320.770 -8.220 1323.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1320.770 2672.050 1323.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1410.770 -8.220 1413.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1410.770 2672.050 1413.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1500.770 -8.220 1503.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1500.770 2672.050 1503.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1590.770 -8.220 1593.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1590.770 2672.050 1593.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1680.770 -8.220 1683.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1680.770 2672.050 1683.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1770.770 -8.220 1773.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1770.770 2672.050 1773.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1860.770 -8.220 1863.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1860.770 2672.050 1863.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 1950.770 -8.220 1953.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 1950.770 2672.050 1953.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2040.770 -8.220 2043.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2040.770 2672.050 2043.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2130.770 -8.220 2133.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2130.770 2672.050 2133.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2220.770 -8.220 2223.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2220.770 2672.050 2223.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2310.770 -8.220 2313.870 332.630 ; - END - PORT - LAYER Metal4 ; - RECT 2310.770 2672.050 2313.870 2991.340 ; - END - PORT - LAYER Metal4 ; - RECT 2400.770 -8.220 2403.870 332.630 ; + RECT 2228.870 -8.220 2231.970 574.430 ; END PORT LAYER Metal4 ; - RECT 2400.770 2672.050 2403.870 2991.340 ; + RECT 2228.870 2864.815 2231.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 2490.770 -8.220 2493.870 332.630 ; + RECT 2338.870 -8.220 2341.970 574.430 ; END PORT LAYER Metal4 ; - RECT 2490.770 2672.050 2493.870 2991.340 ; + RECT 2338.870 2880.080 2341.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 2580.770 -8.220 2583.870 332.630 ; + RECT 2448.870 -8.220 2451.970 574.430 ; END PORT LAYER Metal4 ; - RECT 2580.770 2672.050 2583.870 2991.340 ; + RECT 2448.870 2864.815 2451.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 2670.770 -8.220 2673.870 332.630 ; + RECT 2558.870 -8.220 2561.970 574.430 ; END PORT LAYER Metal4 ; - RECT 2670.770 2672.050 2673.870 2991.340 ; + RECT 2558.870 2864.815 2561.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 2760.770 -8.220 2763.870 332.630 ; + RECT 2668.870 -8.220 2671.970 571.800 ; END PORT LAYER Metal4 ; - RECT 2760.770 2672.050 2763.870 2991.340 ; + RECT 2668.870 2919.280 2671.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 2850.770 -8.220 2853.870 332.630 ; + RECT 2778.870 -8.220 2781.970 574.430 ; END PORT LAYER Metal4 ; - RECT 2850.770 2672.050 2853.870 2991.340 ; + RECT 2778.870 2880.080 2781.970 2991.340 ; END PORT LAYER Metal4 ; - RECT 2940.770 -8.220 2943.870 2991.340 ; + RECT 2888.870 -8.220 2891.970 2991.340 ; END PORT LAYER Metal5 ; @@ -3524,7 +3276,7 @@ END PORT LAYER Metal5 ; - RECT -9.580 332.130 775.340 335.230 ; + RECT -9.580 332.130 2989.900 335.230 ; END PORT LAYER Metal5 ; @@ -3643,40 +3395,8 @@ RECT -9.580 2942.130 2989.900 2945.230 ; END PORT - LAYER Metal5 ; - RECT 2941.260 332.130 2989.900 335.230 ; - END - PORT LAYER Metal4 ; - RECT 745.770 501.460 748.870 831.340 ; - END - PORT - LAYER Metal4 ; - RECT 745.770 321.140 748.870 415.820 ; - END - PORT - LAYER Metal4 ; - RECT 745.770 1324.660 748.870 1654.540 ; - END - PORT - LAYER Metal4 ; - RECT 745.770 916.980 748.870 1246.860 ; - END - PORT - LAYER Metal4 ; - RECT 745.770 2155.700 748.870 2485.580 ; - END - PORT - LAYER Metal4 ; - RECT 745.770 1740.180 748.870 2070.060 ; - END - PORT - LAYER Metal4 ; - RECT 745.770 2571.220 748.870 2697.260 ; - END - PORT - LAYER Metal4 ; - RECT 2962.810 321.140 2965.910 2701.180 ; + RECT 2947.690 544.580 2950.790 2948.140 ; END END vss PIN wb_clk_i @@ -4529,868 +4249,782 @@ END wbs_we_i OBS LAYER Metal1 ; - RECT 12.320 15.380 2968.000 2968.410 ; + RECT 8.490 14.710 2968.000 2968.410 ; LAYER Metal2 ; - RECT 14.700 2977.500 54.860 2978.500 ; - RECT 56.580 2977.500 165.180 2978.500 ; - RECT 166.900 2977.500 275.500 2978.500 ; - RECT 277.220 2977.500 385.820 2978.500 ; - RECT 387.540 2977.500 496.140 2978.500 ; - RECT 497.860 2977.500 606.460 2978.500 ; - RECT 608.180 2977.500 716.780 2978.500 ; - RECT 718.500 2977.500 827.100 2978.500 ; - RECT 828.820 2977.500 937.420 2978.500 ; - RECT 939.140 2977.500 1047.740 2978.500 ; - RECT 1049.460 2977.500 1158.060 2978.500 ; - RECT 1159.780 2977.500 1268.380 2978.500 ; - RECT 1270.100 2977.500 1378.700 2978.500 ; - RECT 1380.420 2977.500 1489.020 2978.500 ; - RECT 1490.740 2977.500 1599.340 2978.500 ; - RECT 1601.060 2977.500 1709.660 2978.500 ; - RECT 1711.380 2977.500 1819.980 2978.500 ; - RECT 1821.700 2977.500 1930.300 2978.500 ; - RECT 1932.020 2977.500 2040.620 2978.500 ; - RECT 2042.340 2977.500 2150.940 2978.500 ; - RECT 2152.660 2977.500 2261.260 2978.500 ; - RECT 2262.980 2977.500 2371.580 2978.500 ; - RECT 2373.300 2977.500 2481.900 2978.500 ; - RECT 2483.620 2977.500 2592.220 2978.500 ; - RECT 2593.940 2977.500 2702.540 2978.500 ; - RECT 2704.260 2977.500 2812.860 2978.500 ; - RECT 2814.580 2977.500 2923.180 2978.500 ; - RECT 2924.900 2977.500 2971.220 2978.500 ; - RECT 14.700 2.700 2971.220 2977.500 ; - RECT 14.700 1.820 56.540 2.700 ; - RECT 58.260 1.820 66.060 2.700 ; - RECT 67.780 1.820 75.580 2.700 ; - RECT 77.300 1.820 85.100 2.700 ; - RECT 86.820 1.820 94.620 2.700 ; - RECT 96.340 1.820 104.140 2.700 ; - RECT 105.860 1.820 113.660 2.700 ; - RECT 115.380 1.820 123.180 2.700 ; - RECT 124.900 1.820 132.700 2.700 ; - RECT 134.420 1.820 142.220 2.700 ; - RECT 143.940 1.820 151.740 2.700 ; - RECT 153.460 1.820 161.260 2.700 ; - RECT 162.980 1.820 170.780 2.700 ; - RECT 172.500 1.820 180.300 2.700 ; - RECT 182.020 1.820 189.820 2.700 ; - RECT 191.540 1.820 199.340 2.700 ; - RECT 201.060 1.820 208.860 2.700 ; - RECT 210.580 1.820 218.380 2.700 ; - RECT 220.100 1.820 227.900 2.700 ; - RECT 229.620 1.820 237.420 2.700 ; - RECT 239.140 1.820 246.940 2.700 ; - RECT 248.660 1.820 256.460 2.700 ; - RECT 258.180 1.820 265.980 2.700 ; - RECT 267.700 1.820 275.500 2.700 ; - RECT 277.220 1.820 285.020 2.700 ; - RECT 286.740 1.820 294.540 2.700 ; - RECT 296.260 1.820 304.060 2.700 ; - RECT 305.780 1.820 313.580 2.700 ; - RECT 315.300 1.820 323.100 2.700 ; - RECT 324.820 1.820 332.620 2.700 ; - RECT 334.340 1.820 342.140 2.700 ; - RECT 343.860 1.820 351.660 2.700 ; - RECT 353.380 1.820 361.180 2.700 ; - RECT 362.900 1.820 370.700 2.700 ; - RECT 372.420 1.820 380.220 2.700 ; - RECT 381.940 1.820 389.740 2.700 ; - RECT 391.460 1.820 399.260 2.700 ; - RECT 400.980 1.820 408.780 2.700 ; - RECT 410.500 1.820 418.300 2.700 ; - RECT 420.020 1.820 427.820 2.700 ; - RECT 429.540 1.820 437.340 2.700 ; - RECT 439.060 1.820 446.860 2.700 ; - RECT 448.580 1.820 456.380 2.700 ; - RECT 458.100 1.820 465.900 2.700 ; - RECT 467.620 1.820 475.420 2.700 ; - RECT 477.140 1.820 484.940 2.700 ; - RECT 486.660 1.820 494.460 2.700 ; - RECT 496.180 1.820 503.980 2.700 ; - RECT 505.700 1.820 513.500 2.700 ; - RECT 515.220 1.820 523.020 2.700 ; - RECT 524.740 1.820 532.540 2.700 ; - RECT 534.260 1.820 542.060 2.700 ; - RECT 543.780 1.820 551.580 2.700 ; - RECT 553.300 1.820 561.100 2.700 ; - RECT 562.820 1.820 570.620 2.700 ; - RECT 572.340 1.820 580.140 2.700 ; - RECT 581.860 1.820 589.660 2.700 ; - RECT 591.380 1.820 599.180 2.700 ; - RECT 600.900 1.820 608.700 2.700 ; - RECT 610.420 1.820 618.220 2.700 ; - RECT 619.940 1.820 627.740 2.700 ; - RECT 629.460 1.820 637.260 2.700 ; - RECT 638.980 1.820 646.780 2.700 ; - RECT 648.500 1.820 656.300 2.700 ; - RECT 658.020 1.820 665.820 2.700 ; - RECT 667.540 1.820 675.340 2.700 ; - RECT 677.060 1.820 684.860 2.700 ; - RECT 686.580 1.820 694.380 2.700 ; - RECT 696.100 1.820 703.900 2.700 ; - RECT 705.620 1.820 713.420 2.700 ; - RECT 715.140 1.820 722.940 2.700 ; - RECT 724.660 1.820 732.460 2.700 ; - RECT 734.180 1.820 741.980 2.700 ; - RECT 743.700 1.820 751.500 2.700 ; - RECT 753.220 1.820 761.020 2.700 ; - RECT 762.740 1.820 770.540 2.700 ; - RECT 772.260 1.820 780.060 2.700 ; - RECT 781.780 1.820 789.580 2.700 ; - RECT 791.300 1.820 799.100 2.700 ; - RECT 800.820 1.820 808.620 2.700 ; - RECT 810.340 1.820 818.140 2.700 ; - RECT 819.860 1.820 827.660 2.700 ; - RECT 829.380 1.820 837.180 2.700 ; - RECT 838.900 1.820 846.700 2.700 ; - RECT 848.420 1.820 856.220 2.700 ; - RECT 857.940 1.820 865.740 2.700 ; - RECT 867.460 1.820 875.260 2.700 ; - RECT 876.980 1.820 884.780 2.700 ; - RECT 886.500 1.820 894.300 2.700 ; - RECT 896.020 1.820 903.820 2.700 ; - RECT 905.540 1.820 913.340 2.700 ; - RECT 915.060 1.820 922.860 2.700 ; - RECT 924.580 1.820 932.380 2.700 ; - RECT 934.100 1.820 941.900 2.700 ; - RECT 943.620 1.820 951.420 2.700 ; - RECT 953.140 1.820 960.940 2.700 ; - RECT 962.660 1.820 970.460 2.700 ; - RECT 972.180 1.820 979.980 2.700 ; - RECT 981.700 1.820 989.500 2.700 ; - RECT 991.220 1.820 999.020 2.700 ; - RECT 1000.740 1.820 1008.540 2.700 ; - RECT 1010.260 1.820 1018.060 2.700 ; - RECT 1019.780 1.820 1027.580 2.700 ; - RECT 1029.300 1.820 1037.100 2.700 ; - RECT 1038.820 1.820 1046.620 2.700 ; - RECT 1048.340 1.820 1056.140 2.700 ; - RECT 1057.860 1.820 1065.660 2.700 ; - RECT 1067.380 1.820 1075.180 2.700 ; - RECT 1076.900 1.820 1084.700 2.700 ; - RECT 1086.420 1.820 1094.220 2.700 ; - RECT 1095.940 1.820 1103.740 2.700 ; - RECT 1105.460 1.820 1113.260 2.700 ; - RECT 1114.980 1.820 1122.780 2.700 ; - RECT 1124.500 1.820 1132.300 2.700 ; - RECT 1134.020 1.820 1141.820 2.700 ; - RECT 1143.540 1.820 1151.340 2.700 ; - RECT 1153.060 1.820 1160.860 2.700 ; - RECT 1162.580 1.820 1170.380 2.700 ; - RECT 1172.100 1.820 1179.900 2.700 ; - RECT 1181.620 1.820 1189.420 2.700 ; - RECT 1191.140 1.820 1198.940 2.700 ; - RECT 1200.660 1.820 1208.460 2.700 ; - RECT 1210.180 1.820 1217.980 2.700 ; - RECT 1219.700 1.820 1227.500 2.700 ; - RECT 1229.220 1.820 1237.020 2.700 ; - RECT 1238.740 1.820 1246.540 2.700 ; - RECT 1248.260 1.820 1256.060 2.700 ; - RECT 1257.780 1.820 1265.580 2.700 ; - RECT 1267.300 1.820 1275.100 2.700 ; - RECT 1276.820 1.820 1284.620 2.700 ; - RECT 1286.340 1.820 1294.140 2.700 ; - RECT 1295.860 1.820 1303.660 2.700 ; - RECT 1305.380 1.820 1313.180 2.700 ; - RECT 1314.900 1.820 1322.700 2.700 ; - RECT 1324.420 1.820 1332.220 2.700 ; - RECT 1333.940 1.820 1341.740 2.700 ; - RECT 1343.460 1.820 1351.260 2.700 ; - RECT 1352.980 1.820 1360.780 2.700 ; - RECT 1362.500 1.820 1370.300 2.700 ; - RECT 1372.020 1.820 1379.820 2.700 ; - RECT 1381.540 1.820 1389.340 2.700 ; - RECT 1391.060 1.820 1398.860 2.700 ; - RECT 1400.580 1.820 1408.380 2.700 ; - RECT 1410.100 1.820 1417.900 2.700 ; - RECT 1419.620 1.820 1427.420 2.700 ; - RECT 1429.140 1.820 1436.940 2.700 ; - RECT 1438.660 1.820 1446.460 2.700 ; - RECT 1448.180 1.820 1455.980 2.700 ; - RECT 1457.700 1.820 1465.500 2.700 ; - RECT 1467.220 1.820 1475.020 2.700 ; - RECT 1476.740 1.820 1484.540 2.700 ; - RECT 1486.260 1.820 1494.060 2.700 ; - RECT 1495.780 1.820 1503.580 2.700 ; - RECT 1505.300 1.820 1513.100 2.700 ; - RECT 1514.820 1.820 1522.620 2.700 ; - RECT 1524.340 1.820 1532.140 2.700 ; - RECT 1533.860 1.820 1541.660 2.700 ; - RECT 1543.380 1.820 1551.180 2.700 ; - RECT 1552.900 1.820 1560.700 2.700 ; - RECT 1562.420 1.820 1570.220 2.700 ; - RECT 1571.940 1.820 1579.740 2.700 ; - RECT 1581.460 1.820 1589.260 2.700 ; - RECT 1590.980 1.820 1598.780 2.700 ; - RECT 1600.500 1.820 1608.300 2.700 ; - RECT 1610.020 1.820 1617.820 2.700 ; - RECT 1619.540 1.820 1627.340 2.700 ; - RECT 1629.060 1.820 1636.860 2.700 ; - RECT 1638.580 1.820 1646.380 2.700 ; - RECT 1648.100 1.820 1655.900 2.700 ; - RECT 1657.620 1.820 1665.420 2.700 ; - RECT 1667.140 1.820 1674.940 2.700 ; - RECT 1676.660 1.820 1684.460 2.700 ; - RECT 1686.180 1.820 1693.980 2.700 ; - RECT 1695.700 1.820 1703.500 2.700 ; - RECT 1705.220 1.820 1713.020 2.700 ; - RECT 1714.740 1.820 1722.540 2.700 ; - RECT 1724.260 1.820 1732.060 2.700 ; - RECT 1733.780 1.820 1741.580 2.700 ; - RECT 1743.300 1.820 1751.100 2.700 ; - RECT 1752.820 1.820 1760.620 2.700 ; - RECT 1762.340 1.820 1770.140 2.700 ; - RECT 1771.860 1.820 1779.660 2.700 ; - RECT 1781.380 1.820 1789.180 2.700 ; - RECT 1790.900 1.820 1798.700 2.700 ; - RECT 1800.420 1.820 1808.220 2.700 ; - RECT 1809.940 1.820 1817.740 2.700 ; - RECT 1819.460 1.820 1827.260 2.700 ; - RECT 1828.980 1.820 1836.780 2.700 ; - RECT 1838.500 1.820 1846.300 2.700 ; - RECT 1848.020 1.820 1855.820 2.700 ; - RECT 1857.540 1.820 1865.340 2.700 ; - RECT 1867.060 1.820 1874.860 2.700 ; - RECT 1876.580 1.820 1884.380 2.700 ; - RECT 1886.100 1.820 1893.900 2.700 ; - RECT 1895.620 1.820 1903.420 2.700 ; - RECT 1905.140 1.820 1912.940 2.700 ; - RECT 1914.660 1.820 1922.460 2.700 ; - RECT 1924.180 1.820 1931.980 2.700 ; - RECT 1933.700 1.820 1941.500 2.700 ; - RECT 1943.220 1.820 1951.020 2.700 ; - RECT 1952.740 1.820 1960.540 2.700 ; - RECT 1962.260 1.820 1970.060 2.700 ; - RECT 1971.780 1.820 1979.580 2.700 ; - RECT 1981.300 1.820 1989.100 2.700 ; - RECT 1990.820 1.820 1998.620 2.700 ; - RECT 2000.340 1.820 2008.140 2.700 ; - RECT 2009.860 1.820 2017.660 2.700 ; - RECT 2019.380 1.820 2027.180 2.700 ; - RECT 2028.900 1.820 2036.700 2.700 ; - RECT 2038.420 1.820 2046.220 2.700 ; - RECT 2047.940 1.820 2055.740 2.700 ; - RECT 2057.460 1.820 2065.260 2.700 ; - RECT 2066.980 1.820 2074.780 2.700 ; - RECT 2076.500 1.820 2084.300 2.700 ; - RECT 2086.020 1.820 2093.820 2.700 ; - RECT 2095.540 1.820 2103.340 2.700 ; - RECT 2105.060 1.820 2112.860 2.700 ; - RECT 2114.580 1.820 2122.380 2.700 ; - RECT 2124.100 1.820 2131.900 2.700 ; - RECT 2133.620 1.820 2141.420 2.700 ; - RECT 2143.140 1.820 2150.940 2.700 ; - RECT 2152.660 1.820 2160.460 2.700 ; - RECT 2162.180 1.820 2169.980 2.700 ; - RECT 2171.700 1.820 2179.500 2.700 ; - RECT 2181.220 1.820 2189.020 2.700 ; - RECT 2190.740 1.820 2198.540 2.700 ; - RECT 2200.260 1.820 2208.060 2.700 ; - RECT 2209.780 1.820 2217.580 2.700 ; - RECT 2219.300 1.820 2227.100 2.700 ; - RECT 2228.820 1.820 2236.620 2.700 ; - RECT 2238.340 1.820 2246.140 2.700 ; - RECT 2247.860 1.820 2255.660 2.700 ; - RECT 2257.380 1.820 2265.180 2.700 ; - RECT 2266.900 1.820 2274.700 2.700 ; - RECT 2276.420 1.820 2284.220 2.700 ; - RECT 2285.940 1.820 2293.740 2.700 ; - RECT 2295.460 1.820 2303.260 2.700 ; - RECT 2304.980 1.820 2312.780 2.700 ; - RECT 2314.500 1.820 2322.300 2.700 ; - RECT 2324.020 1.820 2331.820 2.700 ; - RECT 2333.540 1.820 2341.340 2.700 ; - RECT 2343.060 1.820 2350.860 2.700 ; - RECT 2352.580 1.820 2360.380 2.700 ; - RECT 2362.100 1.820 2369.900 2.700 ; - RECT 2371.620 1.820 2379.420 2.700 ; - RECT 2381.140 1.820 2388.940 2.700 ; - RECT 2390.660 1.820 2398.460 2.700 ; - RECT 2400.180 1.820 2407.980 2.700 ; - RECT 2409.700 1.820 2417.500 2.700 ; - RECT 2419.220 1.820 2427.020 2.700 ; - RECT 2428.740 1.820 2436.540 2.700 ; - RECT 2438.260 1.820 2446.060 2.700 ; - RECT 2447.780 1.820 2455.580 2.700 ; - RECT 2457.300 1.820 2465.100 2.700 ; - RECT 2466.820 1.820 2474.620 2.700 ; - RECT 2476.340 1.820 2484.140 2.700 ; - RECT 2485.860 1.820 2493.660 2.700 ; - RECT 2495.380 1.820 2503.180 2.700 ; - RECT 2504.900 1.820 2512.700 2.700 ; - RECT 2514.420 1.820 2522.220 2.700 ; - RECT 2523.940 1.820 2531.740 2.700 ; - RECT 2533.460 1.820 2541.260 2.700 ; - RECT 2542.980 1.820 2550.780 2.700 ; - RECT 2552.500 1.820 2560.300 2.700 ; - RECT 2562.020 1.820 2569.820 2.700 ; - RECT 2571.540 1.820 2579.340 2.700 ; - RECT 2581.060 1.820 2588.860 2.700 ; - RECT 2590.580 1.820 2598.380 2.700 ; - RECT 2600.100 1.820 2607.900 2.700 ; - RECT 2609.620 1.820 2617.420 2.700 ; - RECT 2619.140 1.820 2626.940 2.700 ; - RECT 2628.660 1.820 2636.460 2.700 ; - RECT 2638.180 1.820 2645.980 2.700 ; - RECT 2647.700 1.820 2655.500 2.700 ; - RECT 2657.220 1.820 2665.020 2.700 ; - RECT 2666.740 1.820 2674.540 2.700 ; - RECT 2676.260 1.820 2684.060 2.700 ; - RECT 2685.780 1.820 2693.580 2.700 ; - RECT 2695.300 1.820 2703.100 2.700 ; - RECT 2704.820 1.820 2712.620 2.700 ; - RECT 2714.340 1.820 2722.140 2.700 ; - RECT 2723.860 1.820 2731.660 2.700 ; - RECT 2733.380 1.820 2741.180 2.700 ; - RECT 2742.900 1.820 2750.700 2.700 ; - RECT 2752.420 1.820 2760.220 2.700 ; - RECT 2761.940 1.820 2769.740 2.700 ; - RECT 2771.460 1.820 2779.260 2.700 ; - RECT 2780.980 1.820 2788.780 2.700 ; - RECT 2790.500 1.820 2798.300 2.700 ; - RECT 2800.020 1.820 2807.820 2.700 ; - RECT 2809.540 1.820 2817.340 2.700 ; - RECT 2819.060 1.820 2826.860 2.700 ; - RECT 2828.580 1.820 2836.380 2.700 ; - RECT 2838.100 1.820 2845.900 2.700 ; - RECT 2847.620 1.820 2855.420 2.700 ; - RECT 2857.140 1.820 2864.940 2.700 ; - RECT 2866.660 1.820 2874.460 2.700 ; - RECT 2876.180 1.820 2883.980 2.700 ; - RECT 2885.700 1.820 2893.500 2.700 ; - RECT 2895.220 1.820 2903.020 2.700 ; - RECT 2904.740 1.820 2912.540 2.700 ; - RECT 2914.260 1.820 2922.060 2.700 ; - RECT 2923.780 1.820 2971.220 2.700 ; + RECT 0.140 2977.500 54.860 2979.670 ; + RECT 56.580 2977.500 165.180 2979.670 ; + RECT 166.900 2977.500 275.500 2979.670 ; + RECT 277.220 2977.500 385.820 2979.670 ; + RECT 387.540 2977.500 496.140 2979.670 ; + RECT 497.860 2977.500 606.460 2979.670 ; + RECT 608.180 2977.500 716.780 2979.670 ; + RECT 718.500 2977.500 827.100 2979.670 ; + RECT 828.820 2977.500 937.420 2979.670 ; + RECT 939.140 2977.500 1047.740 2979.670 ; + RECT 1049.460 2977.500 1158.060 2979.670 ; + RECT 1159.780 2977.500 1268.380 2979.670 ; + RECT 1270.100 2977.500 1378.700 2979.670 ; + RECT 1380.420 2977.500 1489.020 2979.670 ; + RECT 1490.740 2977.500 1599.340 2979.670 ; + RECT 1601.060 2977.500 1709.660 2979.670 ; + RECT 1711.380 2977.500 1819.980 2979.670 ; + RECT 1821.700 2977.500 1930.300 2979.670 ; + RECT 1932.020 2977.500 2040.620 2979.670 ; + RECT 2042.340 2977.500 2150.940 2979.670 ; + RECT 2152.660 2977.500 2261.260 2979.670 ; + RECT 2262.980 2977.500 2371.580 2979.670 ; + RECT 2373.300 2977.500 2481.900 2979.670 ; + RECT 2483.620 2977.500 2592.220 2979.670 ; + RECT 2593.940 2977.500 2702.540 2979.670 ; + RECT 2704.260 2977.500 2812.860 2979.670 ; + RECT 2814.580 2977.500 2923.180 2979.670 ; + RECT 2924.900 2977.500 2965.620 2979.670 ; + RECT 0.140 2.700 2965.620 2977.500 ; + RECT 0.140 1.770 56.540 2.700 ; + RECT 58.260 1.770 66.060 2.700 ; + RECT 67.780 1.770 75.580 2.700 ; + RECT 77.300 1.770 85.100 2.700 ; + RECT 86.820 1.770 94.620 2.700 ; + RECT 96.340 1.770 104.140 2.700 ; + RECT 105.860 1.770 113.660 2.700 ; + RECT 115.380 1.770 123.180 2.700 ; + RECT 124.900 1.770 132.700 2.700 ; + RECT 134.420 1.770 142.220 2.700 ; + RECT 143.940 1.770 151.740 2.700 ; + RECT 153.460 1.770 161.260 2.700 ; + RECT 162.980 1.770 170.780 2.700 ; + RECT 172.500 1.770 180.300 2.700 ; + RECT 182.020 1.770 189.820 2.700 ; + RECT 191.540 1.770 199.340 2.700 ; + RECT 201.060 1.770 208.860 2.700 ; + RECT 210.580 1.770 218.380 2.700 ; + RECT 220.100 1.770 227.900 2.700 ; + RECT 229.620 1.770 237.420 2.700 ; + RECT 239.140 1.770 246.940 2.700 ; + RECT 248.660 1.770 256.460 2.700 ; + RECT 258.180 1.770 265.980 2.700 ; + RECT 267.700 1.770 275.500 2.700 ; + RECT 277.220 1.770 285.020 2.700 ; + RECT 286.740 1.770 294.540 2.700 ; + RECT 296.260 1.770 304.060 2.700 ; + RECT 305.780 1.770 313.580 2.700 ; + RECT 315.300 1.770 323.100 2.700 ; + RECT 324.820 1.770 332.620 2.700 ; + RECT 334.340 1.770 342.140 2.700 ; + RECT 343.860 1.770 351.660 2.700 ; + RECT 353.380 1.770 361.180 2.700 ; + RECT 362.900 1.770 370.700 2.700 ; + RECT 372.420 1.770 380.220 2.700 ; + RECT 381.940 1.770 389.740 2.700 ; + RECT 391.460 1.770 399.260 2.700 ; + RECT 400.980 1.770 408.780 2.700 ; + RECT 410.500 1.770 418.300 2.700 ; + RECT 420.020 1.770 427.820 2.700 ; + RECT 429.540 1.770 437.340 2.700 ; + RECT 439.060 1.770 446.860 2.700 ; + RECT 448.580 1.770 456.380 2.700 ; + RECT 458.100 1.770 465.900 2.700 ; + RECT 467.620 1.770 475.420 2.700 ; + RECT 477.140 1.770 484.940 2.700 ; + RECT 486.660 1.770 494.460 2.700 ; + RECT 496.180 1.770 503.980 2.700 ; + RECT 505.700 1.770 513.500 2.700 ; + RECT 515.220 1.770 523.020 2.700 ; + RECT 524.740 1.770 532.540 2.700 ; + RECT 534.260 1.770 542.060 2.700 ; + RECT 543.780 1.770 551.580 2.700 ; + RECT 553.300 1.770 561.100 2.700 ; + RECT 562.820 1.770 570.620 2.700 ; + RECT 572.340 1.770 580.140 2.700 ; + RECT 581.860 1.770 589.660 2.700 ; + RECT 591.380 1.770 599.180 2.700 ; + RECT 600.900 1.770 608.700 2.700 ; + RECT 610.420 1.770 618.220 2.700 ; + RECT 619.940 1.770 627.740 2.700 ; + RECT 629.460 1.770 637.260 2.700 ; + RECT 638.980 1.770 646.780 2.700 ; + RECT 648.500 1.770 656.300 2.700 ; + RECT 658.020 1.770 665.820 2.700 ; + RECT 667.540 1.770 675.340 2.700 ; + RECT 677.060 1.770 684.860 2.700 ; + RECT 686.580 1.770 694.380 2.700 ; + RECT 696.100 1.770 703.900 2.700 ; + RECT 705.620 1.770 713.420 2.700 ; + RECT 715.140 1.770 722.940 2.700 ; + RECT 724.660 1.770 732.460 2.700 ; + RECT 734.180 1.770 741.980 2.700 ; + RECT 743.700 1.770 751.500 2.700 ; + RECT 753.220 1.770 761.020 2.700 ; + RECT 762.740 1.770 770.540 2.700 ; + RECT 772.260 1.770 780.060 2.700 ; + RECT 781.780 1.770 789.580 2.700 ; + RECT 791.300 1.770 799.100 2.700 ; + RECT 800.820 1.770 808.620 2.700 ; + RECT 810.340 1.770 818.140 2.700 ; + RECT 819.860 1.770 827.660 2.700 ; + RECT 829.380 1.770 837.180 2.700 ; + RECT 838.900 1.770 846.700 2.700 ; + RECT 848.420 1.770 856.220 2.700 ; + RECT 857.940 1.770 865.740 2.700 ; + RECT 867.460 1.770 875.260 2.700 ; + RECT 876.980 1.770 884.780 2.700 ; + RECT 886.500 1.770 894.300 2.700 ; + RECT 896.020 1.770 903.820 2.700 ; + RECT 905.540 1.770 913.340 2.700 ; + RECT 915.060 1.770 922.860 2.700 ; + RECT 924.580 1.770 932.380 2.700 ; + RECT 934.100 1.770 941.900 2.700 ; + RECT 943.620 1.770 951.420 2.700 ; + RECT 953.140 1.770 960.940 2.700 ; + RECT 962.660 1.770 970.460 2.700 ; + RECT 972.180 1.770 979.980 2.700 ; + RECT 981.700 1.770 989.500 2.700 ; + RECT 991.220 1.770 999.020 2.700 ; + RECT 1000.740 1.770 1008.540 2.700 ; + RECT 1010.260 1.770 1018.060 2.700 ; + RECT 1019.780 1.770 1027.580 2.700 ; + RECT 1029.300 1.770 1037.100 2.700 ; + RECT 1038.820 1.770 1046.620 2.700 ; + RECT 1048.340 1.770 1056.140 2.700 ; + RECT 1057.860 1.770 1065.660 2.700 ; + RECT 1067.380 1.770 1075.180 2.700 ; + RECT 1076.900 1.770 1084.700 2.700 ; + RECT 1086.420 1.770 1094.220 2.700 ; + RECT 1095.940 1.770 1103.740 2.700 ; + RECT 1105.460 1.770 1113.260 2.700 ; + RECT 1114.980 1.770 1122.780 2.700 ; + RECT 1124.500 1.770 1132.300 2.700 ; + RECT 1134.020 1.770 1141.820 2.700 ; + RECT 1143.540 1.770 1151.340 2.700 ; + RECT 1153.060 1.770 1160.860 2.700 ; + RECT 1162.580 1.770 1170.380 2.700 ; + RECT 1172.100 1.770 1179.900 2.700 ; + RECT 1181.620 1.770 1189.420 2.700 ; + RECT 1191.140 1.770 1198.940 2.700 ; + RECT 1200.660 1.770 1208.460 2.700 ; + RECT 1210.180 1.770 1217.980 2.700 ; + RECT 1219.700 1.770 1227.500 2.700 ; + RECT 1229.220 1.770 1237.020 2.700 ; + RECT 1238.740 1.770 1246.540 2.700 ; + RECT 1248.260 1.770 1256.060 2.700 ; + RECT 1257.780 1.770 1265.580 2.700 ; + RECT 1267.300 1.770 1275.100 2.700 ; + RECT 1276.820 1.770 1284.620 2.700 ; + RECT 1286.340 1.770 1294.140 2.700 ; + RECT 1295.860 1.770 1303.660 2.700 ; + RECT 1305.380 1.770 1313.180 2.700 ; + RECT 1314.900 1.770 1322.700 2.700 ; + RECT 1324.420 1.770 1332.220 2.700 ; + RECT 1333.940 1.770 1341.740 2.700 ; + RECT 1343.460 1.770 1351.260 2.700 ; + RECT 1352.980 1.770 1360.780 2.700 ; + RECT 1362.500 1.770 1370.300 2.700 ; + RECT 1372.020 1.770 1379.820 2.700 ; + RECT 1381.540 1.770 1389.340 2.700 ; + RECT 1391.060 1.770 1398.860 2.700 ; + RECT 1400.580 1.770 1408.380 2.700 ; + RECT 1410.100 1.770 1417.900 2.700 ; + RECT 1419.620 1.770 1427.420 2.700 ; + RECT 1429.140 1.770 1436.940 2.700 ; + RECT 1438.660 1.770 1446.460 2.700 ; + RECT 1448.180 1.770 1455.980 2.700 ; + RECT 1457.700 1.770 1465.500 2.700 ; + RECT 1467.220 1.770 1475.020 2.700 ; + RECT 1476.740 1.770 1484.540 2.700 ; + RECT 1486.260 1.770 1494.060 2.700 ; + RECT 1495.780 1.770 1503.580 2.700 ; + RECT 1505.300 1.770 1513.100 2.700 ; + RECT 1514.820 1.770 1522.620 2.700 ; + RECT 1524.340 1.770 1532.140 2.700 ; + RECT 1533.860 1.770 1541.660 2.700 ; + RECT 1543.380 1.770 1551.180 2.700 ; + RECT 1552.900 1.770 1560.700 2.700 ; + RECT 1562.420 1.770 1570.220 2.700 ; + RECT 1571.940 1.770 1579.740 2.700 ; + RECT 1581.460 1.770 1589.260 2.700 ; + RECT 1590.980 1.770 1598.780 2.700 ; + RECT 1600.500 1.770 1608.300 2.700 ; + RECT 1610.020 1.770 1617.820 2.700 ; + RECT 1619.540 1.770 1627.340 2.700 ; + RECT 1629.060 1.770 1636.860 2.700 ; + RECT 1638.580 1.770 1646.380 2.700 ; + RECT 1648.100 1.770 1655.900 2.700 ; + RECT 1657.620 1.770 1665.420 2.700 ; + RECT 1667.140 1.770 1674.940 2.700 ; + RECT 1676.660 1.770 1684.460 2.700 ; + RECT 1686.180 1.770 1693.980 2.700 ; + RECT 1695.700 1.770 1703.500 2.700 ; + RECT 1705.220 1.770 1713.020 2.700 ; + RECT 1714.740 1.770 1722.540 2.700 ; + RECT 1724.260 1.770 1732.060 2.700 ; + RECT 1733.780 1.770 1741.580 2.700 ; + RECT 1743.300 1.770 1751.100 2.700 ; + RECT 1752.820 1.770 1760.620 2.700 ; + RECT 1762.340 1.770 1770.140 2.700 ; + RECT 1771.860 1.770 1779.660 2.700 ; + RECT 1781.380 1.770 1789.180 2.700 ; + RECT 1790.900 1.770 1798.700 2.700 ; + RECT 1800.420 1.770 1808.220 2.700 ; + RECT 1809.940 1.770 1817.740 2.700 ; + RECT 1819.460 1.770 1827.260 2.700 ; + RECT 1828.980 1.770 1836.780 2.700 ; + RECT 1838.500 1.770 1846.300 2.700 ; + RECT 1848.020 1.770 1855.820 2.700 ; + RECT 1857.540 1.770 1865.340 2.700 ; + RECT 1867.060 1.770 1874.860 2.700 ; + RECT 1876.580 1.770 1884.380 2.700 ; + RECT 1886.100 1.770 1893.900 2.700 ; + RECT 1895.620 1.770 1903.420 2.700 ; + RECT 1905.140 1.770 1912.940 2.700 ; + RECT 1914.660 1.770 1922.460 2.700 ; + RECT 1924.180 1.770 1931.980 2.700 ; + RECT 1933.700 1.770 1941.500 2.700 ; + RECT 1943.220 1.770 1951.020 2.700 ; + RECT 1952.740 1.770 1960.540 2.700 ; + RECT 1962.260 1.770 1970.060 2.700 ; + RECT 1971.780 1.770 1979.580 2.700 ; + RECT 1981.300 1.770 1989.100 2.700 ; + RECT 1990.820 1.770 1998.620 2.700 ; + RECT 2000.340 1.770 2008.140 2.700 ; + RECT 2009.860 1.770 2017.660 2.700 ; + RECT 2019.380 1.770 2027.180 2.700 ; + RECT 2028.900 1.770 2036.700 2.700 ; + RECT 2038.420 1.770 2046.220 2.700 ; + RECT 2047.940 1.770 2055.740 2.700 ; + RECT 2057.460 1.770 2065.260 2.700 ; + RECT 2066.980 1.770 2074.780 2.700 ; + RECT 2076.500 1.770 2084.300 2.700 ; + RECT 2086.020 1.770 2093.820 2.700 ; + RECT 2095.540 1.770 2103.340 2.700 ; + RECT 2105.060 1.770 2112.860 2.700 ; + RECT 2114.580 1.770 2122.380 2.700 ; + RECT 2124.100 1.770 2131.900 2.700 ; + RECT 2133.620 1.770 2141.420 2.700 ; + RECT 2143.140 1.770 2150.940 2.700 ; + RECT 2152.660 1.770 2160.460 2.700 ; + RECT 2162.180 1.770 2169.980 2.700 ; + RECT 2171.700 1.770 2179.500 2.700 ; + RECT 2181.220 1.770 2189.020 2.700 ; + RECT 2190.740 1.770 2198.540 2.700 ; + RECT 2200.260 1.770 2208.060 2.700 ; + RECT 2209.780 1.770 2217.580 2.700 ; + RECT 2219.300 1.770 2227.100 2.700 ; + RECT 2228.820 1.770 2236.620 2.700 ; + RECT 2238.340 1.770 2246.140 2.700 ; + RECT 2247.860 1.770 2255.660 2.700 ; + RECT 2257.380 1.770 2265.180 2.700 ; + RECT 2266.900 1.770 2274.700 2.700 ; + RECT 2276.420 1.770 2284.220 2.700 ; + RECT 2285.940 1.770 2293.740 2.700 ; + RECT 2295.460 1.770 2303.260 2.700 ; + RECT 2304.980 1.770 2312.780 2.700 ; + RECT 2314.500 1.770 2322.300 2.700 ; + RECT 2324.020 1.770 2331.820 2.700 ; + RECT 2333.540 1.770 2341.340 2.700 ; + RECT 2343.060 1.770 2350.860 2.700 ; + RECT 2352.580 1.770 2360.380 2.700 ; + RECT 2362.100 1.770 2369.900 2.700 ; + RECT 2371.620 1.770 2379.420 2.700 ; + RECT 2381.140 1.770 2388.940 2.700 ; + RECT 2390.660 1.770 2398.460 2.700 ; + RECT 2400.180 1.770 2407.980 2.700 ; + RECT 2409.700 1.770 2417.500 2.700 ; + RECT 2419.220 1.770 2427.020 2.700 ; + RECT 2428.740 1.770 2436.540 2.700 ; + RECT 2438.260 1.770 2446.060 2.700 ; + RECT 2447.780 1.770 2455.580 2.700 ; + RECT 2457.300 1.770 2465.100 2.700 ; + RECT 2466.820 1.770 2474.620 2.700 ; + RECT 2476.340 1.770 2484.140 2.700 ; + RECT 2485.860 1.770 2493.660 2.700 ; + RECT 2495.380 1.770 2503.180 2.700 ; + RECT 2504.900 1.770 2512.700 2.700 ; + RECT 2514.420 1.770 2522.220 2.700 ; + RECT 2523.940 1.770 2531.740 2.700 ; + RECT 2533.460 1.770 2541.260 2.700 ; + RECT 2542.980 1.770 2550.780 2.700 ; + RECT 2552.500 1.770 2560.300 2.700 ; + RECT 2562.020 1.770 2569.820 2.700 ; + RECT 2571.540 1.770 2579.340 2.700 ; + RECT 2581.060 1.770 2588.860 2.700 ; + RECT 2590.580 1.770 2598.380 2.700 ; + RECT 2600.100 1.770 2607.900 2.700 ; + RECT 2609.620 1.770 2617.420 2.700 ; + RECT 2619.140 1.770 2626.940 2.700 ; + RECT 2628.660 1.770 2636.460 2.700 ; + RECT 2638.180 1.770 2645.980 2.700 ; + RECT 2647.700 1.770 2655.500 2.700 ; + RECT 2657.220 1.770 2665.020 2.700 ; + RECT 2666.740 1.770 2674.540 2.700 ; + RECT 2676.260 1.770 2684.060 2.700 ; + RECT 2685.780 1.770 2693.580 2.700 ; + RECT 2695.300 1.770 2703.100 2.700 ; + RECT 2704.820 1.770 2712.620 2.700 ; + RECT 2714.340 1.770 2722.140 2.700 ; + RECT 2723.860 1.770 2731.660 2.700 ; + RECT 2733.380 1.770 2741.180 2.700 ; + RECT 2742.900 1.770 2750.700 2.700 ; + RECT 2752.420 1.770 2760.220 2.700 ; + RECT 2761.940 1.770 2769.740 2.700 ; + RECT 2771.460 1.770 2779.260 2.700 ; + RECT 2780.980 1.770 2788.780 2.700 ; + RECT 2790.500 1.770 2798.300 2.700 ; + RECT 2800.020 1.770 2807.820 2.700 ; + RECT 2809.540 1.770 2817.340 2.700 ; + RECT 2819.060 1.770 2826.860 2.700 ; + RECT 2828.580 1.770 2836.380 2.700 ; + RECT 2838.100 1.770 2845.900 2.700 ; + RECT 2847.620 1.770 2855.420 2.700 ; + RECT 2857.140 1.770 2864.940 2.700 ; + RECT 2866.660 1.770 2874.460 2.700 ; + RECT 2876.180 1.770 2883.980 2.700 ; + RECT 2885.700 1.770 2893.500 2.700 ; + RECT 2895.220 1.770 2903.020 2.700 ; + RECT 2904.740 1.770 2912.540 2.700 ; + RECT 2914.260 1.770 2922.060 2.700 ; + RECT 2923.780 1.770 2965.620 2.700 ; LAYER Metal3 ; - RECT 1.960 2944.500 2978.500 2968.420 ; - RECT 1.960 2942.780 2977.500 2944.500 ; - RECT 1.960 2937.220 2978.500 2942.780 ; - RECT 2.700 2935.500 2978.500 2937.220 ; - RECT 1.960 2878.420 2978.500 2935.500 ; - RECT 1.960 2876.700 2977.500 2878.420 ; - RECT 1.960 2866.660 2978.500 2876.700 ; - RECT 2.700 2864.940 2978.500 2866.660 ; - RECT 1.960 2812.340 2978.500 2864.940 ; - RECT 1.960 2810.620 2977.500 2812.340 ; - RECT 1.960 2796.100 2978.500 2810.620 ; - RECT 2.700 2794.380 2978.500 2796.100 ; - RECT 1.960 2746.260 2978.500 2794.380 ; - RECT 1.960 2744.540 2977.500 2746.260 ; - RECT 1.960 2725.540 2978.500 2744.540 ; - RECT 2.700 2723.820 2978.500 2725.540 ; - RECT 1.960 2680.180 2978.500 2723.820 ; - RECT 1.960 2678.460 2977.500 2680.180 ; - RECT 1.960 2654.980 2978.500 2678.460 ; - RECT 2.700 2653.260 2978.500 2654.980 ; - RECT 1.960 2614.100 2978.500 2653.260 ; - RECT 1.960 2612.380 2977.500 2614.100 ; - RECT 1.960 2584.420 2978.500 2612.380 ; - RECT 2.700 2582.700 2978.500 2584.420 ; - RECT 1.960 2548.020 2978.500 2582.700 ; - RECT 1.960 2546.300 2977.500 2548.020 ; - RECT 1.960 2513.860 2978.500 2546.300 ; - RECT 2.700 2512.140 2978.500 2513.860 ; - RECT 1.960 2481.940 2978.500 2512.140 ; - RECT 1.960 2480.220 2977.500 2481.940 ; - RECT 1.960 2443.300 2978.500 2480.220 ; - RECT 2.700 2441.580 2978.500 2443.300 ; - RECT 1.960 2415.860 2978.500 2441.580 ; - RECT 1.960 2414.140 2977.500 2415.860 ; - RECT 1.960 2372.740 2978.500 2414.140 ; - RECT 2.700 2371.020 2978.500 2372.740 ; - RECT 1.960 2349.780 2978.500 2371.020 ; - RECT 1.960 2348.060 2977.500 2349.780 ; - RECT 1.960 2302.180 2978.500 2348.060 ; - RECT 2.700 2300.460 2978.500 2302.180 ; - RECT 1.960 2283.700 2978.500 2300.460 ; - RECT 1.960 2281.980 2977.500 2283.700 ; - RECT 1.960 2231.620 2978.500 2281.980 ; - RECT 2.700 2229.900 2978.500 2231.620 ; - RECT 1.960 2217.620 2978.500 2229.900 ; - RECT 1.960 2215.900 2977.500 2217.620 ; - RECT 1.960 2161.060 2978.500 2215.900 ; - RECT 2.700 2159.340 2978.500 2161.060 ; - RECT 1.960 2151.540 2978.500 2159.340 ; - RECT 1.960 2149.820 2977.500 2151.540 ; - RECT 1.960 2090.500 2978.500 2149.820 ; - RECT 2.700 2088.780 2978.500 2090.500 ; - RECT 1.960 2085.460 2978.500 2088.780 ; - RECT 1.960 2083.740 2977.500 2085.460 ; - RECT 1.960 2019.940 2978.500 2083.740 ; - RECT 2.700 2019.380 2978.500 2019.940 ; + RECT 0.090 2944.500 2978.360 2979.620 ; + RECT 0.090 2942.780 2977.500 2944.500 ; + RECT 0.090 2937.220 2978.360 2942.780 ; + RECT 2.700 2935.500 2978.360 2937.220 ; + RECT 0.090 2878.420 2978.360 2935.500 ; + RECT 0.090 2876.700 2977.500 2878.420 ; + RECT 0.090 2866.660 2978.360 2876.700 ; + RECT 2.700 2864.940 2978.360 2866.660 ; + RECT 0.090 2812.340 2978.360 2864.940 ; + RECT 0.090 2810.620 2977.500 2812.340 ; + RECT 0.090 2796.100 2978.360 2810.620 ; + RECT 2.700 2794.380 2978.360 2796.100 ; + RECT 0.090 2746.260 2978.360 2794.380 ; + RECT 0.090 2744.540 2977.500 2746.260 ; + RECT 0.090 2725.540 2978.360 2744.540 ; + RECT 2.700 2723.820 2978.360 2725.540 ; + RECT 0.090 2680.180 2978.360 2723.820 ; + RECT 0.090 2678.460 2977.500 2680.180 ; + RECT 0.090 2654.980 2978.360 2678.460 ; + RECT 2.700 2653.260 2978.360 2654.980 ; + RECT 0.090 2614.100 2978.360 2653.260 ; + RECT 0.090 2612.380 2977.500 2614.100 ; + RECT 0.090 2584.420 2978.360 2612.380 ; + RECT 2.700 2582.700 2978.360 2584.420 ; + RECT 0.090 2548.020 2978.360 2582.700 ; + RECT 0.090 2546.300 2977.500 2548.020 ; + RECT 0.090 2513.860 2978.360 2546.300 ; + RECT 2.700 2512.140 2978.360 2513.860 ; + RECT 0.090 2481.940 2978.360 2512.140 ; + RECT 0.090 2480.220 2977.500 2481.940 ; + RECT 0.090 2443.300 2978.360 2480.220 ; + RECT 2.700 2441.580 2978.360 2443.300 ; + RECT 0.090 2415.860 2978.360 2441.580 ; + RECT 0.090 2414.140 2977.500 2415.860 ; + RECT 0.090 2372.740 2978.360 2414.140 ; + RECT 2.700 2371.020 2978.360 2372.740 ; + RECT 0.090 2349.780 2978.360 2371.020 ; + RECT 0.090 2348.060 2977.500 2349.780 ; + RECT 0.090 2302.180 2978.360 2348.060 ; + RECT 2.700 2300.460 2978.360 2302.180 ; + RECT 0.090 2283.700 2978.360 2300.460 ; + RECT 0.090 2281.980 2977.500 2283.700 ; + RECT 0.090 2231.620 2978.360 2281.980 ; + RECT 2.700 2229.900 2978.360 2231.620 ; + RECT 0.090 2217.620 2978.360 2229.900 ; + RECT 0.090 2215.900 2977.500 2217.620 ; + RECT 0.090 2161.060 2978.360 2215.900 ; + RECT 2.700 2159.340 2978.360 2161.060 ; + RECT 0.090 2151.540 2978.360 2159.340 ; + RECT 0.090 2149.820 2977.500 2151.540 ; + RECT 0.090 2090.500 2978.360 2149.820 ; + RECT 2.700 2088.780 2978.360 2090.500 ; + RECT 0.090 2085.460 2978.360 2088.780 ; + RECT 0.090 2083.740 2977.500 2085.460 ; + RECT 0.090 2019.940 2978.360 2083.740 ; + RECT 2.700 2019.380 2978.360 2019.940 ; RECT 2.700 2018.220 2977.500 2019.380 ; - RECT 1.960 2017.660 2977.500 2018.220 ; - RECT 1.960 1953.300 2978.500 2017.660 ; - RECT 1.960 1951.580 2977.500 1953.300 ; - RECT 1.960 1949.380 2978.500 1951.580 ; - RECT 2.700 1947.660 2978.500 1949.380 ; - RECT 1.960 1887.220 2978.500 1947.660 ; - RECT 1.960 1885.500 2977.500 1887.220 ; - RECT 1.960 1878.820 2978.500 1885.500 ; - RECT 2.700 1877.100 2978.500 1878.820 ; - RECT 1.960 1821.140 2978.500 1877.100 ; - RECT 1.960 1819.420 2977.500 1821.140 ; - RECT 1.960 1808.260 2978.500 1819.420 ; - RECT 2.700 1806.540 2978.500 1808.260 ; - RECT 1.960 1755.060 2978.500 1806.540 ; - RECT 1.960 1753.340 2977.500 1755.060 ; - RECT 1.960 1737.700 2978.500 1753.340 ; - RECT 2.700 1735.980 2978.500 1737.700 ; - RECT 1.960 1688.980 2978.500 1735.980 ; - RECT 1.960 1687.260 2977.500 1688.980 ; - RECT 1.960 1667.140 2978.500 1687.260 ; - RECT 2.700 1665.420 2978.500 1667.140 ; - RECT 1.960 1622.900 2978.500 1665.420 ; - RECT 1.960 1621.180 2977.500 1622.900 ; - RECT 1.960 1596.580 2978.500 1621.180 ; - RECT 2.700 1594.860 2978.500 1596.580 ; - RECT 1.960 1556.820 2978.500 1594.860 ; - RECT 1.960 1555.100 2977.500 1556.820 ; - RECT 1.960 1526.020 2978.500 1555.100 ; - RECT 2.700 1524.300 2978.500 1526.020 ; - RECT 1.960 1490.740 2978.500 1524.300 ; - RECT 1.960 1489.020 2977.500 1490.740 ; - RECT 1.960 1455.460 2978.500 1489.020 ; - RECT 2.700 1453.740 2978.500 1455.460 ; - RECT 1.960 1424.660 2978.500 1453.740 ; - RECT 1.960 1422.940 2977.500 1424.660 ; - RECT 1.960 1384.900 2978.500 1422.940 ; - RECT 2.700 1383.180 2978.500 1384.900 ; - RECT 1.960 1358.580 2978.500 1383.180 ; - RECT 1.960 1356.860 2977.500 1358.580 ; - RECT 1.960 1314.340 2978.500 1356.860 ; - RECT 2.700 1312.620 2978.500 1314.340 ; - RECT 1.960 1292.500 2978.500 1312.620 ; - RECT 1.960 1290.780 2977.500 1292.500 ; - RECT 1.960 1243.780 2978.500 1290.780 ; - RECT 2.700 1242.060 2978.500 1243.780 ; - RECT 1.960 1226.420 2978.500 1242.060 ; - RECT 1.960 1224.700 2977.500 1226.420 ; - RECT 1.960 1173.220 2978.500 1224.700 ; - RECT 2.700 1171.500 2978.500 1173.220 ; - RECT 1.960 1160.340 2978.500 1171.500 ; - RECT 1.960 1158.620 2977.500 1160.340 ; - RECT 1.960 1102.660 2978.500 1158.620 ; - RECT 2.700 1100.940 2978.500 1102.660 ; - RECT 1.960 1094.260 2978.500 1100.940 ; - RECT 1.960 1092.540 2977.500 1094.260 ; - RECT 1.960 1032.100 2978.500 1092.540 ; - RECT 2.700 1030.380 2978.500 1032.100 ; - RECT 1.960 1028.180 2978.500 1030.380 ; - RECT 1.960 1026.460 2977.500 1028.180 ; - RECT 1.960 962.100 2978.500 1026.460 ; - RECT 1.960 961.540 2977.500 962.100 ; + RECT 0.090 2017.660 2977.500 2018.220 ; + RECT 0.090 1953.300 2978.360 2017.660 ; + RECT 0.090 1951.580 2977.500 1953.300 ; + RECT 0.090 1949.380 2978.360 1951.580 ; + RECT 2.700 1947.660 2978.360 1949.380 ; + RECT 0.090 1887.220 2978.360 1947.660 ; + RECT 0.090 1885.500 2977.500 1887.220 ; + RECT 0.090 1878.820 2978.360 1885.500 ; + RECT 2.700 1877.100 2978.360 1878.820 ; + RECT 0.090 1821.140 2978.360 1877.100 ; + RECT 0.090 1819.420 2977.500 1821.140 ; + RECT 0.090 1808.260 2978.360 1819.420 ; + RECT 2.700 1806.540 2978.360 1808.260 ; + RECT 0.090 1755.060 2978.360 1806.540 ; + RECT 0.090 1753.340 2977.500 1755.060 ; + RECT 0.090 1737.700 2978.360 1753.340 ; + RECT 2.700 1735.980 2978.360 1737.700 ; + RECT 0.090 1688.980 2978.360 1735.980 ; + RECT 0.090 1687.260 2977.500 1688.980 ; + RECT 0.090 1667.140 2978.360 1687.260 ; + RECT 2.700 1665.420 2978.360 1667.140 ; + RECT 0.090 1622.900 2978.360 1665.420 ; + RECT 0.090 1621.180 2977.500 1622.900 ; + RECT 0.090 1596.580 2978.360 1621.180 ; + RECT 2.700 1594.860 2978.360 1596.580 ; + RECT 0.090 1556.820 2978.360 1594.860 ; + RECT 0.090 1555.100 2977.500 1556.820 ; + RECT 0.090 1526.020 2978.360 1555.100 ; + RECT 2.700 1524.300 2978.360 1526.020 ; + RECT 0.090 1490.740 2978.360 1524.300 ; + RECT 0.090 1489.020 2977.500 1490.740 ; + RECT 0.090 1455.460 2978.360 1489.020 ; + RECT 2.700 1453.740 2978.360 1455.460 ; + RECT 0.090 1424.660 2978.360 1453.740 ; + RECT 0.090 1422.940 2977.500 1424.660 ; + RECT 0.090 1384.900 2978.360 1422.940 ; + RECT 2.700 1383.180 2978.360 1384.900 ; + RECT 0.090 1358.580 2978.360 1383.180 ; + RECT 0.090 1356.860 2977.500 1358.580 ; + RECT 0.090 1314.340 2978.360 1356.860 ; + RECT 2.700 1312.620 2978.360 1314.340 ; + RECT 0.090 1292.500 2978.360 1312.620 ; + RECT 0.090 1290.780 2977.500 1292.500 ; + RECT 0.090 1243.780 2978.360 1290.780 ; + RECT 2.700 1242.060 2978.360 1243.780 ; + RECT 0.090 1226.420 2978.360 1242.060 ; + RECT 0.090 1224.700 2977.500 1226.420 ; + RECT 0.090 1173.220 2978.360 1224.700 ; + RECT 2.700 1171.500 2978.360 1173.220 ; + RECT 0.090 1160.340 2978.360 1171.500 ; + RECT 0.090 1158.620 2977.500 1160.340 ; + RECT 0.090 1102.660 2978.360 1158.620 ; + RECT 2.700 1100.940 2978.360 1102.660 ; + RECT 0.090 1094.260 2978.360 1100.940 ; + RECT 0.090 1092.540 2977.500 1094.260 ; + RECT 0.090 1032.100 2978.360 1092.540 ; + RECT 2.700 1030.380 2978.360 1032.100 ; + RECT 0.090 1028.180 2978.360 1030.380 ; + RECT 0.090 1026.460 2977.500 1028.180 ; + RECT 0.090 962.100 2978.360 1026.460 ; + RECT 0.090 961.540 2977.500 962.100 ; RECT 2.700 960.380 2977.500 961.540 ; - RECT 2.700 959.820 2978.500 960.380 ; - RECT 1.960 896.020 2978.500 959.820 ; - RECT 1.960 894.300 2977.500 896.020 ; - RECT 1.960 890.980 2978.500 894.300 ; - RECT 2.700 889.260 2978.500 890.980 ; - RECT 1.960 829.940 2978.500 889.260 ; - RECT 1.960 828.220 2977.500 829.940 ; - RECT 1.960 820.420 2978.500 828.220 ; - RECT 2.700 818.700 2978.500 820.420 ; - RECT 1.960 763.860 2978.500 818.700 ; - RECT 1.960 762.140 2977.500 763.860 ; - RECT 1.960 749.860 2978.500 762.140 ; - RECT 2.700 748.140 2978.500 749.860 ; - RECT 1.960 697.780 2978.500 748.140 ; - RECT 1.960 696.060 2977.500 697.780 ; - RECT 1.960 679.300 2978.500 696.060 ; - RECT 2.700 677.580 2978.500 679.300 ; - RECT 1.960 631.700 2978.500 677.580 ; - RECT 1.960 629.980 2977.500 631.700 ; - RECT 1.960 608.740 2978.500 629.980 ; - RECT 2.700 607.020 2978.500 608.740 ; - RECT 1.960 565.620 2978.500 607.020 ; - RECT 1.960 563.900 2977.500 565.620 ; - RECT 1.960 538.180 2978.500 563.900 ; - RECT 2.700 536.460 2978.500 538.180 ; - RECT 1.960 499.540 2978.500 536.460 ; - RECT 1.960 497.820 2977.500 499.540 ; - RECT 1.960 467.620 2978.500 497.820 ; - RECT 2.700 465.900 2978.500 467.620 ; - RECT 1.960 433.460 2978.500 465.900 ; - RECT 1.960 431.740 2977.500 433.460 ; - RECT 1.960 397.060 2978.500 431.740 ; - RECT 2.700 395.340 2978.500 397.060 ; - RECT 1.960 367.380 2978.500 395.340 ; - RECT 1.960 365.660 2977.500 367.380 ; - RECT 1.960 326.500 2978.500 365.660 ; - RECT 2.700 324.780 2978.500 326.500 ; - RECT 1.960 301.300 2978.500 324.780 ; - RECT 1.960 299.580 2977.500 301.300 ; - RECT 1.960 255.940 2978.500 299.580 ; - RECT 2.700 254.220 2978.500 255.940 ; - RECT 1.960 235.220 2978.500 254.220 ; - RECT 1.960 233.500 2977.500 235.220 ; - RECT 1.960 185.380 2978.500 233.500 ; - RECT 2.700 183.660 2978.500 185.380 ; - RECT 1.960 169.140 2978.500 183.660 ; - RECT 1.960 167.420 2977.500 169.140 ; - RECT 1.960 114.820 2978.500 167.420 ; - RECT 2.700 113.100 2978.500 114.820 ; - RECT 1.960 103.060 2978.500 113.100 ; - RECT 1.960 101.340 2977.500 103.060 ; - RECT 1.960 44.260 2978.500 101.340 ; - RECT 2.700 42.540 2978.500 44.260 ; - RECT 1.960 36.980 2978.500 42.540 ; - RECT 1.960 35.260 2977.500 36.980 ; - RECT 1.960 15.540 2978.500 35.260 ; + RECT 2.700 959.820 2978.360 960.380 ; + RECT 0.090 896.020 2978.360 959.820 ; + RECT 0.090 894.300 2977.500 896.020 ; + RECT 0.090 890.980 2978.360 894.300 ; + RECT 2.700 889.260 2978.360 890.980 ; + RECT 0.090 829.940 2978.360 889.260 ; + RECT 0.090 828.220 2977.500 829.940 ; + RECT 0.090 820.420 2978.360 828.220 ; + RECT 2.700 818.700 2978.360 820.420 ; + RECT 0.090 763.860 2978.360 818.700 ; + RECT 0.090 762.140 2977.500 763.860 ; + RECT 0.090 749.860 2978.360 762.140 ; + RECT 2.700 748.140 2978.360 749.860 ; + RECT 0.090 697.780 2978.360 748.140 ; + RECT 0.090 696.060 2977.500 697.780 ; + RECT 0.090 679.300 2978.360 696.060 ; + RECT 2.700 677.580 2978.360 679.300 ; + RECT 0.090 631.700 2978.360 677.580 ; + RECT 0.090 629.980 2977.500 631.700 ; + RECT 0.090 608.740 2978.360 629.980 ; + RECT 2.700 607.020 2978.360 608.740 ; + RECT 0.090 565.620 2978.360 607.020 ; + RECT 0.090 563.900 2977.500 565.620 ; + RECT 0.090 538.180 2978.360 563.900 ; + RECT 2.700 536.460 2978.360 538.180 ; + RECT 0.090 499.540 2978.360 536.460 ; + RECT 0.090 497.820 2977.500 499.540 ; + RECT 0.090 467.620 2978.360 497.820 ; + RECT 2.700 465.900 2978.360 467.620 ; + RECT 0.090 433.460 2978.360 465.900 ; + RECT 0.090 431.740 2977.500 433.460 ; + RECT 0.090 397.060 2978.360 431.740 ; + RECT 2.700 395.340 2978.360 397.060 ; + RECT 0.090 367.380 2978.360 395.340 ; + RECT 0.090 365.660 2977.500 367.380 ; + RECT 0.090 326.500 2978.360 365.660 ; + RECT 2.700 324.780 2978.360 326.500 ; + RECT 0.090 301.300 2978.360 324.780 ; + RECT 0.090 299.580 2977.500 301.300 ; + RECT 0.090 255.940 2978.360 299.580 ; + RECT 2.700 254.220 2978.360 255.940 ; + RECT 0.090 235.220 2978.360 254.220 ; + RECT 0.090 233.500 2977.500 235.220 ; + RECT 0.090 185.380 2978.360 233.500 ; + RECT 2.700 183.660 2978.360 185.380 ; + RECT 0.090 169.140 2978.360 183.660 ; + RECT 0.090 167.420 2977.500 169.140 ; + RECT 0.090 114.820 2978.360 167.420 ; + RECT 2.700 113.100 2978.360 114.820 ; + RECT 0.090 103.060 2978.360 113.100 ; + RECT 0.090 101.340 2977.500 103.060 ; + RECT 0.090 44.260 2978.360 101.340 ; + RECT 2.700 42.540 2978.360 44.260 ; + RECT 0.090 36.980 2978.360 42.540 ; + RECT 0.090 35.260 2977.500 36.980 ; + RECT 0.090 1.260 2978.360 35.260 ; LAYER Metal4 ; - RECT 70.700 2587.510 410.030 2874.380 ; - RECT 70.700 2463.290 105.470 2587.510 ; - RECT 109.170 2463.290 150.470 2587.510 ; - RECT 154.170 2463.290 195.470 2587.510 ; - RECT 199.170 2586.560 285.470 2587.510 ; - RECT 199.170 2465.360 240.470 2586.560 ; - RECT 244.170 2465.360 285.470 2586.560 ; - RECT 199.170 2463.290 285.470 2465.360 ; - RECT 289.170 2463.290 330.470 2587.510 ; - RECT 334.170 2463.290 375.470 2587.510 ; - RECT 379.170 2567.000 410.030 2587.510 ; - RECT 413.730 2567.000 420.470 2874.380 ; - RECT 379.170 2489.800 420.470 2567.000 ; - RECT 379.170 2463.290 410.030 2489.800 ; - RECT 70.700 2173.510 410.030 2463.290 ; - RECT 70.700 2049.290 105.470 2173.510 ; - RECT 109.170 2049.290 150.470 2173.510 ; - RECT 154.170 2049.290 195.470 2173.510 ; - RECT 199.170 2172.560 285.470 2173.510 ; - RECT 199.170 2051.360 240.470 2172.560 ; - RECT 244.170 2051.360 285.470 2172.560 ; - RECT 199.170 2049.290 285.470 2051.360 ; - RECT 289.170 2049.290 330.470 2173.510 ; - RECT 334.170 2049.290 375.470 2173.510 ; - RECT 379.170 2159.320 410.030 2173.510 ; - RECT 413.730 2159.320 420.470 2489.800 ; - RECT 379.170 2074.280 420.470 2159.320 ; - RECT 379.170 2049.290 410.030 2074.280 ; - RECT 70.700 1759.510 410.030 2049.290 ; - RECT 70.700 1635.290 105.470 1759.510 ; - RECT 109.170 1635.290 150.470 1759.510 ; - RECT 154.170 1635.290 195.470 1759.510 ; - RECT 199.170 1758.560 285.470 1759.510 ; - RECT 199.170 1637.360 240.470 1758.560 ; - RECT 244.170 1637.360 285.470 1758.560 ; - RECT 199.170 1635.290 285.470 1637.360 ; - RECT 289.170 1635.290 330.470 1759.510 ; - RECT 334.170 1635.290 375.470 1759.510 ; - RECT 379.170 1743.800 410.030 1759.510 ; - RECT 413.730 1743.800 420.470 2074.280 ; - RECT 379.170 1658.760 420.470 1743.800 ; - RECT 379.170 1635.290 410.030 1658.760 ; - RECT 70.700 1345.510 410.030 1635.290 ; - RECT 70.700 1221.290 105.470 1345.510 ; - RECT 109.170 1221.290 150.470 1345.510 ; - RECT 154.170 1221.290 195.470 1345.510 ; - RECT 199.170 1344.560 285.470 1345.510 ; - RECT 199.170 1223.360 240.470 1344.560 ; - RECT 244.170 1223.360 285.470 1344.560 ; - RECT 199.170 1221.290 285.470 1223.360 ; - RECT 289.170 1221.290 330.470 1345.510 ; - RECT 334.170 1221.290 375.470 1345.510 ; - RECT 379.170 1328.280 410.030 1345.510 ; - RECT 413.730 1328.280 420.470 1658.760 ; - RECT 379.170 1243.240 420.470 1328.280 ; - RECT 379.170 1221.290 410.030 1243.240 ; - RECT 70.700 931.510 410.030 1221.290 ; - RECT 70.700 807.290 105.470 931.510 ; - RECT 109.170 807.290 150.470 931.510 ; - RECT 154.170 807.290 195.470 931.510 ; - RECT 199.170 930.560 285.470 931.510 ; - RECT 199.170 809.360 240.470 930.560 ; - RECT 244.170 809.360 285.470 930.560 ; - RECT 199.170 807.290 285.470 809.360 ; - RECT 289.170 807.290 330.470 931.510 ; - RECT 334.170 807.290 375.470 931.510 ; - RECT 379.170 912.760 410.030 931.510 ; - RECT 413.730 912.760 420.470 1243.240 ; - RECT 379.170 827.765 420.470 912.760 ; - RECT 379.170 807.290 410.030 827.765 ; - RECT 70.700 517.510 410.030 807.290 ; - RECT 70.700 393.290 105.470 517.510 ; - RECT 109.170 393.290 150.470 517.510 ; - RECT 154.170 393.290 195.470 517.510 ; - RECT 199.170 516.560 285.470 517.510 ; - RECT 199.170 395.360 240.470 516.560 ; - RECT 244.170 395.360 285.470 516.560 ; - RECT 199.170 393.290 285.470 395.360 ; - RECT 289.170 393.290 330.470 517.510 ; - RECT 334.170 393.290 375.470 517.510 ; - RECT 379.170 497.240 410.030 517.510 ; - RECT 413.730 497.240 420.470 827.765 ; - RECT 379.170 420.040 420.470 497.240 ; - RECT 379.170 393.290 410.030 420.040 ; - RECT 70.700 103.510 410.030 393.290 ; - RECT 70.700 16.330 105.470 103.510 ; - RECT 109.170 16.330 150.470 103.510 ; - RECT 154.170 16.330 195.470 103.510 ; - RECT 199.170 102.560 285.470 103.510 ; - RECT 199.170 16.330 240.470 102.560 ; - RECT 244.170 16.330 285.470 102.560 ; - RECT 289.170 16.330 330.470 103.510 ; - RECT 334.170 16.330 375.470 103.510 ; - RECT 379.170 81.720 410.030 103.510 ; - RECT 413.730 81.720 420.470 420.040 ; - RECT 379.170 16.330 420.470 81.720 ; - RECT 424.170 2587.510 735.470 2874.380 ; - RECT 424.170 2463.290 465.470 2587.510 ; - RECT 469.170 2463.290 510.470 2587.510 ; - RECT 514.170 2463.290 555.470 2587.510 ; - RECT 559.170 2586.560 645.470 2587.510 ; - RECT 559.170 2465.360 600.470 2586.560 ; - RECT 604.170 2465.360 645.470 2586.560 ; - RECT 559.170 2463.290 645.470 2465.360 ; - RECT 649.170 2463.290 690.470 2587.510 ; - RECT 694.170 2463.290 735.470 2587.510 ; - RECT 424.170 2173.510 735.470 2463.290 ; - RECT 424.170 2049.290 465.470 2173.510 ; - RECT 469.170 2049.290 510.470 2173.510 ; - RECT 514.170 2049.290 555.470 2173.510 ; - RECT 559.170 2172.560 645.470 2173.510 ; - RECT 559.170 2051.360 600.470 2172.560 ; - RECT 604.170 2051.360 645.470 2172.560 ; - RECT 559.170 2049.290 645.470 2051.360 ; - RECT 649.170 2049.290 690.470 2173.510 ; - RECT 694.170 2049.290 735.470 2173.510 ; - RECT 424.170 1759.510 735.470 2049.290 ; - RECT 424.170 1635.290 465.470 1759.510 ; - RECT 469.170 1635.290 510.470 1759.510 ; - RECT 514.170 1635.290 555.470 1759.510 ; - RECT 559.170 1758.560 645.470 1759.510 ; - RECT 559.170 1637.360 600.470 1758.560 ; - RECT 604.170 1637.360 645.470 1758.560 ; - RECT 559.170 1635.290 645.470 1637.360 ; - RECT 649.170 1635.290 690.470 1759.510 ; - RECT 694.170 1635.290 735.470 1759.510 ; - RECT 424.170 1345.510 735.470 1635.290 ; - RECT 424.170 1221.290 465.470 1345.510 ; - RECT 469.170 1221.290 510.470 1345.510 ; - RECT 514.170 1221.290 555.470 1345.510 ; - RECT 559.170 1344.560 645.470 1345.510 ; - RECT 559.170 1223.360 600.470 1344.560 ; - RECT 604.170 1223.360 645.470 1344.560 ; - RECT 559.170 1221.290 645.470 1223.360 ; - RECT 649.170 1221.290 690.470 1345.510 ; - RECT 694.170 1221.290 735.470 1345.510 ; - RECT 424.170 931.510 735.470 1221.290 ; - RECT 424.170 807.290 465.470 931.510 ; - RECT 469.170 807.290 510.470 931.510 ; - RECT 514.170 807.290 555.470 931.510 ; - RECT 559.170 930.560 645.470 931.510 ; - RECT 559.170 809.360 600.470 930.560 ; - RECT 604.170 809.360 645.470 930.560 ; - RECT 559.170 807.290 645.470 809.360 ; - RECT 649.170 807.290 690.470 931.510 ; - RECT 694.170 807.290 735.470 931.510 ; - RECT 424.170 517.510 735.470 807.290 ; - RECT 424.170 393.290 465.470 517.510 ; - RECT 469.170 393.290 510.470 517.510 ; - RECT 514.170 393.290 555.470 517.510 ; - RECT 559.170 516.560 645.470 517.510 ; - RECT 559.170 395.360 600.470 516.560 ; - RECT 604.170 395.360 645.470 516.560 ; - RECT 559.170 393.290 645.470 395.360 ; - RECT 649.170 393.290 690.470 517.510 ; - RECT 694.170 393.290 735.470 517.510 ; - RECT 424.170 103.510 735.470 393.290 ; - RECT 424.170 16.330 465.470 103.510 ; - RECT 469.170 16.330 510.470 103.510 ; - RECT 514.170 16.330 555.470 103.510 ; - RECT 559.170 102.560 645.470 103.510 ; - RECT 559.170 16.330 600.470 102.560 ; - RECT 604.170 16.330 645.470 102.560 ; - RECT 649.170 16.330 690.470 103.510 ; - RECT 694.170 16.330 735.470 103.510 ; - RECT 739.170 2697.560 780.470 2874.380 ; - RECT 739.170 2570.920 745.470 2697.560 ; - RECT 749.170 2671.750 780.470 2697.560 ; - RECT 784.170 2671.750 825.470 2874.380 ; - RECT 829.170 2671.750 870.470 2874.380 ; - RECT 874.170 2671.750 915.470 2874.380 ; - RECT 919.170 2671.750 960.470 2874.380 ; - RECT 964.170 2671.750 1005.470 2874.380 ; - RECT 1009.170 2671.750 1050.470 2874.380 ; - RECT 1054.170 2671.750 1095.470 2874.380 ; - RECT 1099.170 2671.750 1140.470 2874.380 ; - RECT 1144.170 2674.380 1185.470 2874.380 ; - RECT 1189.170 2674.380 1230.470 2874.380 ; - RECT 1144.170 2671.750 1230.470 2674.380 ; - RECT 1234.170 2671.750 1275.470 2874.380 ; - RECT 1279.170 2671.750 1320.470 2874.380 ; - RECT 1324.170 2674.380 1365.470 2874.380 ; - RECT 1369.170 2674.380 1410.470 2874.380 ; - RECT 1324.170 2671.750 1410.470 2674.380 ; - RECT 1414.170 2671.750 1455.470 2874.380 ; - RECT 1459.170 2671.750 1500.470 2874.380 ; - RECT 1504.170 2671.750 1545.470 2874.380 ; - RECT 1549.170 2671.750 1590.470 2874.380 ; - RECT 1594.170 2671.750 1635.470 2874.380 ; - RECT 1639.170 2671.750 1680.470 2874.380 ; - RECT 1684.170 2671.750 1725.470 2874.380 ; - RECT 1729.170 2671.750 1770.470 2874.380 ; - RECT 1774.170 2671.750 1815.470 2874.380 ; - RECT 1819.170 2671.750 1860.470 2874.380 ; - RECT 1864.170 2671.750 1905.470 2874.380 ; - RECT 1909.170 2671.750 1950.470 2874.380 ; - RECT 1954.170 2671.750 1995.470 2874.380 ; - RECT 1999.170 2671.750 2040.470 2874.380 ; - RECT 2044.170 2671.750 2085.470 2874.380 ; - RECT 2089.170 2671.750 2130.470 2874.380 ; - RECT 2134.170 2671.750 2175.470 2874.380 ; - RECT 2179.170 2671.750 2220.470 2874.380 ; - RECT 2224.170 2671.750 2265.470 2874.380 ; - RECT 2269.170 2671.750 2310.470 2874.380 ; - RECT 2314.170 2671.750 2355.470 2874.380 ; - RECT 2359.170 2671.750 2400.470 2874.380 ; - RECT 2404.170 2671.750 2445.470 2874.380 ; - RECT 2449.170 2671.750 2490.470 2874.380 ; - RECT 2494.170 2671.750 2535.470 2874.380 ; - RECT 2539.170 2671.750 2580.470 2874.380 ; - RECT 2584.170 2671.750 2625.470 2874.380 ; - RECT 2629.170 2671.750 2670.470 2874.380 ; - RECT 2674.170 2671.750 2715.470 2874.380 ; - RECT 2719.170 2671.750 2760.470 2874.380 ; - RECT 2764.170 2671.750 2805.470 2874.380 ; - RECT 2809.170 2671.750 2850.470 2874.380 ; - RECT 2854.170 2674.380 2895.470 2874.380 ; - RECT 2899.170 2674.380 2940.470 2874.380 ; - RECT 2854.170 2671.750 2940.470 2674.380 ; - RECT 749.170 2570.920 2940.470 2671.750 ; - RECT 739.170 2485.880 2940.470 2570.920 ; - RECT 739.170 2155.400 745.470 2485.880 ; - RECT 749.170 2155.400 2940.470 2485.880 ; - RECT 739.170 2070.360 2940.470 2155.400 ; - RECT 739.170 1739.880 745.470 2070.360 ; - RECT 749.170 1739.880 2940.470 2070.360 ; - RECT 739.170 1654.840 2940.470 1739.880 ; - RECT 739.170 1324.360 745.470 1654.840 ; - RECT 749.170 1324.360 2940.470 1654.840 ; - RECT 739.170 1247.160 2940.470 1324.360 ; - RECT 739.170 916.680 745.470 1247.160 ; - RECT 749.170 916.680 2940.470 1247.160 ; - RECT 739.170 831.640 2940.470 916.680 ; - RECT 739.170 501.160 745.470 831.640 ; - RECT 749.170 501.160 2940.470 831.640 ; - RECT 739.170 416.120 2940.470 501.160 ; - RECT 739.170 320.840 745.470 416.120 ; - RECT 749.170 332.930 2940.470 416.120 ; - RECT 749.170 320.840 780.470 332.930 ; - RECT 739.170 16.330 780.470 320.840 ; - RECT 784.170 16.330 825.470 332.930 ; - RECT 829.170 16.330 870.470 332.930 ; - RECT 874.170 16.330 915.470 332.930 ; - RECT 919.170 16.330 960.470 332.930 ; - RECT 964.170 16.330 1005.470 332.930 ; - RECT 1009.170 16.330 1050.470 332.930 ; - RECT 1054.170 16.330 1095.470 332.930 ; - RECT 1099.170 16.330 1140.470 332.930 ; - RECT 1144.170 16.330 1185.470 332.930 ; - RECT 1189.170 16.330 1230.470 332.930 ; - RECT 1234.170 16.330 1275.470 332.930 ; - RECT 1279.170 16.330 1320.470 332.930 ; - RECT 1324.170 16.330 1365.470 332.930 ; - RECT 1369.170 16.330 1410.470 332.930 ; - RECT 1414.170 16.330 1455.470 332.930 ; - RECT 1459.170 16.330 1500.470 332.930 ; - RECT 1504.170 16.330 1545.470 332.930 ; - RECT 1549.170 16.330 1590.470 332.930 ; - RECT 1594.170 16.330 1635.470 332.930 ; - RECT 1639.170 16.330 1680.470 332.930 ; - RECT 1684.170 16.330 1725.470 332.930 ; - RECT 1729.170 16.330 1770.470 332.930 ; - RECT 1774.170 16.330 1815.470 332.930 ; - RECT 1819.170 16.330 1860.470 332.930 ; - RECT 1864.170 16.330 1905.470 332.930 ; - RECT 1909.170 16.330 1950.470 332.930 ; - RECT 1954.170 16.330 1995.470 332.930 ; - RECT 1999.170 16.330 2040.470 332.930 ; - RECT 2044.170 16.330 2085.470 332.930 ; - RECT 2089.170 16.330 2130.470 332.930 ; - RECT 2134.170 16.330 2175.470 332.930 ; - RECT 2179.170 16.330 2220.470 332.930 ; - RECT 2224.170 16.330 2265.470 332.930 ; - RECT 2269.170 16.330 2310.470 332.930 ; - RECT 2314.170 16.330 2355.470 332.930 ; - RECT 2359.170 16.330 2400.470 332.930 ; - RECT 2404.170 16.330 2445.470 332.930 ; - RECT 2449.170 16.330 2490.470 332.930 ; - RECT 2494.170 16.330 2535.470 332.930 ; - RECT 2539.170 16.330 2580.470 332.930 ; - RECT 2584.170 16.330 2625.470 332.930 ; - RECT 2629.170 16.330 2670.470 332.930 ; - RECT 2674.170 16.330 2715.470 332.930 ; - RECT 2719.170 16.330 2760.470 332.930 ; - RECT 2764.170 16.330 2805.470 332.930 ; - RECT 2809.170 16.330 2850.470 332.930 ; - RECT 2854.170 16.330 2895.470 332.930 ; - RECT 2899.170 16.330 2940.470 332.930 ; - RECT 2944.170 16.330 2958.340 2874.380 ; + RECT 0.140 1.070 15.470 2976.870 ; + RECT 19.170 1.070 28.570 2976.870 ; + RECT 32.270 2910.650 125.470 2976.870 ; + RECT 129.170 2910.650 138.570 2976.870 ; + RECT 142.270 2910.650 235.470 2976.870 ; + RECT 239.170 2910.650 248.570 2976.870 ; + RECT 252.270 2910.650 345.470 2976.870 ; + RECT 32.270 2601.270 345.470 2910.650 ; + RECT 32.270 2490.650 125.470 2601.270 ; + RECT 129.170 2490.650 138.570 2601.270 ; + RECT 142.270 2490.650 235.470 2601.270 ; + RECT 239.170 2490.650 248.570 2601.270 ; + RECT 252.270 2490.650 345.470 2601.270 ; + RECT 32.270 2181.270 345.470 2490.650 ; + RECT 32.270 2070.650 125.470 2181.270 ; + RECT 129.170 2070.650 138.570 2181.270 ; + RECT 142.270 2070.650 235.470 2181.270 ; + RECT 239.170 2070.650 248.570 2181.270 ; + RECT 252.270 2070.650 345.470 2181.270 ; + RECT 32.270 1761.270 345.470 2070.650 ; + RECT 32.270 1650.650 125.470 1761.270 ; + RECT 129.170 1650.650 138.570 1761.270 ; + RECT 142.270 1650.650 235.470 1761.270 ; + RECT 239.170 1650.650 248.570 1761.270 ; + RECT 252.270 1650.650 345.470 1761.270 ; + RECT 32.270 1341.270 345.470 1650.650 ; + RECT 32.270 1230.650 125.470 1341.270 ; + RECT 129.170 1230.650 138.570 1341.270 ; + RECT 142.270 1230.650 235.470 1341.270 ; + RECT 239.170 1230.650 248.570 1341.270 ; + RECT 252.270 1230.650 345.470 1341.270 ; + RECT 32.270 921.270 345.470 1230.650 ; + RECT 32.270 810.650 125.470 921.270 ; + RECT 129.170 810.650 138.570 921.270 ; + RECT 142.270 810.650 235.470 921.270 ; + RECT 239.170 810.650 248.570 921.270 ; + RECT 252.270 810.650 345.470 921.270 ; + RECT 32.270 501.270 345.470 810.650 ; + RECT 32.270 390.650 125.470 501.270 ; + RECT 129.170 390.650 138.570 501.270 ; + RECT 142.270 390.650 235.470 501.270 ; + RECT 239.170 390.650 248.570 501.270 ; + RECT 252.270 390.650 345.470 501.270 ; + RECT 32.270 81.270 345.470 390.650 ; + RECT 32.270 1.070 125.470 81.270 ; + RECT 129.170 1.070 138.570 81.270 ; + RECT 142.270 1.070 235.470 81.270 ; + RECT 239.170 1.070 248.570 81.270 ; + RECT 252.270 1.070 345.470 81.270 ; + RECT 349.170 1.070 358.570 2976.870 ; + RECT 362.270 2910.650 455.470 2976.870 ; + RECT 459.170 2910.650 468.570 2976.870 ; + RECT 472.270 2910.650 565.470 2976.870 ; + RECT 569.170 2910.650 578.570 2976.870 ; + RECT 582.270 2910.650 675.470 2976.870 ; + RECT 362.270 2601.270 675.470 2910.650 ; + RECT 362.270 2490.650 455.470 2601.270 ; + RECT 459.170 2490.650 468.570 2601.270 ; + RECT 472.270 2490.650 565.470 2601.270 ; + RECT 569.170 2490.650 578.570 2601.270 ; + RECT 582.270 2490.650 675.470 2601.270 ; + RECT 362.270 2181.270 675.470 2490.650 ; + RECT 362.270 2070.650 455.470 2181.270 ; + RECT 459.170 2070.650 468.570 2181.270 ; + RECT 472.270 2070.650 565.470 2181.270 ; + RECT 569.170 2070.650 578.570 2181.270 ; + RECT 582.270 2070.650 675.470 2181.270 ; + RECT 362.270 1761.270 675.470 2070.650 ; + RECT 362.270 1650.650 455.470 1761.270 ; + RECT 459.170 1650.650 468.570 1761.270 ; + RECT 472.270 1650.650 565.470 1761.270 ; + RECT 569.170 1650.650 578.570 1761.270 ; + RECT 582.270 1650.650 675.470 1761.270 ; + RECT 362.270 1341.270 675.470 1650.650 ; + RECT 362.270 1230.650 455.470 1341.270 ; + RECT 459.170 1230.650 468.570 1341.270 ; + RECT 472.270 1230.650 565.470 1341.270 ; + RECT 569.170 1230.650 578.570 1341.270 ; + RECT 582.270 1230.650 675.470 1341.270 ; + RECT 362.270 921.270 675.470 1230.650 ; + RECT 362.270 810.650 455.470 921.270 ; + RECT 459.170 810.650 468.570 921.270 ; + RECT 472.270 810.650 565.470 921.270 ; + RECT 569.170 810.650 578.570 921.270 ; + RECT 582.270 810.650 675.470 921.270 ; + RECT 362.270 501.270 675.470 810.650 ; + RECT 362.270 390.650 455.470 501.270 ; + RECT 459.170 390.650 468.570 501.270 ; + RECT 472.270 390.650 565.470 501.270 ; + RECT 569.170 390.650 578.570 501.270 ; + RECT 582.270 390.650 675.470 501.270 ; + RECT 362.270 81.270 675.470 390.650 ; + RECT 362.270 1.070 455.470 81.270 ; + RECT 459.170 1.070 468.570 81.270 ; + RECT 472.270 1.070 565.470 81.270 ; + RECT 569.170 1.070 578.570 81.270 ; + RECT 582.270 1.070 675.470 81.270 ; + RECT 679.170 1.070 688.570 2976.870 ; + RECT 692.270 2864.515 785.470 2976.870 ; + RECT 789.170 2864.515 798.570 2976.870 ; + RECT 802.270 2864.515 895.470 2976.870 ; + RECT 899.170 2864.515 908.570 2976.870 ; + RECT 912.270 2864.515 1005.470 2976.870 ; + RECT 1009.170 2879.780 1018.570 2976.870 ; + RECT 1022.270 2879.780 1115.470 2976.870 ; + RECT 1119.170 2879.780 1128.570 2976.870 ; + RECT 1009.170 2864.515 1128.570 2879.780 ; + RECT 1132.270 2864.515 1225.470 2976.870 ; + RECT 1229.170 2864.515 1238.570 2976.870 ; + RECT 1242.270 2918.980 1335.470 2976.870 ; + RECT 1339.170 2918.980 1348.570 2976.870 ; + RECT 1242.270 2864.515 1348.570 2918.980 ; + RECT 1352.270 2864.515 1445.470 2976.870 ; + RECT 1449.170 2879.780 1458.570 2976.870 ; + RECT 1462.270 2879.780 1555.470 2976.870 ; + RECT 1559.170 2879.780 1568.570 2976.870 ; + RECT 1449.170 2864.515 1568.570 2879.780 ; + RECT 1572.270 2864.515 1665.470 2976.870 ; + RECT 1669.170 2864.515 1678.570 2976.870 ; + RECT 1682.270 2864.515 1775.470 2976.870 ; + RECT 1779.170 2864.515 1788.570 2976.870 ; + RECT 1792.270 2864.515 1885.470 2976.870 ; + RECT 1889.170 2918.980 1898.570 2976.870 ; + RECT 1902.270 2918.980 1995.470 2976.870 ; + RECT 1889.170 2879.780 1995.470 2918.980 ; + RECT 1999.170 2879.780 2008.570 2976.870 ; + RECT 1889.170 2864.515 2008.570 2879.780 ; + RECT 2012.270 2864.515 2105.470 2976.870 ; + RECT 2109.170 2864.515 2118.570 2976.870 ; + RECT 2122.270 2864.515 2215.470 2976.870 ; + RECT 2219.170 2864.515 2228.570 2976.870 ; + RECT 2232.270 2864.515 2325.470 2976.870 ; + RECT 2329.170 2879.780 2338.570 2976.870 ; + RECT 2342.270 2879.780 2435.470 2976.870 ; + RECT 2439.170 2879.780 2448.570 2976.870 ; + RECT 2329.170 2864.515 2448.570 2879.780 ; + RECT 2452.270 2864.515 2545.470 2976.870 ; + RECT 2549.170 2864.515 2558.570 2976.870 ; + RECT 2562.270 2918.980 2655.470 2976.870 ; + RECT 2659.170 2918.980 2668.570 2976.870 ; + RECT 2672.270 2918.980 2765.470 2976.870 ; + RECT 2562.270 2864.515 2765.470 2918.980 ; + RECT 2769.170 2879.780 2778.570 2976.870 ; + RECT 2782.270 2879.780 2875.470 2976.870 ; + RECT 2879.170 2879.780 2888.570 2976.870 ; + RECT 2769.170 2864.515 2888.570 2879.780 ; + RECT 692.270 599.540 2888.570 2864.515 ; + RECT 692.270 574.730 2875.470 599.540 ; + RECT 692.270 1.070 785.470 574.730 ; + RECT 789.170 1.070 798.570 574.730 ; + RECT 802.270 1.070 895.470 574.730 ; + RECT 899.170 1.070 908.570 574.730 ; + RECT 912.270 1.070 1005.470 574.730 ; + RECT 1009.170 1.070 1018.570 574.730 ; + RECT 1022.270 1.070 1115.470 574.730 ; + RECT 1119.170 1.070 1128.570 574.730 ; + RECT 1132.270 1.070 1225.470 574.730 ; + RECT 1229.170 1.070 1238.570 574.730 ; + RECT 1242.270 572.100 1348.570 574.730 ; + RECT 1242.270 1.070 1335.470 572.100 ; + RECT 1339.170 1.070 1348.570 572.100 ; + RECT 1352.270 1.070 1445.470 574.730 ; + RECT 1449.170 1.070 1458.570 574.730 ; + RECT 1462.270 1.070 1555.470 574.730 ; + RECT 1559.170 1.070 1568.570 574.730 ; + RECT 1572.270 1.070 1665.470 574.730 ; + RECT 1669.170 1.070 1678.570 574.730 ; + RECT 1682.270 1.070 1775.470 574.730 ; + RECT 1779.170 1.070 1788.570 574.730 ; + RECT 1792.270 1.070 1885.470 574.730 ; + RECT 1889.170 572.100 1995.470 574.730 ; + RECT 1889.170 1.070 1898.570 572.100 ; + RECT 1902.270 1.070 1995.470 572.100 ; + RECT 1999.170 1.070 2008.570 574.730 ; + RECT 2012.270 1.070 2105.470 574.730 ; + RECT 2109.170 1.070 2118.570 574.730 ; + RECT 2122.270 1.070 2215.470 574.730 ; + RECT 2219.170 1.070 2228.570 574.730 ; + RECT 2232.270 1.070 2325.470 574.730 ; + RECT 2329.170 1.070 2338.570 574.730 ; + RECT 2342.270 1.070 2435.470 574.730 ; + RECT 2439.170 1.070 2448.570 574.730 ; + RECT 2452.270 1.070 2545.470 574.730 ; + RECT 2549.170 1.070 2558.570 574.730 ; + RECT 2562.270 572.100 2765.470 574.730 ; + RECT 2562.270 1.070 2655.470 572.100 ; + RECT 2659.170 1.070 2668.570 572.100 ; + RECT 2672.270 1.070 2765.470 572.100 ; + RECT 2769.170 1.070 2778.570 574.730 ; + RECT 2782.270 1.070 2875.470 574.730 ; + RECT 2879.170 1.070 2888.570 599.540 ; + RECT 2892.270 2948.440 2956.100 2976.870 ; + RECT 2892.270 544.280 2933.950 2948.440 ; + RECT 2937.650 544.280 2947.390 2948.440 ; + RECT 2951.090 544.280 2956.100 2948.440 ; + RECT 2892.270 1.070 2956.100 544.280 ; LAYER Metal5 ; - RECT 71.180 2675.730 2958.420 2676.180 ; - RECT 71.180 2630.730 2958.420 2671.630 ; - RECT 71.180 2585.730 2958.420 2626.630 ; - RECT 71.180 2540.730 2958.420 2581.630 ; - RECT 71.180 2495.730 2958.420 2536.630 ; - RECT 71.180 2450.730 2958.420 2491.630 ; - RECT 71.180 2405.730 2958.420 2446.630 ; - RECT 71.180 2360.730 2958.420 2401.630 ; - RECT 71.180 2315.730 2958.420 2356.630 ; - RECT 71.180 2270.730 2958.420 2311.630 ; - RECT 71.180 2225.730 2958.420 2266.630 ; - RECT 71.180 2180.730 2958.420 2221.630 ; - RECT 71.180 2135.730 2958.420 2176.630 ; - RECT 71.180 2090.730 2958.420 2131.630 ; - RECT 71.180 2045.730 2958.420 2086.630 ; - RECT 71.180 2000.730 2958.420 2041.630 ; - RECT 71.180 1955.730 2958.420 1996.630 ; - RECT 71.180 1910.730 2958.420 1951.630 ; - RECT 71.180 1865.730 2958.420 1906.630 ; - RECT 71.180 1820.730 2958.420 1861.630 ; - RECT 71.180 1775.730 2958.420 1816.630 ; - RECT 71.180 1730.730 2958.420 1771.630 ; - RECT 71.180 1685.730 2958.420 1726.630 ; - RECT 71.180 1640.730 2958.420 1681.630 ; - RECT 71.180 1595.730 2958.420 1636.630 ; - RECT 71.180 1550.730 2958.420 1591.630 ; - RECT 71.180 1505.730 2958.420 1546.630 ; - RECT 71.180 1460.730 2958.420 1501.630 ; - RECT 71.180 1415.730 2958.420 1456.630 ; - RECT 71.180 1370.730 2958.420 1411.630 ; - RECT 71.180 1325.730 2958.420 1366.630 ; - RECT 71.180 1280.730 2958.420 1321.630 ; - RECT 71.180 1235.730 2958.420 1276.630 ; - RECT 71.180 1190.730 2958.420 1231.630 ; - RECT 71.180 1145.730 2958.420 1186.630 ; - RECT 71.180 1100.730 2958.420 1141.630 ; - RECT 71.180 1055.730 2958.420 1096.630 ; - RECT 71.180 1010.730 2958.420 1051.630 ; - RECT 71.180 965.730 2958.420 1006.630 ; - RECT 71.180 920.730 2958.420 961.630 ; - RECT 71.180 875.730 2958.420 916.630 ; - RECT 71.180 830.730 2958.420 871.630 ; - RECT 71.180 785.730 2958.420 826.630 ; - RECT 71.180 740.730 2958.420 781.630 ; - RECT 71.180 695.730 2958.420 736.630 ; - RECT 71.180 650.730 2958.420 691.630 ; - RECT 71.180 605.730 2958.420 646.630 ; - RECT 71.180 560.730 2958.420 601.630 ; - RECT 71.180 515.730 2958.420 556.630 ; - RECT 71.180 470.730 2958.420 511.630 ; - RECT 71.180 425.730 2958.420 466.630 ; - RECT 71.180 380.730 2958.420 421.630 ; - RECT 71.180 335.730 2958.420 376.630 ; - RECT 775.840 331.630 2940.760 335.730 ; - RECT 71.180 290.730 2958.420 331.630 ; - RECT 71.180 245.730 2958.420 286.630 ; - RECT 71.180 200.730 2958.420 241.630 ; - RECT 71.180 155.730 2958.420 196.630 ; - RECT 71.180 110.730 2958.420 151.630 ; - RECT 71.180 65.730 2958.420 106.630 ; - RECT 71.180 37.020 2958.420 61.630 ; + RECT 0.060 2945.730 2956.180 2964.580 ; + RECT 0.060 2900.730 2956.180 2941.630 ; + RECT 0.060 2855.730 2956.180 2896.630 ; + RECT 0.060 2810.730 2956.180 2851.630 ; + RECT 0.060 2765.730 2956.180 2806.630 ; + RECT 0.060 2720.730 2956.180 2761.630 ; + RECT 0.060 2675.730 2956.180 2716.630 ; + RECT 0.060 2630.730 2956.180 2671.630 ; + RECT 0.060 2585.730 2956.180 2626.630 ; + RECT 0.060 2540.730 2956.180 2581.630 ; + RECT 0.060 2495.730 2956.180 2536.630 ; + RECT 0.060 2450.730 2956.180 2491.630 ; + RECT 0.060 2405.730 2956.180 2446.630 ; + RECT 0.060 2360.730 2956.180 2401.630 ; + RECT 0.060 2315.730 2956.180 2356.630 ; + RECT 0.060 2270.730 2956.180 2311.630 ; + RECT 0.060 2225.730 2956.180 2266.630 ; + RECT 0.060 2180.730 2956.180 2221.630 ; + RECT 0.060 2135.730 2956.180 2176.630 ; + RECT 0.060 2090.730 2956.180 2131.630 ; + RECT 0.060 2045.730 2956.180 2086.630 ; + RECT 0.060 2000.730 2956.180 2041.630 ; + RECT 0.060 1955.730 2956.180 1996.630 ; + RECT 0.060 1910.730 2956.180 1951.630 ; + RECT 0.060 1865.730 2956.180 1906.630 ; + RECT 0.060 1820.730 2956.180 1861.630 ; + RECT 0.060 1775.730 2956.180 1816.630 ; + RECT 0.060 1730.730 2956.180 1771.630 ; + RECT 0.060 1685.730 2956.180 1726.630 ; + RECT 0.060 1640.730 2956.180 1681.630 ; + RECT 0.060 1595.730 2956.180 1636.630 ; + RECT 0.060 1550.730 2956.180 1591.630 ; + RECT 0.060 1505.730 2956.180 1546.630 ; + RECT 0.060 1460.730 2956.180 1501.630 ; + RECT 0.060 1415.730 2956.180 1456.630 ; + RECT 0.060 1370.730 2956.180 1411.630 ; + RECT 0.060 1325.730 2956.180 1366.630 ; + RECT 0.060 1280.730 2956.180 1321.630 ; + RECT 0.060 1235.730 2956.180 1276.630 ; + RECT 0.060 1190.730 2956.180 1231.630 ; + RECT 0.060 1145.730 2956.180 1186.630 ; + RECT 0.060 1100.730 2956.180 1141.630 ; + RECT 0.060 1055.730 2956.180 1096.630 ; + RECT 0.060 1010.730 2956.180 1051.630 ; + RECT 0.060 965.730 2956.180 1006.630 ; + RECT 0.060 920.730 2956.180 961.630 ; + RECT 0.060 875.730 2956.180 916.630 ; + RECT 0.060 830.730 2956.180 871.630 ; + RECT 0.060 785.730 2956.180 826.630 ; + RECT 0.060 740.730 2956.180 781.630 ; + RECT 0.060 695.730 2956.180 736.630 ; + RECT 0.060 650.730 2956.180 691.630 ; + RECT 0.060 605.730 2956.180 646.630 ; + RECT 0.060 560.730 2956.180 601.630 ; + RECT 736.740 556.630 2901.660 560.730 ; + RECT 0.060 515.730 2956.180 556.630 ; + RECT 0.060 470.730 2956.180 511.630 ; + RECT 0.060 425.730 2956.180 466.630 ; + RECT 0.060 380.730 2956.180 421.630 ; + RECT 0.060 335.730 2956.180 376.630 ; + RECT 0.060 290.730 2956.180 331.630 ; + RECT 0.060 245.730 2956.180 286.630 ; + RECT 0.060 200.730 2956.180 241.630 ; + RECT 0.060 155.730 2956.180 196.630 ; + RECT 0.060 110.730 2956.180 151.630 ; + RECT 0.060 65.730 2956.180 106.630 ; + RECT 0.060 20.730 2956.180 61.630 ; + RECT 0.060 1.180 2956.180 16.630 ; END END user_project_wrapper END LIBRARY
diff --git a/openlane/config.tcl b/openlane/config.tcl index 95cd6b8..5a9b46f 100644 --- a/openlane/config.tcl +++ b/openlane/config.tcl
@@ -13,23 +13,19 @@ set ::env(FP_PDN_HOFFSET) 3 set ::env(FP_PDN_HORIZONTAL_HALO) 5 set ::env(FP_PDN_VERTICAL_HALO) 5 +set ::env(FP_PDN_VPITCH) 110 +set ::env(FP_PDN_VSPACING) 10 +set ::env(FP_PDN_HSPACING) 41.9 set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) 0.45 -set ::env(DIODE_INSERTION_STRATEGY) 3 -set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 2000.0 +set ::env(PL_TARGET_DENSITY) 0.43 set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1 -set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1 -set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 40 -set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 40 -set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.1 -set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1 -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1 -set ::env(GRT_ADJUSTMENT) 0.5 -set ::env(PDN_CFG) "/home/egor/proj/fpga/impl/open/pdn_cfg.tcl" +set ::env(GRT_ALLOW_CONGESTION) 1 +set ::env(GRT_ADJUSTMENT) 0.12 +set ::env(PDN_CFG) "/home/egor/proj/fpga2/impl/open/pdn_cfg.tcl" set ::env(RUN_KLAYOUT_XOR) 0 -set ::env(VERILOG_FILES_BLACKBOX) "/home/egor/proj/fpga/impl/open/macros.v" -set ::env(EXTRA_LEFS) "/home/egor/proj/fpga/impl/open/best/fpga_struct_block/results/final/lef/fpga_struct_block.lef /home/egor/proj/fpga/impl/open/best/efuse_ctrl/results/final/lef/efuse_ctrl.lef" -set ::env(EXTRA_GDS_FILES) "/home/egor/proj/fpga/impl/open/best/fpga_struct_block/results/final/gds/fpga_struct_block.gds /home/egor/proj/fpga/impl/open/best/efuse_ctrl/results/final/gds/efuse_ctrl.gds" +set ::env(VERILOG_FILES_BLACKBOX) "/home/egor/proj/fpga2/impl/open/macros.v" +set ::env(EXTRA_LEFS) "/home/egor/proj/fpga2/impl/open/best/fpga_struct_block/results/final/lef/fpga_struct_block.lef /home/egor/proj/fpga2/impl/open/best/efuse_ctrl/results/final/lef/efuse_ctrl.lef" +set ::env(EXTRA_GDS_FILES) "/home/egor/proj/fpga2/impl/open/best/fpga_struct_block/results/final/gds/fpga_struct_block.gds /home/egor/proj/fpga2/impl/open/best/efuse_ctrl/results/final/gds/efuse_ctrl.gds" set ::env(MACRO_PLACEMENT_CFG) "designs/user_project_wrapper/macro.cfg" set ::env(DESIGN_NAME) user_project_wrapper set ::env(VERILOG_FILES) "designs/user_project_wrapper/ariel_fpga_top_fromvhdl.v designs/user_project_wrapper/fpga_tech.v designs/user_project_wrapper/user_project_wrapper.v"
diff --git a/openlane/fpga_struct_block/config.tcl b/openlane/fpga_struct_block/config.tcl index 4fe01d1..9d9c4d6 100644 --- a/openlane/fpga_struct_block/config.tcl +++ b/openlane/fpga_struct_block/config.tcl
@@ -2,8 +2,9 @@ set ::env(SYNTH_STRATEGY) "AREA 3" set ::env(CLOCK_PERIOD) 100 set ::env(CLOCK_PORT) "clk_i config_clk_i" -set ::env(FP_CORE_UTIL) 59 -set ::env(PL_TARGET_DENSITY) 0.7 +set ::env(FP_SIZING) "absolute" +set ::env(DIE_AREA) "0 0 250 310" +set ::env(PL_TARGET_DENSITY) 0.72 set ::env(SYNTH_TIMING_DERATE) 0.07 set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_ROUTABILITY_DRIVEN) 1
diff --git a/openlane/fpga_struct_block/fpga_struct_block.sdc b/openlane/fpga_struct_block/fpga_struct_block.sdc index 7c3f5b8..0897b86 100644 --- a/openlane/fpga_struct_block/fpga_struct_block.sdc +++ b/openlane/fpga_struct_block/fpga_struct_block.sdc
@@ -48,63 +48,63 @@ set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.cell_reg.register/D] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.cell_reg.register/D] +set_max_delay -ignore_clock_latency 0.52 -from [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.cell_reg.register/D] # Crossbar constraints -set_max_delay -ignore_clock_latency 7.2 -from [get_pins *logic_block*logic_cells***cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells***cell.in_bufs***cell_tstart.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 7.2 -from [get_ports inputs_i*] -to [get_pins *logic_block*logic_cells***cell.in_bufs***cell_tstart.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 7.4 -from [get_pins *logic_block*logic_cells***cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells***cell.in_bufs***cell_tstart.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 7.4 -from [get_ports inputs_i*] -to [get_pins *logic_block*logic_cells***cell.in_bufs***cell_tstart.tech_buf/$BUFOPIN] # Output constraints -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[0]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*1*cell.cell_reg.register/Q] -to [get_ports outputs_o[0]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[1]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*2*cell.cell_reg.register/Q] -to [get_ports outputs_o[1]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[2]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*3*cell.cell_reg.register/Q] -to [get_ports outputs_o[2]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[3]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*4*cell.cell_reg.register/Q] -to [get_ports outputs_o[3]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[4]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*5*cell.cell_reg.register/Q] -to [get_ports outputs_o[4]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[5]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*6*cell.cell_reg.register/Q] -to [get_ports outputs_o[5]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[6]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*7*cell.cell_reg.register/Q] -to [get_ports outputs_o[6]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[7]] -set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*8*cell.cell_reg.register/Q] -to [get_ports outputs_o[7]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[0]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*1*cell.cell_reg.register/Q] -to [get_ports outputs_o[0]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[1]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*2*cell.cell_reg.register/Q] -to [get_ports outputs_o[1]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[2]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*3*cell.cell_reg.register/Q] -to [get_ports outputs_o[2]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[3]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*4*cell.cell_reg.register/Q] -to [get_ports outputs_o[3]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[4]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*5*cell.cell_reg.register/Q] -to [get_ports outputs_o[4]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[5]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*6*cell.cell_reg.register/Q] -to [get_ports outputs_o[5]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[6]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*7*cell.cell_reg.register/Q] -to [get_ports outputs_o[6]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[7]] +set_max_delay -ignore_clock_latency 2.8 -from [get_pins *logic_block*logic_cells*8*cell.cell_reg.register/Q] -to [get_ports outputs_o[7]] set_input_delay 0.0 -clock [get_clocks config_clk_i] [get_ports config_shift_i]
diff --git a/openlane/macro.cfg b/openlane/macro.cfg index 7dbb66e..679cc64 100644 --- a/openlane/macro.cfg +++ b/openlane/macro.cfg
@@ -1,16 +1,16 @@ -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block 100.0 100.0 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block 100.0 514.0 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block 100.0 927.9999999999999 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block 100.0 1341.9999999999998 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block 100.0 1755.9999999999998 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block 100.0 2169.9999999999995 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block 100.0 2583.9999999999995 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block 435.40000000000003 100.0 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block 435.40000000000003 514.0 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block 435.40000000000003 927.9999999999999 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block 435.40000000000003 1341.9999999999998 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block 435.40000000000003 1755.9999999999998 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block 435.40000000000003 2169.9999999999995 N -ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block 435.40000000000003 2583.9999999999995 N -ariel_fpga_top_inst.efuse 770.8000000000001 336.7 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block 60.0 80.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block 60.0 500.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block 60.0 920.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block 60.0 1340.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block 60.0 1760.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block 60.0 2180.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block 60.0 2600.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block 395.84999999999997 80.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block 395.84999999999997 500.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block 395.84999999999997 920.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block 395.84999999999997 1340.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block 395.84999999999997 1760.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block 395.84999999999997 2180.0 N +ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block 395.84999999999997 2600.0 N +ariel_fpga_top_inst.efuse_mem_inst 731.6999999999999 561.7 N
diff --git a/openlane/user_project_wrapper.sdc b/openlane/user_project_wrapper.sdc index 8ac36b6..36868de 100644 --- a/openlane/user_project_wrapper.sdc +++ b/openlane/user_project_wrapper.sdc
@@ -55,478 +55,478 @@ set_disable_timing [get_cells *loop_breaker*] # Routing node <-> LB constraints -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] -set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i] +set_max_delay -ignore_clock_latency 0.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] # Routing node internal && RN <-> RN constraints -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 2.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 1.4 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] # From IO to routing nodes constraints -set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] -set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:3.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:3.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] -set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] -set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:8.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:8.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] +set_max_delay -ignore_clock_latency 4.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 8.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] +set_max_delay -ignore_clock_latency 4.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:3.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 8.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:3.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] +set_max_delay -ignore_clock_latency 4.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 8.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] +set_max_delay -ignore_clock_latency 4.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:8.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] +set_max_delay -ignore_clock_latency 8.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:8.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*] set_input_delay 0 -clock [get_clocks wb_clk_i] [get_ports wbs*_i]
diff --git a/sdf/efuse_ctrl.sdf.gz b/sdf/efuse_ctrl.sdf.gz index 590e87e..97b0dfa 100644 --- a/sdf/efuse_ctrl.sdf.gz +++ b/sdf/efuse_ctrl.sdf.gz Binary files differ
diff --git a/sdf/fpga_struct_block.sdf.gz b/sdf/fpga_struct_block.sdf.gz index 811a7b5..8e29ee2 100644 --- a/sdf/fpga_struct_block.sdf.gz +++ b/sdf/fpga_struct_block.sdf.gz Binary files differ
diff --git a/sdf/user_project_wrapper.sdf.gz b/sdf/user_project_wrapper.sdf.gz index 75f8c79..71b2142 100644 --- a/sdf/user_project_wrapper.sdf.gz +++ b/sdf/user_project_wrapper.sdf.gz Binary files differ
diff --git a/verilog/gl/efuse_ctrl.v.gz b/verilog/gl/efuse_ctrl.v.gz index 227b046..b728d80 100644 --- a/verilog/gl/efuse_ctrl.v.gz +++ b/verilog/gl/efuse_ctrl.v.gz Binary files differ
diff --git a/verilog/gl/fpga_struct_block.v.gz b/verilog/gl/fpga_struct_block.v.gz index c8471cb..cc4c847 100644 --- a/verilog/gl/fpga_struct_block.v.gz +++ b/verilog/gl/fpga_struct_block.v.gz Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz index b09c8c9..ca5a2f7 100644 --- a/verilog/gl/user_project_wrapper.v.gz +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ
diff --git a/verilog/rtl/ariel_fpga_top_fromvhdl.v b/verilog/rtl/ariel_fpga_top_fromvhdl.v index fd30de2..9eedfae 100644 --- a/verilog/rtl/ariel_fpga_top_fromvhdl.v +++ b/verilog/rtl/ariel_fpga_top_fromvhdl.v
@@ -24,7 +24,7 @@ wire _19_; wire _20_; wire [143:0] _21_; - wire [401:0] _22_; + wire [468:0] _22_; wire _23_; wire [143:0] _24_; wire [1:0] _25_; @@ -70,13 +70,13 @@ wire [2:0] user_irq; wire [31:0] vrnode_data; wire [31:0] vrnode_data_out; - wire [401:0] \wb_arbiter_inst:11 ; - wire [32:0] \wb_arbiter_inst:9 ; + wire [32:0] \wb_arbiter_inst:11 ; + wire [468:0] \wb_arbiter_inst:13 ; input wb_clk_i; wire wb_clk_i; wire [66:0] wb_from_caravel; - wire [197:0] wb_i_bottom; - wire [401:0] wb_o_bottom; + wire [230:0] wb_i_bottom; + wire [468:0] wb_o_bottom; input wb_rst_i; wire wb_rst_i; wire [32:0] wb_to_caravel; @@ -123,17 +123,17 @@ .i(fw_tap_bus[1]), .z(_18_) ); - efuse_ctrl efuse ( + efuse_ctrl efuse_mem_inst ( .wb_ack_o(_16_), - .wb_adr_i(wb_o_bottom[379:370]), + .wb_adr_i(wb_o_bottom[447:437]), .wb_clk_i(wb_clk_i), - .wb_cyc_i(wb_o_bottom[336]), - .wb_dat_i(wb_o_bottom[345:338]), + .wb_cyc_i(wb_o_bottom[403]), + .wb_dat_i(wb_o_bottom[412:405]), .wb_dat_o(_15_), .wb_rst_i(wb_rst_i), - .wb_sel_i(2'h0), - .wb_stb_i(wb_o_bottom[335]), - .wb_we_i(wb_o_bottom[337]) + .wb_sel_i(1'h0), + .wb_stb_i(wb_o_bottom[402]), + .wb_we_i(wb_o_bottom[404]) ); wb_register32_81b45b9a32734d4367912d54c45d3716474431dc fabric_reset_reg_inst ( .reg_i(32'd0), @@ -199,8 +199,8 @@ .\wb_o.dat_o (_03_), .wb_rst_i(wb_rst_i) ); - wb_arbiter_sync_6 wb_arbiter_inst ( - .addr_map(192'h300200003001e0003001a000300120003001100030010000), + wb_arbiter_sync_7 wb_arbiter_inst ( + .addr_map(224'h30030000300200003001e0003001a000300120003001100030010000), .wb_clk_i(wb_clk_i), .wb_i_bottom(wb_i_bottom), .\wb_i_up.adr_i (wb_from_caravel[66:35]), @@ -230,22 +230,22 @@ assign config_vrnode_o = _26_; assign config_hrnode_i = { hrnode_data[1], config_hrnode_clk, hrnode_data[0], config_hrnode_clk }; assign config_hrnode_o = _27_; - assign inputs_i = 144'h000000000000000000000000000000000000; + assign inputs_i = { 69'h000000000000000000, io_in[30:0], fpga_rst[3], wb_o_bottom[335], wb_o_bottom[336], wb_o_bottom[337], wb_o_bottom[377:338] }; assign outputs_o = _24_; assign outputs_o_buf = _28_; assign inputs_i_buf = _21_; assign wb_from_caravel = { wbs_adr_i, wbs_dat_i, wbs_we_i, wbs_cyc_i, wbs_stb_i }; - assign wb_to_caravel = \wb_arbiter_inst:9 ; - assign wb_i_bottom = { 24'hzzzzzz, _15_, _16_, _13_, _12_, _09_, _08_, _06_, _05_, _03_, _02_, _30_, _29_ }; - assign wb_o_bottom = \wb_arbiter_inst:11 ; - assign \wb_arbiter_inst:9 = { _11_, _00_ }; - assign \wb_arbiter_inst:11 = _22_; + assign wb_to_caravel = \wb_arbiter_inst:11 ; + assign wb_i_bottom = { 24'h000000, _15_, _16_, outputs_o[107:76], outputs_o[108], _13_, _12_, _09_, _08_, _06_, _05_, _03_, _02_, _30_, _29_ }; + assign wb_o_bottom = \wb_arbiter_inst:13 ; + assign \wb_arbiter_inst:11 = { _11_, _00_ }; + assign \wb_arbiter_inst:13 = _22_; assign wbs_ack_o = wb_to_caravel[0]; assign wbs_dat_o = wb_to_caravel[32:1]; assign la_data_out = 64'h0000000000000000; assign io_out = outputs_o[37:0]; - assign io_oeb = 38'hzzzzzzzzzz; - assign user_irq = 3'hz; + assign io_oeb = { 35'h000000000, outputs_o[143:141] }; + assign user_irq = 3'h0; endmodule module fpga_cfg_shiftreg_2(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o); @@ -524,70 +524,70 @@ input glb_rst_i; wire glb_rst_i; wire glb_rstn; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31081 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31083 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31091 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31093 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32223 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32225 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32233 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32235 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33365 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33367 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33375 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33377 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34507 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34509 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34517 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34519 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35649 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35651 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35659 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35661 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36791 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36793 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36801 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36803 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37933 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37935 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37943 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37945 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37955 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37957 ; - wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39418 ; - wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39420 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40886 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40888 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40896 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40898 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42028 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42030 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42038 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42040 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43170 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43172 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43180 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43182 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44312 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44314 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44322 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44324 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45454 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45456 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45464 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45466 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46596 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46598 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46606 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46608 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47738 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47740 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47748 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47750 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47760 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47762 ; - wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49223 ; - wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49225 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31125 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31127 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31135 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31137 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32267 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32269 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32277 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32279 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33409 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33411 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33419 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33421 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34551 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34553 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34561 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34563 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35693 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35695 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35703 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35705 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36835 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36837 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36845 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36847 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37977 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37979 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37987 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37989 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37999 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:38001 ; + wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39462 ; + wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39464 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40930 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40932 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40940 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40942 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42072 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42074 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42082 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42084 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43214 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43216 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43224 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43226 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44356 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44358 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44366 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44368 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45498 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45500 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45508 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45510 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46640 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46642 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46650 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46652 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47782 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47784 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47792 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47794 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47804 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47806 ; + wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49267 ; + wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49269 ; wire [37:0] hrnode_cfg_shift_chain; input [143:0] inputs_i; wire [143:0] inputs_i; @@ -602,90 +602,90 @@ wire [335:0] up_tracks_fwd; wire [2351:0] up_tracks_in; wire [335:0] up_tracks_out; - wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2426 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2428 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2416 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2418 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3904 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3906 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3894 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3896 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5382 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5384 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5372 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5374 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6860 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6862 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6850 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6852 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8338 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8340 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8328 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8330 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9816 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9818 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9806 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9808 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11294 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11296 ; - wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11284 ; - wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11286 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12436 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12438 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12426 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12428 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13578 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13580 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13568 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13570 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14720 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14722 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14710 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14712 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15862 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15864 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15852 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15854 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17004 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17006 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16994 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16996 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18146 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18148 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18136 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18138 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19288 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19290 ; - wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19278 ; - wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19280 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20763 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20765 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19300 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19302 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22238 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22240 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20775 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20777 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23713 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23715 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22250 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22252 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25188 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25190 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23725 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23727 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26663 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26665 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25200 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25202 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28138 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28140 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26675 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26677 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29613 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29615 ; - wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28150 ; - wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28152 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2470 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2472 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2460 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2462 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3948 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3950 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3938 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3940 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5426 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5428 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5416 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5418 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6904 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6906 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6894 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6896 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8382 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8384 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8372 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8374 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9860 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9862 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9850 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9852 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11338 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11340 ; + wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11328 ; + wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11330 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12480 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12482 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12470 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12472 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13622 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13624 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13612 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13614 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14764 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14766 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14754 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14756 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15906 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15908 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15896 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15898 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17048 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17050 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17038 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17040 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18190 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18192 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18180 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18182 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19332 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19334 ; + wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19322 ; + wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19324 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20807 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20809 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19344 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19346 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22282 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22284 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20819 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20821 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23757 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23759 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22294 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22296 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25232 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25234 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23769 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23771 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26707 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26709 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25244 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25246 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28182 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28184 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26719 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26721 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29657 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29659 ; + wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28194 ; + wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28196 ; wire [62:0] vrnode_cfg_shift_chain; assign _000_ = ~ glb_rst_i; fpga_io_mux \horizontal_routing_network_x:1.horizontal_routing_network_y:1.down_io.routing_down_io ( @@ -1609,168 +1609,168 @@ assign block_out = { _002_, _004_, _006_, _008_, _010_, _012_, _014_, _016_, _018_, _020_, _022_, _024_, _026_, _028_ }; assign glb_rstn = _000_; assign block_cfg_shift_chain = { config_block_i[1], _013_, _011_, _009_, _007_, _005_, _003_, _001_, config_block_i[3], _027_, _025_, _023_, _021_, _019_, _017_, _015_ }; - assign hrnode_cfg_shift_chain = { _141_, \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31081 , \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31091 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32223 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32233 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33365 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33375 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34507 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34517 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35649 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35659 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36791 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36801 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37933 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37943 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37955 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39418 , _173_, config_hrnode_i[1], _177_, \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40886 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40896 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42028 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42038 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43170 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43180 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44312 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44322 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45454 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45464 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46596 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46606 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47738 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47748 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47760 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49223 , _209_, config_hrnode_i[3] }; - assign vrnode_cfg_shift_chain = { _029_, \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2416 , \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2426 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12426 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12436 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19300 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20763 , _101_, config_vrnode_i[1], _035_, \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3894 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3904 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13568 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13578 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20775 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22238 , _107_, config_vrnode_i[3], _041_, \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5372 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5382 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14710 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14720 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22250 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23713 , _113_, config_vrnode_i[5], _047_, \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6850 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6860 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15852 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15862 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23725 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25188 , _119_, config_vrnode_i[7], _053_, \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8328 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8338 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16994 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17004 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25200 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26663 , _125_, config_vrnode_i[9], _059_, \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9806 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9816 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18136 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18146 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26675 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28138 , _131_, config_vrnode_i[11], _065_, \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11284 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11294 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19278 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19288 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28150 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29613 , _137_, config_vrnode_i[13] }; + assign hrnode_cfg_shift_chain = { _141_, \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31125 , \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31135 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32267 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32277 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33409 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33419 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34551 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34561 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35693 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35703 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36835 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36845 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37977 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37987 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37999 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39462 , _173_, config_hrnode_i[1], _177_, \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40930 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40940 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42072 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42082 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43214 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43224 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44356 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44366 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45498 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45508 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46640 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46650 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47782 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47792 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47804 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49267 , _209_, config_hrnode_i[3] }; + assign vrnode_cfg_shift_chain = { _029_, \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2460 , \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2470 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12470 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12480 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19344 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20807 , _101_, config_vrnode_i[1], _035_, \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3938 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3948 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13612 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13622 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20819 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22282 , _107_, config_vrnode_i[3], _041_, \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5416 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5426 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14754 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14764 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22294 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23757 , _113_, config_vrnode_i[5], _047_, \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6894 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6904 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15896 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15906 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23769 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25232 , _119_, config_vrnode_i[7], _053_, \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8372 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8382 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17038 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17048 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25244 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26707 , _125_, config_vrnode_i[9], _059_, \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9850 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9860 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18180 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18190 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26719 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28182 , _131_, config_vrnode_i[11], _065_, \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11328 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11338 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19322 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19332 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28194 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29657 , _137_, config_vrnode_i[13] }; assign up_tracks_in = { left_tracks_out[241], 1'h0, up_tracks_fwd[320], block_out[111], block_out[107], 1'h0, inputs_i[0], left_tracks_out[242], 1'h0, up_tracks_fwd[321], block_out[111], block_out[107], 1'h0, inputs_i[0], left_tracks_out[243], 1'h0, up_tracks_fwd[322], block_out[111], block_out[107], 1'h0, inputs_i[1], left_tracks_out[244], 1'h0, up_tracks_fwd[323], block_out[111], block_out[107], 1'h0, inputs_i[1], left_tracks_out[245], 1'h0, up_tracks_fwd[324], block_out[111], block_out[107], 1'h0, inputs_i[2], left_tracks_out[246], 1'h0, up_tracks_fwd[325], block_out[111], block_out[107], 1'h0, inputs_i[2], left_tracks_out[247], 1'h0, up_tracks_fwd[326], block_out[111], block_out[107], 1'h0, inputs_i[3], left_tracks_out[248], 1'h0, up_tracks_fwd[327], block_out[111], block_out[107], 1'h0, inputs_i[3], left_tracks_out[249], 1'h0, up_tracks_fwd[328], block_out[111], block_out[107], 1'h0, inputs_i[4], left_tracks_out[250], 1'h0, up_tracks_fwd[329], block_out[111], block_out[107], 1'h0, inputs_i[4], left_tracks_out[251], 1'h0, up_tracks_fwd[330], block_out[111], block_out[107], 1'h0, inputs_i[5], left_tracks_out[252], 1'h0, up_tracks_fwd[331], block_out[111], block_out[107], 1'h0, inputs_i[5], left_tracks_out[253], 1'h0, up_tracks_fwd[332], block_out[111], block_out[107], 1'h0, inputs_i[6], left_tracks_out[254], 1'h0, up_tracks_fwd[333], block_out[111], block_out[107], 1'h0, inputs_i[6], left_tracks_out[255], 1'h0, up_tracks_fwd[334], block_out[111], block_out[107], 1'h0, inputs_i[7], left_tracks_out[240], 1'h0, up_tracks_fwd[335], block_out[111], block_out[107], 1'h0, inputs_i[7], left_tracks_out[225], 1'h0, up_tracks_fwd[304], block_out[103], block_out[99], 1'h0, inputs_i[8], left_tracks_out[226], 1'h0, up_tracks_fwd[305], block_out[103], block_out[99], 1'h0, inputs_i[8], left_tracks_out[227], 1'h0, up_tracks_fwd[306], block_out[103], block_out[99], 1'h0, inputs_i[9], left_tracks_out[228], 1'h0, up_tracks_fwd[307], block_out[103], block_out[99], 1'h0, inputs_i[9], left_tracks_out[229], 1'h0, up_tracks_fwd[308], block_out[103], block_out[99], 1'h0, inputs_i[10], left_tracks_out[230], 1'h0, up_tracks_fwd[309], block_out[103], block_out[99], 1'h0, inputs_i[10], left_tracks_out[231], 1'h0, up_tracks_fwd[310], block_out[103], block_out[99], 1'h0, inputs_i[11], left_tracks_out[232], 1'h0, up_tracks_fwd[311], block_out[103], block_out[99], 1'h0, inputs_i[11], left_tracks_out[233], 1'h0, up_tracks_fwd[312], block_out[103], block_out[99], 1'h0, inputs_i[12], left_tracks_out[234], 1'h0, up_tracks_fwd[313], block_out[103], block_out[99], 1'h0, inputs_i[12], left_tracks_out[235], 1'h0, up_tracks_fwd[314], block_out[103], block_out[99], 1'h0, inputs_i[13], left_tracks_out[236], 1'h0, up_tracks_fwd[315], block_out[103], block_out[99], 1'h0, inputs_i[13], left_tracks_out[237], 1'h0, up_tracks_fwd[316], block_out[103], block_out[99], 1'h0, inputs_i[14], left_tracks_out[238], 1'h0, up_tracks_fwd[317], block_out[103], block_out[99], 1'h0, inputs_i[14], left_tracks_out[239], 1'h0, up_tracks_fwd[318], block_out[103], block_out[99], 1'h0, inputs_i[15], left_tracks_out[224], 1'h0, up_tracks_fwd[319], block_out[103], block_out[99], 1'h0, inputs_i[15], left_tracks_out[209], 1'h0, up_tracks_fwd[288], block_out[95], block_out[91], 1'h0, inputs_i[16], left_tracks_out[210], 1'h0, up_tracks_fwd[289], block_out[95], block_out[91], 1'h0, inputs_i[16], left_tracks_out[211], 1'h0, up_tracks_fwd[290], block_out[95], block_out[91], 1'h0, inputs_i[17], left_tracks_out[212], 1'h0, up_tracks_fwd[291], block_out[95], block_out[91], 1'h0, inputs_i[17], left_tracks_out[213], 1'h0, up_tracks_fwd[292], block_out[95], block_out[91], 1'h0, inputs_i[18], left_tracks_out[214], 1'h0, up_tracks_fwd[293], block_out[95], block_out[91], 1'h0, inputs_i[18], left_tracks_out[215], 1'h0, up_tracks_fwd[294], block_out[95], block_out[91], 1'h0, inputs_i[19], left_tracks_out[216], 1'h0, up_tracks_fwd[295], block_out[95], block_out[91], 1'h0, inputs_i[19], left_tracks_out[217], 1'h0, up_tracks_fwd[296], block_out[95], block_out[91], 1'h0, inputs_i[20], left_tracks_out[218], 1'h0, up_tracks_fwd[297], block_out[95], block_out[91], 1'h0, inputs_i[20], left_tracks_out[219], 1'h0, up_tracks_fwd[298], block_out[95], block_out[91], 1'h0, inputs_i[21], left_tracks_out[220], 1'h0, up_tracks_fwd[299], block_out[95], block_out[91], 1'h0, inputs_i[21], left_tracks_out[221], 1'h0, up_tracks_fwd[300], block_out[95], block_out[91], 1'h0, inputs_i[22], left_tracks_out[222], 1'h0, up_tracks_fwd[301], block_out[95], block_out[91], 1'h0, inputs_i[22], left_tracks_out[223], 1'h0, up_tracks_fwd[302], block_out[95], block_out[91], 1'h0, inputs_i[23], left_tracks_out[208], 1'h0, up_tracks_fwd[303], block_out[95], block_out[91], 1'h0, inputs_i[23], left_tracks_out[193], 1'h0, up_tracks_fwd[272], block_out[87], block_out[83], 1'h0, inputs_i[24], left_tracks_out[194], 1'h0, up_tracks_fwd[273], block_out[87], block_out[83], 1'h0, inputs_i[24], left_tracks_out[195], 1'h0, up_tracks_fwd[274], block_out[87], block_out[83], 1'h0, inputs_i[25], left_tracks_out[196], 1'h0, up_tracks_fwd[275], block_out[87], block_out[83], 1'h0, inputs_i[25], left_tracks_out[197], 1'h0, up_tracks_fwd[276], block_out[87], block_out[83], 1'h0, inputs_i[26], left_tracks_out[198], 1'h0, up_tracks_fwd[277], block_out[87], block_out[83], 1'h0, inputs_i[26], left_tracks_out[199], 1'h0, up_tracks_fwd[278], block_out[87], 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block_out[69], block_out[65], left_tracks_out[43], right_tracks_out[166], up_tracks_fwd[138], block_out[15], block_out[11], block_out[69], block_out[65], left_tracks_out[44], right_tracks_out[165], up_tracks_fwd[139], block_out[15], block_out[11], block_out[69], block_out[65], left_tracks_out[45], right_tracks_out[164], up_tracks_fwd[140], block_out[15], block_out[11], block_out[69], block_out[65], left_tracks_out[46], right_tracks_out[163], up_tracks_fwd[141], block_out[15], block_out[11], block_out[69], block_out[65], left_tracks_out[47], right_tracks_out[162], up_tracks_fwd[142], block_out[15], block_out[11], block_out[69], block_out[65], left_tracks_out[32], right_tracks_out[161], up_tracks_fwd[143], block_out[15], block_out[11], block_out[69], block_out[65], left_tracks_out[17], right_tracks_out[144], up_tracks_fwd[112], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[18], right_tracks_out[159], up_tracks_fwd[113], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[19], right_tracks_out[158], up_tracks_fwd[114], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[20], right_tracks_out[157], up_tracks_fwd[115], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[21], right_tracks_out[156], up_tracks_fwd[116], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[22], right_tracks_out[155], up_tracks_fwd[117], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[23], right_tracks_out[154], up_tracks_fwd[118], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[24], right_tracks_out[153], up_tracks_fwd[119], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[25], right_tracks_out[152], up_tracks_fwd[120], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[26], right_tracks_out[151], up_tracks_fwd[121], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[27], right_tracks_out[150], up_tracks_fwd[122], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[28], right_tracks_out[149], up_tracks_fwd[123], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[29], right_tracks_out[148], up_tracks_fwd[124], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[30], right_tracks_out[147], up_tracks_fwd[125], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[31], right_tracks_out[146], up_tracks_fwd[126], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[16], right_tracks_out[145], up_tracks_fwd[127], block_out[7], block_out[3], block_out[61], block_out[57], 1'h0, right_tracks_out[112], up_tracks_fwd[96], 1'h0, inputs_i[72], block_out[53], block_out[49], 1'h0, right_tracks_out[127], up_tracks_fwd[97], 1'h0, inputs_i[72], block_out[53], block_out[49], 1'h0, right_tracks_out[126], up_tracks_fwd[98], 1'h0, inputs_i[73], block_out[53], block_out[49], 1'h0, right_tracks_out[125], up_tracks_fwd[99], 1'h0, inputs_i[73], block_out[53], block_out[49], 1'h0, right_tracks_out[124], up_tracks_fwd[100], 1'h0, inputs_i[74], block_out[53], block_out[49], 1'h0, right_tracks_out[123], up_tracks_fwd[101], 1'h0, inputs_i[74], block_out[53], block_out[49], 1'h0, right_tracks_out[122], up_tracks_fwd[102], 1'h0, inputs_i[75], block_out[53], block_out[49], 1'h0, right_tracks_out[121], up_tracks_fwd[103], 1'h0, inputs_i[75], block_out[53], block_out[49], 1'h0, right_tracks_out[120], up_tracks_fwd[104], 1'h0, inputs_i[76], block_out[53], block_out[49], 1'h0, right_tracks_out[119], up_tracks_fwd[105], 1'h0, inputs_i[76], block_out[53], block_out[49], 1'h0, right_tracks_out[118], up_tracks_fwd[106], 1'h0, inputs_i[77], block_out[53], block_out[49], 1'h0, right_tracks_out[117], up_tracks_fwd[107], 1'h0, inputs_i[77], block_out[53], block_out[49], 1'h0, right_tracks_out[116], up_tracks_fwd[108], 1'h0, inputs_i[78], block_out[53], block_out[49], 1'h0, right_tracks_out[115], up_tracks_fwd[109], 1'h0, inputs_i[78], block_out[53], block_out[49], 1'h0, right_tracks_out[114], up_tracks_fwd[110], 1'h0, inputs_i[79], block_out[53], block_out[49], 1'h0, right_tracks_out[113], up_tracks_fwd[111], 1'h0, inputs_i[79], block_out[53], block_out[49], 1'h0, right_tracks_out[96], up_tracks_fwd[80], 1'h0, inputs_i[80], block_out[45], block_out[41], 1'h0, right_tracks_out[111], up_tracks_fwd[81], 1'h0, inputs_i[80], block_out[45], block_out[41], 1'h0, right_tracks_out[110], up_tracks_fwd[82], 1'h0, inputs_i[81], block_out[45], block_out[41], 1'h0, right_tracks_out[109], up_tracks_fwd[83], 1'h0, inputs_i[81], block_out[45], block_out[41], 1'h0, right_tracks_out[108], up_tracks_fwd[84], 1'h0, inputs_i[82], block_out[45], block_out[41], 1'h0, right_tracks_out[107], up_tracks_fwd[85], 1'h0, inputs_i[82], block_out[45], block_out[41], 1'h0, right_tracks_out[106], up_tracks_fwd[86], 1'h0, inputs_i[83], block_out[45], block_out[41], 1'h0, right_tracks_out[105], up_tracks_fwd[87], 1'h0, inputs_i[83], block_out[45], block_out[41], 1'h0, right_tracks_out[104], up_tracks_fwd[88], 1'h0, inputs_i[84], block_out[45], block_out[41], 1'h0, right_tracks_out[103], up_tracks_fwd[89], 1'h0, inputs_i[84], block_out[45], block_out[41], 1'h0, right_tracks_out[102], up_tracks_fwd[90], 1'h0, inputs_i[85], block_out[45], block_out[41], 1'h0, right_tracks_out[101], up_tracks_fwd[91], 1'h0, inputs_i[85], block_out[45], block_out[41], 1'h0, right_tracks_out[100], up_tracks_fwd[92], 1'h0, inputs_i[86], block_out[45], block_out[41], 1'h0, right_tracks_out[99], up_tracks_fwd[93], 1'h0, inputs_i[86], block_out[45], block_out[41], 1'h0, right_tracks_out[98], up_tracks_fwd[94], 1'h0, inputs_i[87], block_out[45], block_out[41], 1'h0, right_tracks_out[97], up_tracks_fwd[95], 1'h0, inputs_i[87], block_out[45], block_out[41], 1'h0, right_tracks_out[80], up_tracks_fwd[64], 1'h0, inputs_i[88], block_out[37], block_out[33], 1'h0, right_tracks_out[95], up_tracks_fwd[65], 1'h0, inputs_i[88], block_out[37], block_out[33], 1'h0, right_tracks_out[94], up_tracks_fwd[66], 1'h0, inputs_i[89], block_out[37], block_out[33], 1'h0, right_tracks_out[93], up_tracks_fwd[67], 1'h0, inputs_i[89], block_out[37], block_out[33], 1'h0, right_tracks_out[92], up_tracks_fwd[68], 1'h0, inputs_i[90], block_out[37], block_out[33], 1'h0, right_tracks_out[91], up_tracks_fwd[69], 1'h0, inputs_i[90], block_out[37], block_out[33], 1'h0, right_tracks_out[90], up_tracks_fwd[70], 1'h0, inputs_i[91], block_out[37], block_out[33], 1'h0, right_tracks_out[89], up_tracks_fwd[71], 1'h0, inputs_i[91], block_out[37], block_out[33], 1'h0, right_tracks_out[88], up_tracks_fwd[72], 1'h0, inputs_i[92], block_out[37], block_out[33], 1'h0, right_tracks_out[87], up_tracks_fwd[73], 1'h0, inputs_i[92], block_out[37], block_out[33], 1'h0, right_tracks_out[86], up_tracks_fwd[74], 1'h0, inputs_i[93], block_out[37], block_out[33], 1'h0, right_tracks_out[85], up_tracks_fwd[75], 1'h0, inputs_i[93], block_out[37], block_out[33], 1'h0, right_tracks_out[84], up_tracks_fwd[76], 1'h0, inputs_i[94], block_out[37], block_out[33], 1'h0, right_tracks_out[83], up_tracks_fwd[77], 1'h0, inputs_i[94], block_out[37], block_out[33], 1'h0, right_tracks_out[82], up_tracks_fwd[78], 1'h0, inputs_i[95], block_out[37], block_out[33], 1'h0, right_tracks_out[81], up_tracks_fwd[79], 1'h0, inputs_i[95], block_out[37], block_out[33], 1'h0, right_tracks_out[64], up_tracks_fwd[48], 1'h0, inputs_i[96], block_out[29], block_out[25], 1'h0, right_tracks_out[79], up_tracks_fwd[49], 1'h0, inputs_i[96], block_out[29], block_out[25], 1'h0, right_tracks_out[78], up_tracks_fwd[50], 1'h0, inputs_i[97], block_out[29], block_out[25], 1'h0, right_tracks_out[77], up_tracks_fwd[51], 1'h0, inputs_i[97], block_out[29], block_out[25], 1'h0, right_tracks_out[76], up_tracks_fwd[52], 1'h0, inputs_i[98], block_out[29], block_out[25], 1'h0, right_tracks_out[75], up_tracks_fwd[53], 1'h0, inputs_i[98], block_out[29], block_out[25], 1'h0, right_tracks_out[74], up_tracks_fwd[54], 1'h0, inputs_i[99], block_out[29], block_out[25], 1'h0, right_tracks_out[73], up_tracks_fwd[55], 1'h0, inputs_i[99], block_out[29], block_out[25], 1'h0, right_tracks_out[72], up_tracks_fwd[56], 1'h0, inputs_i[100], block_out[29], block_out[25], 1'h0, right_tracks_out[71], up_tracks_fwd[57], 1'h0, inputs_i[100], block_out[29], block_out[25], 1'h0, right_tracks_out[70], up_tracks_fwd[58], 1'h0, inputs_i[101], block_out[29], block_out[25], 1'h0, right_tracks_out[69], up_tracks_fwd[59], 1'h0, inputs_i[101], block_out[29], block_out[25], 1'h0, right_tracks_out[68], up_tracks_fwd[60], 1'h0, inputs_i[102], block_out[29], block_out[25], 1'h0, right_tracks_out[67], up_tracks_fwd[61], 1'h0, inputs_i[102], block_out[29], block_out[25], 1'h0, right_tracks_out[66], up_tracks_fwd[62], 1'h0, inputs_i[103], block_out[29], block_out[25], 1'h0, right_tracks_out[65], up_tracks_fwd[63], 1'h0, inputs_i[103], block_out[29], block_out[25], 1'h0, right_tracks_out[48], up_tracks_fwd[32], 1'h0, inputs_i[104], block_out[21], block_out[17], 1'h0, right_tracks_out[63], up_tracks_fwd[33], 1'h0, inputs_i[104], block_out[21], block_out[17], 1'h0, right_tracks_out[62], up_tracks_fwd[34], 1'h0, inputs_i[105], block_out[21], block_out[17], 1'h0, right_tracks_out[61], up_tracks_fwd[35], 1'h0, inputs_i[105], block_out[21], block_out[17], 1'h0, right_tracks_out[60], up_tracks_fwd[36], 1'h0, inputs_i[106], block_out[21], block_out[17], 1'h0, right_tracks_out[59], up_tracks_fwd[37], 1'h0, inputs_i[106], block_out[21], block_out[17], 1'h0, right_tracks_out[58], up_tracks_fwd[38], 1'h0, inputs_i[107], block_out[21], block_out[17], 1'h0, right_tracks_out[57], up_tracks_fwd[39], 1'h0, inputs_i[107], block_out[21], block_out[17], 1'h0, right_tracks_out[56], up_tracks_fwd[40], 1'h0, inputs_i[108], block_out[21], block_out[17], 1'h0, right_tracks_out[55], up_tracks_fwd[41], 1'h0, inputs_i[108], block_out[21], block_out[17], 1'h0, right_tracks_out[54], up_tracks_fwd[42], 1'h0, inputs_i[109], block_out[21], block_out[17], 1'h0, right_tracks_out[53], up_tracks_fwd[43], 1'h0, inputs_i[109], block_out[21], block_out[17], 1'h0, right_tracks_out[52], up_tracks_fwd[44], 1'h0, inputs_i[110], block_out[21], block_out[17], 1'h0, right_tracks_out[51], up_tracks_fwd[45], 1'h0, inputs_i[110], block_out[21], block_out[17], 1'h0, right_tracks_out[50], up_tracks_fwd[46], 1'h0, inputs_i[111], block_out[21], block_out[17], 1'h0, right_tracks_out[49], up_tracks_fwd[47], 1'h0, inputs_i[111], block_out[21], block_out[17], 1'h0, right_tracks_out[32], up_tracks_fwd[16], 1'h0, inputs_i[112], block_out[13], block_out[9], 1'h0, right_tracks_out[47], up_tracks_fwd[17], 1'h0, inputs_i[112], block_out[13], block_out[9], 1'h0, right_tracks_out[46], up_tracks_fwd[18], 1'h0, inputs_i[113], block_out[13], block_out[9], 1'h0, right_tracks_out[45], up_tracks_fwd[19], 1'h0, inputs_i[113], block_out[13], block_out[9], 1'h0, right_tracks_out[44], up_tracks_fwd[20], 1'h0, inputs_i[114], block_out[13], block_out[9], 1'h0, right_tracks_out[43], up_tracks_fwd[21], 1'h0, inputs_i[114], block_out[13], block_out[9], 1'h0, right_tracks_out[42], up_tracks_fwd[22], 1'h0, inputs_i[115], block_out[13], block_out[9], 1'h0, right_tracks_out[41], up_tracks_fwd[23], 1'h0, inputs_i[115], block_out[13], block_out[9], 1'h0, right_tracks_out[40], up_tracks_fwd[24], 1'h0, inputs_i[116], block_out[13], block_out[9], 1'h0, right_tracks_out[39], up_tracks_fwd[25], 1'h0, inputs_i[116], block_out[13], block_out[9], 1'h0, right_tracks_out[38], up_tracks_fwd[26], 1'h0, inputs_i[117], block_out[13], block_out[9], 1'h0, right_tracks_out[37], up_tracks_fwd[27], 1'h0, inputs_i[117], block_out[13], block_out[9], 1'h0, right_tracks_out[36], up_tracks_fwd[28], 1'h0, inputs_i[118], block_out[13], block_out[9], 1'h0, right_tracks_out[35], up_tracks_fwd[29], 1'h0, inputs_i[118], block_out[13], block_out[9], 1'h0, right_tracks_out[34], up_tracks_fwd[30], 1'h0, inputs_i[119], block_out[13], block_out[9], 1'h0, right_tracks_out[33], up_tracks_fwd[31], 1'h0, inputs_i[119], block_out[13], block_out[9], 1'h0, right_tracks_out[16], up_tracks_fwd[0], 1'h0, inputs_i[120], block_out[5], block_out[1], 1'h0, right_tracks_out[31], up_tracks_fwd[1], 1'h0, inputs_i[120], block_out[5], block_out[1], 1'h0, right_tracks_out[30], up_tracks_fwd[2], 1'h0, inputs_i[121], block_out[5], block_out[1], 1'h0, right_tracks_out[29], up_tracks_fwd[3], 1'h0, inputs_i[121], block_out[5], block_out[1], 1'h0, right_tracks_out[28], up_tracks_fwd[4], 1'h0, inputs_i[122], block_out[5], block_out[1], 1'h0, right_tracks_out[27], up_tracks_fwd[5], 1'h0, inputs_i[122], block_out[5], block_out[1], 1'h0, right_tracks_out[26], up_tracks_fwd[6], 1'h0, inputs_i[123], block_out[5], block_out[1], 1'h0, right_tracks_out[25], up_tracks_fwd[7], 1'h0, inputs_i[123], block_out[5], block_out[1], 1'h0, right_tracks_out[24], up_tracks_fwd[8], 1'h0, inputs_i[124], block_out[5], block_out[1], 1'h0, right_tracks_out[23], up_tracks_fwd[9], 1'h0, inputs_i[124], block_out[5], block_out[1], 1'h0, right_tracks_out[22], up_tracks_fwd[10], 1'h0, inputs_i[125], block_out[5], block_out[1], 1'h0, right_tracks_out[21], up_tracks_fwd[11], 1'h0, inputs_i[125], block_out[5], block_out[1], 1'h0, right_tracks_out[20], up_tracks_fwd[12], 1'h0, inputs_i[126], block_out[5], block_out[1], 1'h0, right_tracks_out[19], up_tracks_fwd[13], 1'h0, inputs_i[126], block_out[5], block_out[1], 1'h0, right_tracks_out[18], up_tracks_fwd[14], 1'h0, inputs_i[127], block_out[5], block_out[1], 1'h0, right_tracks_out[17], up_tracks_fwd[15], 1'h0, inputs_i[127], block_out[5], block_out[1] }; - assign up_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2418 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3896 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5374 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6852 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8330 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9808 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11286 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12428 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13570 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14712 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15854 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16996 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18138 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19280 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19302 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20777 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22252 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23727 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25202 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26677 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28152 }; + assign up_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2462 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3940 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5418 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6896 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8374 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9852 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11330 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12472 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13614 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14756 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15898 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17040 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18182 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19324 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19346 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20821 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22296 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23771 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25246 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26721 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28196 }; assign down_tracks_in = { 1'h0, left_tracks_out[238], down_tracks_fwd[320], block_out[111], block_out[107], 1'h0, inputs_i[0], 1'h0, left_tracks_out[237], down_tracks_fwd[321], block_out[111], block_out[107], 1'h0, inputs_i[0], 1'h0, left_tracks_out[236], down_tracks_fwd[322], block_out[111], block_out[107], 1'h0, inputs_i[1], 1'h0, left_tracks_out[235], down_tracks_fwd[323], block_out[111], block_out[107], 1'h0, inputs_i[1], 1'h0, left_tracks_out[234], down_tracks_fwd[324], block_out[111], block_out[107], 1'h0, inputs_i[2], 1'h0, left_tracks_out[233], down_tracks_fwd[325], block_out[111], block_out[107], 1'h0, inputs_i[2], 1'h0, left_tracks_out[232], down_tracks_fwd[326], block_out[111], block_out[107], 1'h0, inputs_i[3], 1'h0, left_tracks_out[231], down_tracks_fwd[327], block_out[111], block_out[107], 1'h0, inputs_i[3], 1'h0, left_tracks_out[230], down_tracks_fwd[328], block_out[111], block_out[107], 1'h0, inputs_i[4], 1'h0, left_tracks_out[229], down_tracks_fwd[329], block_out[111], block_out[107], 1'h0, inputs_i[4], 1'h0, left_tracks_out[228], down_tracks_fwd[330], block_out[111], block_out[107], 1'h0, inputs_i[5], 1'h0, left_tracks_out[227], down_tracks_fwd[331], block_out[111], block_out[107], 1'h0, inputs_i[5], 1'h0, left_tracks_out[226], down_tracks_fwd[332], block_out[111], block_out[107], 1'h0, inputs_i[6], 1'h0, left_tracks_out[225], down_tracks_fwd[333], block_out[111], block_out[107], 1'h0, inputs_i[6], 1'h0, left_tracks_out[224], down_tracks_fwd[334], block_out[111], block_out[107], 1'h0, inputs_i[7], 1'h0, left_tracks_out[239], down_tracks_fwd[335], block_out[111], block_out[107], 1'h0, inputs_i[7], 1'h0, left_tracks_out[222], down_tracks_fwd[304], block_out[103], block_out[99], 1'h0, inputs_i[8], 1'h0, left_tracks_out[221], down_tracks_fwd[305], block_out[103], block_out[99], 1'h0, inputs_i[8], 1'h0, left_tracks_out[220], down_tracks_fwd[306], block_out[103], block_out[99], 1'h0, inputs_i[9], 1'h0, left_tracks_out[219], down_tracks_fwd[307], block_out[103], block_out[99], 1'h0, inputs_i[9], 1'h0, left_tracks_out[218], down_tracks_fwd[308], block_out[103], block_out[99], 1'h0, inputs_i[10], 1'h0, left_tracks_out[217], down_tracks_fwd[309], block_out[103], block_out[99], 1'h0, inputs_i[10], 1'h0, left_tracks_out[216], down_tracks_fwd[310], block_out[103], block_out[99], 1'h0, inputs_i[11], 1'h0, left_tracks_out[215], down_tracks_fwd[311], block_out[103], block_out[99], 1'h0, inputs_i[11], 1'h0, left_tracks_out[214], down_tracks_fwd[312], block_out[103], block_out[99], 1'h0, inputs_i[12], 1'h0, left_tracks_out[213], down_tracks_fwd[313], block_out[103], block_out[99], 1'h0, inputs_i[12], 1'h0, left_tracks_out[212], down_tracks_fwd[314], block_out[103], block_out[99], 1'h0, inputs_i[13], 1'h0, left_tracks_out[211], down_tracks_fwd[315], block_out[103], block_out[99], 1'h0, inputs_i[13], 1'h0, left_tracks_out[210], down_tracks_fwd[316], block_out[103], block_out[99], 1'h0, inputs_i[14], 1'h0, left_tracks_out[209], down_tracks_fwd[317], block_out[103], block_out[99], 1'h0, inputs_i[14], 1'h0, left_tracks_out[208], down_tracks_fwd[318], block_out[103], block_out[99], 1'h0, inputs_i[15], 1'h0, left_tracks_out[223], down_tracks_fwd[319], block_out[103], block_out[99], 1'h0, inputs_i[15], 1'h0, left_tracks_out[206], down_tracks_fwd[288], block_out[95], block_out[91], 1'h0, inputs_i[16], 1'h0, left_tracks_out[205], down_tracks_fwd[289], block_out[95], block_out[91], 1'h0, inputs_i[16], 1'h0, left_tracks_out[204], down_tracks_fwd[290], block_out[95], block_out[91], 1'h0, inputs_i[17], 1'h0, left_tracks_out[203], down_tracks_fwd[291], block_out[95], block_out[91], 1'h0, inputs_i[17], 1'h0, left_tracks_out[202], down_tracks_fwd[292], block_out[95], block_out[91], 1'h0, inputs_i[18], 1'h0, left_tracks_out[201], down_tracks_fwd[293], block_out[95], block_out[91], 1'h0, inputs_i[18], 1'h0, left_tracks_out[200], down_tracks_fwd[294], block_out[95], block_out[91], 1'h0, inputs_i[19], 1'h0, left_tracks_out[199], down_tracks_fwd[295], block_out[95], block_out[91], 1'h0, inputs_i[19], 1'h0, left_tracks_out[198], down_tracks_fwd[296], block_out[95], block_out[91], 1'h0, inputs_i[20], 1'h0, left_tracks_out[197], down_tracks_fwd[297], block_out[95], block_out[91], 1'h0, inputs_i[20], 1'h0, left_tracks_out[196], down_tracks_fwd[298], block_out[95], block_out[91], 1'h0, inputs_i[21], 1'h0, left_tracks_out[195], down_tracks_fwd[299], block_out[95], block_out[91], 1'h0, inputs_i[21], 1'h0, left_tracks_out[194], down_tracks_fwd[300], block_out[95], block_out[91], 1'h0, inputs_i[22], 1'h0, left_tracks_out[193], down_tracks_fwd[301], block_out[95], block_out[91], 1'h0, inputs_i[22], 1'h0, left_tracks_out[192], down_tracks_fwd[302], block_out[95], block_out[91], 1'h0, inputs_i[23], 1'h0, left_tracks_out[207], down_tracks_fwd[303], block_out[95], block_out[91], 1'h0, inputs_i[23], 1'h0, left_tracks_out[190], down_tracks_fwd[272], block_out[87], block_out[83], 1'h0, inputs_i[24], 1'h0, left_tracks_out[189], down_tracks_fwd[273], block_out[87], block_out[83], 1'h0, inputs_i[24], 1'h0, left_tracks_out[188], down_tracks_fwd[274], block_out[87], block_out[83], 1'h0, inputs_i[25], 1'h0, left_tracks_out[187], down_tracks_fwd[275], block_out[87], block_out[83], 1'h0, inputs_i[25], 1'h0, left_tracks_out[186], down_tracks_fwd[276], block_out[87], block_out[83], 1'h0, inputs_i[26], 1'h0, left_tracks_out[185], down_tracks_fwd[277], block_out[87], block_out[83], 1'h0, inputs_i[26], 1'h0, left_tracks_out[184], down_tracks_fwd[278], block_out[87], block_out[83], 1'h0, inputs_i[27], 1'h0, left_tracks_out[183], down_tracks_fwd[279], block_out[87], block_out[83], 1'h0, inputs_i[27], 1'h0, left_tracks_out[182], down_tracks_fwd[280], block_out[87], block_out[83], 1'h0, inputs_i[28], 1'h0, left_tracks_out[181], down_tracks_fwd[281], block_out[87], block_out[83], 1'h0, inputs_i[28], 1'h0, left_tracks_out[180], down_tracks_fwd[282], block_out[87], block_out[83], 1'h0, inputs_i[29], 1'h0, left_tracks_out[179], down_tracks_fwd[283], block_out[87], block_out[83], 1'h0, inputs_i[29], 1'h0, left_tracks_out[178], down_tracks_fwd[284], block_out[87], block_out[83], 1'h0, inputs_i[30], 1'h0, left_tracks_out[177], down_tracks_fwd[285], block_out[87], block_out[83], 1'h0, inputs_i[30], 1'h0, left_tracks_out[176], down_tracks_fwd[286], block_out[87], block_out[83], 1'h0, inputs_i[31], 1'h0, left_tracks_out[191], down_tracks_fwd[287], block_out[87], block_out[83], 1'h0, inputs_i[31], 1'h0, left_tracks_out[174], down_tracks_fwd[256], block_out[79], block_out[75], 1'h0, inputs_i[32], 1'h0, left_tracks_out[173], down_tracks_fwd[257], block_out[79], block_out[75], 1'h0, inputs_i[32], 1'h0, left_tracks_out[172], down_tracks_fwd[258], block_out[79], block_out[75], 1'h0, inputs_i[33], 1'h0, left_tracks_out[171], down_tracks_fwd[259], block_out[79], block_out[75], 1'h0, inputs_i[33], 1'h0, left_tracks_out[170], down_tracks_fwd[260], block_out[79], block_out[75], 1'h0, inputs_i[34], 1'h0, left_tracks_out[169], down_tracks_fwd[261], block_out[79], block_out[75], 1'h0, inputs_i[34], 1'h0, left_tracks_out[168], down_tracks_fwd[262], block_out[79], block_out[75], 1'h0, inputs_i[35], 1'h0, left_tracks_out[167], down_tracks_fwd[263], block_out[79], block_out[75], 1'h0, inputs_i[35], 1'h0, left_tracks_out[166], down_tracks_fwd[264], block_out[79], block_out[75], 1'h0, inputs_i[36], 1'h0, left_tracks_out[165], down_tracks_fwd[265], block_out[79], block_out[75], 1'h0, inputs_i[36], 1'h0, left_tracks_out[164], down_tracks_fwd[266], block_out[79], block_out[75], 1'h0, inputs_i[37], 1'h0, left_tracks_out[163], down_tracks_fwd[267], block_out[79], block_out[75], 1'h0, inputs_i[37], 1'h0, left_tracks_out[162], down_tracks_fwd[268], block_out[79], block_out[75], 1'h0, inputs_i[38], 1'h0, left_tracks_out[161], down_tracks_fwd[269], block_out[79], block_out[75], 1'h0, inputs_i[38], 1'h0, left_tracks_out[160], down_tracks_fwd[270], block_out[79], block_out[75], 1'h0, inputs_i[39], 1'h0, left_tracks_out[175], down_tracks_fwd[271], block_out[79], block_out[75], 1'h0, inputs_i[39], 1'h0, left_tracks_out[158], down_tracks_fwd[240], block_out[71], block_out[67], 1'h0, inputs_i[40], 1'h0, left_tracks_out[157], down_tracks_fwd[241], block_out[71], block_out[67], 1'h0, inputs_i[40], 1'h0, left_tracks_out[156], down_tracks_fwd[242], block_out[71], block_out[67], 1'h0, inputs_i[41], 1'h0, left_tracks_out[155], down_tracks_fwd[243], block_out[71], block_out[67], 1'h0, inputs_i[41], 1'h0, left_tracks_out[154], down_tracks_fwd[244], block_out[71], block_out[67], 1'h0, inputs_i[42], 1'h0, left_tracks_out[153], down_tracks_fwd[245], block_out[71], block_out[67], 1'h0, inputs_i[42], 1'h0, left_tracks_out[152], down_tracks_fwd[246], block_out[71], block_out[67], 1'h0, inputs_i[43], 1'h0, left_tracks_out[151], down_tracks_fwd[247], block_out[71], block_out[67], 1'h0, inputs_i[43], 1'h0, left_tracks_out[150], down_tracks_fwd[248], block_out[71], block_out[67], 1'h0, inputs_i[44], 1'h0, left_tracks_out[149], down_tracks_fwd[249], block_out[71], block_out[67], 1'h0, inputs_i[44], 1'h0, left_tracks_out[148], down_tracks_fwd[250], block_out[71], block_out[67], 1'h0, inputs_i[45], 1'h0, left_tracks_out[147], down_tracks_fwd[251], block_out[71], block_out[67], 1'h0, inputs_i[45], 1'h0, left_tracks_out[146], down_tracks_fwd[252], block_out[71], block_out[67], 1'h0, inputs_i[46], 1'h0, left_tracks_out[145], down_tracks_fwd[253], block_out[71], block_out[67], 1'h0, inputs_i[46], 1'h0, left_tracks_out[144], down_tracks_fwd[254], block_out[71], block_out[67], 1'h0, inputs_i[47], 1'h0, left_tracks_out[159], down_tracks_fwd[255], block_out[71], block_out[67], 1'h0, inputs_i[47], 1'h0, left_tracks_out[142], down_tracks_fwd[224], block_out[63], block_out[59], 1'h0, inputs_i[48], 1'h0, left_tracks_out[141], down_tracks_fwd[225], block_out[63], block_out[59], 1'h0, inputs_i[48], 1'h0, left_tracks_out[140], down_tracks_fwd[226], block_out[63], block_out[59], 1'h0, inputs_i[49], 1'h0, left_tracks_out[139], down_tracks_fwd[227], block_out[63], block_out[59], 1'h0, inputs_i[49], 1'h0, left_tracks_out[138], down_tracks_fwd[228], block_out[63], block_out[59], 1'h0, inputs_i[50], 1'h0, left_tracks_out[137], down_tracks_fwd[229], block_out[63], block_out[59], 1'h0, inputs_i[50], 1'h0, left_tracks_out[136], down_tracks_fwd[230], block_out[63], block_out[59], 1'h0, inputs_i[51], 1'h0, left_tracks_out[135], down_tracks_fwd[231], block_out[63], block_out[59], 1'h0, inputs_i[51], 1'h0, left_tracks_out[134], down_tracks_fwd[232], block_out[63], block_out[59], 1'h0, inputs_i[52], 1'h0, left_tracks_out[133], down_tracks_fwd[233], block_out[63], block_out[59], 1'h0, inputs_i[52], 1'h0, left_tracks_out[132], down_tracks_fwd[234], block_out[63], block_out[59], 1'h0, inputs_i[53], 1'h0, left_tracks_out[131], down_tracks_fwd[235], block_out[63], block_out[59], 1'h0, inputs_i[53], 1'h0, left_tracks_out[130], down_tracks_fwd[236], block_out[63], block_out[59], 1'h0, inputs_i[54], 1'h0, left_tracks_out[129], down_tracks_fwd[237], block_out[63], block_out[59], 1'h0, inputs_i[54], 1'h0, left_tracks_out[128], down_tracks_fwd[238], block_out[63], block_out[59], 1'h0, inputs_i[55], 1'h0, left_tracks_out[143], down_tracks_fwd[239], block_out[63], block_out[59], 1'h0, inputs_i[55], right_tracks_out[225], left_tracks_out[110], down_tracks_fwd[208], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[226], left_tracks_out[109], down_tracks_fwd[209], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[227], left_tracks_out[108], down_tracks_fwd[210], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[228], left_tracks_out[107], down_tracks_fwd[211], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[229], left_tracks_out[106], down_tracks_fwd[212], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[230], left_tracks_out[105], down_tracks_fwd[213], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[231], left_tracks_out[104], down_tracks_fwd[214], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[232], left_tracks_out[103], down_tracks_fwd[215], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[233], left_tracks_out[102], down_tracks_fwd[216], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[234], left_tracks_out[101], down_tracks_fwd[217], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[235], left_tracks_out[100], down_tracks_fwd[218], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[236], left_tracks_out[99], down_tracks_fwd[219], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[237], left_tracks_out[98], down_tracks_fwd[220], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[238], left_tracks_out[97], down_tracks_fwd[221], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[239], left_tracks_out[96], down_tracks_fwd[222], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[224], left_tracks_out[111], down_tracks_fwd[223], block_out[55], block_out[51], block_out[109], block_out[105], right_tracks_out[209], left_tracks_out[94], down_tracks_fwd[192], block_out[47], block_out[43], block_out[101], block_out[97], right_tracks_out[210], left_tracks_out[93], down_tracks_fwd[193], block_out[47], block_out[43], block_out[101], block_out[97], right_tracks_out[211], left_tracks_out[92], down_tracks_fwd[194], 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down_tracks_fwd[51], 1'h0, inputs_i[97], block_out[29], block_out[25], right_tracks_out[53], 1'h0, down_tracks_fwd[52], 1'h0, inputs_i[98], block_out[29], block_out[25], right_tracks_out[54], 1'h0, down_tracks_fwd[53], 1'h0, inputs_i[98], block_out[29], block_out[25], right_tracks_out[55], 1'h0, down_tracks_fwd[54], 1'h0, inputs_i[99], block_out[29], block_out[25], right_tracks_out[56], 1'h0, down_tracks_fwd[55], 1'h0, inputs_i[99], block_out[29], block_out[25], right_tracks_out[57], 1'h0, down_tracks_fwd[56], 1'h0, inputs_i[100], block_out[29], block_out[25], right_tracks_out[58], 1'h0, down_tracks_fwd[57], 1'h0, inputs_i[100], block_out[29], block_out[25], right_tracks_out[59], 1'h0, down_tracks_fwd[58], 1'h0, inputs_i[101], block_out[29], block_out[25], right_tracks_out[60], 1'h0, down_tracks_fwd[59], 1'h0, inputs_i[101], block_out[29], block_out[25], right_tracks_out[61], 1'h0, down_tracks_fwd[60], 1'h0, inputs_i[102], block_out[29], block_out[25], right_tracks_out[62], 1'h0, down_tracks_fwd[61], 1'h0, inputs_i[102], block_out[29], block_out[25], right_tracks_out[63], 1'h0, down_tracks_fwd[62], 1'h0, inputs_i[103], block_out[29], block_out[25], right_tracks_out[48], 1'h0, down_tracks_fwd[63], 1'h0, inputs_i[103], block_out[29], block_out[25], right_tracks_out[33], 1'h0, down_tracks_fwd[32], 1'h0, inputs_i[104], block_out[21], block_out[17], right_tracks_out[34], 1'h0, down_tracks_fwd[33], 1'h0, inputs_i[104], block_out[21], block_out[17], right_tracks_out[35], 1'h0, down_tracks_fwd[34], 1'h0, inputs_i[105], block_out[21], block_out[17], right_tracks_out[36], 1'h0, down_tracks_fwd[35], 1'h0, inputs_i[105], block_out[21], block_out[17], right_tracks_out[37], 1'h0, down_tracks_fwd[36], 1'h0, inputs_i[106], block_out[21], block_out[17], right_tracks_out[38], 1'h0, down_tracks_fwd[37], 1'h0, inputs_i[106], block_out[21], block_out[17], right_tracks_out[39], 1'h0, down_tracks_fwd[38], 1'h0, inputs_i[107], block_out[21], block_out[17], right_tracks_out[40], 1'h0, down_tracks_fwd[39], 1'h0, inputs_i[107], block_out[21], block_out[17], right_tracks_out[41], 1'h0, down_tracks_fwd[40], 1'h0, inputs_i[108], block_out[21], block_out[17], right_tracks_out[42], 1'h0, down_tracks_fwd[41], 1'h0, inputs_i[108], block_out[21], block_out[17], right_tracks_out[43], 1'h0, down_tracks_fwd[42], 1'h0, inputs_i[109], block_out[21], block_out[17], right_tracks_out[44], 1'h0, down_tracks_fwd[43], 1'h0, inputs_i[109], block_out[21], block_out[17], right_tracks_out[45], 1'h0, down_tracks_fwd[44], 1'h0, inputs_i[110], block_out[21], block_out[17], right_tracks_out[46], 1'h0, down_tracks_fwd[45], 1'h0, inputs_i[110], block_out[21], block_out[17], right_tracks_out[47], 1'h0, down_tracks_fwd[46], 1'h0, inputs_i[111], block_out[21], block_out[17], right_tracks_out[32], 1'h0, down_tracks_fwd[47], 1'h0, inputs_i[111], block_out[21], block_out[17], right_tracks_out[17], 1'h0, down_tracks_fwd[16], 1'h0, inputs_i[112], block_out[13], block_out[9], right_tracks_out[18], 1'h0, down_tracks_fwd[17], 1'h0, inputs_i[112], block_out[13], block_out[9], right_tracks_out[19], 1'h0, down_tracks_fwd[18], 1'h0, inputs_i[113], block_out[13], block_out[9], right_tracks_out[20], 1'h0, down_tracks_fwd[19], 1'h0, inputs_i[113], block_out[13], block_out[9], right_tracks_out[21], 1'h0, down_tracks_fwd[20], 1'h0, inputs_i[114], block_out[13], block_out[9], right_tracks_out[22], 1'h0, down_tracks_fwd[21], 1'h0, inputs_i[114], block_out[13], block_out[9], right_tracks_out[23], 1'h0, down_tracks_fwd[22], 1'h0, inputs_i[115], block_out[13], block_out[9], right_tracks_out[24], 1'h0, down_tracks_fwd[23], 1'h0, inputs_i[115], block_out[13], block_out[9], right_tracks_out[25], 1'h0, down_tracks_fwd[24], 1'h0, inputs_i[116], block_out[13], block_out[9], right_tracks_out[26], 1'h0, down_tracks_fwd[25], 1'h0, inputs_i[116], block_out[13], block_out[9], right_tracks_out[27], 1'h0, down_tracks_fwd[26], 1'h0, inputs_i[117], block_out[13], block_out[9], right_tracks_out[28], 1'h0, down_tracks_fwd[27], 1'h0, inputs_i[117], block_out[13], block_out[9], right_tracks_out[29], 1'h0, down_tracks_fwd[28], 1'h0, inputs_i[118], block_out[13], block_out[9], right_tracks_out[30], 1'h0, down_tracks_fwd[29], 1'h0, inputs_i[118], block_out[13], block_out[9], right_tracks_out[31], 1'h0, down_tracks_fwd[30], 1'h0, inputs_i[119], block_out[13], block_out[9], right_tracks_out[16], 1'h0, down_tracks_fwd[31], 1'h0, inputs_i[119], block_out[13], block_out[9], right_tracks_out[1], 1'h0, down_tracks_fwd[0], 1'h0, inputs_i[120], block_out[5], block_out[1], right_tracks_out[2], 1'h0, down_tracks_fwd[1], 1'h0, inputs_i[120], block_out[5], block_out[1], right_tracks_out[3], 1'h0, down_tracks_fwd[2], 1'h0, inputs_i[121], block_out[5], block_out[1], right_tracks_out[4], 1'h0, down_tracks_fwd[3], 1'h0, inputs_i[121], block_out[5], block_out[1], right_tracks_out[5], 1'h0, down_tracks_fwd[4], 1'h0, inputs_i[122], block_out[5], block_out[1], right_tracks_out[6], 1'h0, down_tracks_fwd[5], 1'h0, inputs_i[122], block_out[5], block_out[1], right_tracks_out[7], 1'h0, down_tracks_fwd[6], 1'h0, inputs_i[123], block_out[5], block_out[1], right_tracks_out[8], 1'h0, down_tracks_fwd[7], 1'h0, inputs_i[123], block_out[5], block_out[1], right_tracks_out[9], 1'h0, down_tracks_fwd[8], 1'h0, inputs_i[124], block_out[5], block_out[1], right_tracks_out[10], 1'h0, down_tracks_fwd[9], 1'h0, inputs_i[124], block_out[5], block_out[1], right_tracks_out[11], 1'h0, down_tracks_fwd[10], 1'h0, inputs_i[125], block_out[5], block_out[1], right_tracks_out[12], 1'h0, down_tracks_fwd[11], 1'h0, inputs_i[125], block_out[5], block_out[1], right_tracks_out[13], 1'h0, down_tracks_fwd[12], 1'h0, inputs_i[126], block_out[5], block_out[1], right_tracks_out[14], 1'h0, down_tracks_fwd[13], 1'h0, inputs_i[126], block_out[5], block_out[1], right_tracks_out[15], 1'h0, down_tracks_fwd[14], 1'h0, inputs_i[127], block_out[5], block_out[1], right_tracks_out[0], 1'h0, down_tracks_fwd[15], 1'h0, inputs_i[127], block_out[5], block_out[1] }; - assign down_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2428 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3906 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5384 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6862 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8340 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9818 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11296 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12438 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13580 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14722 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15864 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17006 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18148 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19290 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20765 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22240 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23715 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25190 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26665 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28140 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29615 }; + assign down_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2472 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3950 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5428 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6906 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8384 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9862 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11340 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12482 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13624 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14766 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15908 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17050 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18192 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19334 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20809 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22284 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23759 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25234 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26709 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28184 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29659 }; assign left_tracks_in = { down_tracks_out[208], 1'h0, left_tracks_fwd[240], 1'h0, inputs_i[128], block_out[110], block_out[106], down_tracks_out[223], 1'h0, left_tracks_fwd[241], 1'h0, inputs_i[128], block_out[110], block_out[106], down_tracks_out[222], 1'h0, left_tracks_fwd[242], 1'h0, inputs_i[129], block_out[110], block_out[106], down_tracks_out[221], 1'h0, left_tracks_fwd[243], 1'h0, inputs_i[129], block_out[110], block_out[106], down_tracks_out[220], 1'h0, left_tracks_fwd[244], 1'h0, inputs_i[130], block_out[110], block_out[106], down_tracks_out[219], 1'h0, left_tracks_fwd[245], 1'h0, inputs_i[130], block_out[110], block_out[106], down_tracks_out[218], 1'h0, left_tracks_fwd[246], 1'h0, inputs_i[131], block_out[110], block_out[106], down_tracks_out[217], 1'h0, left_tracks_fwd[247], 1'h0, inputs_i[131], block_out[110], block_out[106], down_tracks_out[216], 1'h0, left_tracks_fwd[248], 1'h0, inputs_i[132], block_out[110], block_out[106], down_tracks_out[215], 1'h0, left_tracks_fwd[249], 1'h0, inputs_i[132], block_out[110], block_out[106], down_tracks_out[214], 1'h0, left_tracks_fwd[250], 1'h0, inputs_i[133], block_out[110], block_out[106], down_tracks_out[213], 1'h0, left_tracks_fwd[251], 1'h0, inputs_i[133], block_out[110], block_out[106], down_tracks_out[212], 1'h0, left_tracks_fwd[252], 1'h0, inputs_i[134], block_out[110], block_out[106], down_tracks_out[211], 1'h0, left_tracks_fwd[253], 1'h0, inputs_i[134], block_out[110], block_out[106], down_tracks_out[210], 1'h0, left_tracks_fwd[254], 1'h0, inputs_i[135], block_out[110], block_out[106], down_tracks_out[209], 1'h0, left_tracks_fwd[255], 1'h0, inputs_i[135], block_out[110], block_out[106], down_tracks_out[192], up_tracks_out[223], left_tracks_fwd[224], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[207], up_tracks_out[208], left_tracks_fwd[225], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[206], up_tracks_out[209], left_tracks_fwd[226], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[205], up_tracks_out[210], left_tracks_fwd[227], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[204], up_tracks_out[211], left_tracks_fwd[228], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[203], up_tracks_out[212], left_tracks_fwd[229], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[202], up_tracks_out[213], left_tracks_fwd[230], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[201], up_tracks_out[214], left_tracks_fwd[231], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[200], up_tracks_out[215], left_tracks_fwd[232], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[199], up_tracks_out[216], left_tracks_fwd[233], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[198], up_tracks_out[217], left_tracks_fwd[234], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[197], up_tracks_out[218], left_tracks_fwd[235], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[196], up_tracks_out[219], left_tracks_fwd[236], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[195], up_tracks_out[220], left_tracks_fwd[237], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[194], up_tracks_out[221], left_tracks_fwd[238], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[193], up_tracks_out[222], left_tracks_fwd[239], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[176], up_tracks_out[207], left_tracks_fwd[208], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[191], up_tracks_out[192], left_tracks_fwd[209], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[190], up_tracks_out[193], left_tracks_fwd[210], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[189], up_tracks_out[194], left_tracks_fwd[211], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[188], up_tracks_out[195], left_tracks_fwd[212], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[187], up_tracks_out[196], left_tracks_fwd[213], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[186], up_tracks_out[197], left_tracks_fwd[214], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[185], up_tracks_out[198], left_tracks_fwd[215], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[184], up_tracks_out[199], left_tracks_fwd[216], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[183], up_tracks_out[200], left_tracks_fwd[217], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[182], up_tracks_out[201], left_tracks_fwd[218], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[181], up_tracks_out[202], left_tracks_fwd[219], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[180], up_tracks_out[203], left_tracks_fwd[220], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[179], up_tracks_out[204], left_tracks_fwd[221], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[178], up_tracks_out[205], left_tracks_fwd[222], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[177], up_tracks_out[206], left_tracks_fwd[223], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[160], up_tracks_out[191], left_tracks_fwd[192], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[175], up_tracks_out[176], left_tracks_fwd[193], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[174], up_tracks_out[177], left_tracks_fwd[194], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[173], up_tracks_out[178], left_tracks_fwd[195], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[172], up_tracks_out[179], left_tracks_fwd[196], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[171], up_tracks_out[180], left_tracks_fwd[197], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[170], up_tracks_out[181], left_tracks_fwd[198], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[169], up_tracks_out[182], left_tracks_fwd[199], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[168], up_tracks_out[183], left_tracks_fwd[200], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[167], up_tracks_out[184], left_tracks_fwd[201], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[166], up_tracks_out[185], left_tracks_fwd[202], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[165], up_tracks_out[186], left_tracks_fwd[203], block_out[92], block_out[88], block_out[86], block_out[82], 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left_tracks_fwd[20], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[11], up_tracks_out[20], left_tracks_fwd[21], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[10], up_tracks_out[21], left_tracks_fwd[22], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[9], up_tracks_out[22], left_tracks_fwd[23], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[8], up_tracks_out[23], left_tracks_fwd[24], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[7], up_tracks_out[24], left_tracks_fwd[25], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[6], up_tracks_out[25], left_tracks_fwd[26], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[5], up_tracks_out[26], left_tracks_fwd[27], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[4], up_tracks_out[27], left_tracks_fwd[28], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[3], up_tracks_out[28], left_tracks_fwd[29], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[2], up_tracks_out[29], left_tracks_fwd[30], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[1], up_tracks_out[30], left_tracks_fwd[31], block_out[12], block_out[8], block_out[6], block_out[2], 1'h0, up_tracks_out[15], left_tracks_fwd[0], block_out[4], block_out[0], 1'h0, inputs_i[64], 1'h0, up_tracks_out[0], left_tracks_fwd[1], block_out[4], block_out[0], 1'h0, inputs_i[64], 1'h0, up_tracks_out[1], left_tracks_fwd[2], block_out[4], block_out[0], 1'h0, inputs_i[65], 1'h0, up_tracks_out[2], left_tracks_fwd[3], block_out[4], block_out[0], 1'h0, inputs_i[65], 1'h0, up_tracks_out[3], left_tracks_fwd[4], block_out[4], block_out[0], 1'h0, inputs_i[66], 1'h0, up_tracks_out[4], left_tracks_fwd[5], block_out[4], block_out[0], 1'h0, inputs_i[66], 1'h0, up_tracks_out[5], left_tracks_fwd[6], block_out[4], block_out[0], 1'h0, inputs_i[67], 1'h0, up_tracks_out[6], left_tracks_fwd[7], block_out[4], block_out[0], 1'h0, inputs_i[67], 1'h0, up_tracks_out[7], left_tracks_fwd[8], block_out[4], block_out[0], 1'h0, inputs_i[68], 1'h0, up_tracks_out[8], left_tracks_fwd[9], block_out[4], block_out[0], 1'h0, inputs_i[68], 1'h0, up_tracks_out[9], left_tracks_fwd[10], block_out[4], block_out[0], 1'h0, inputs_i[69], 1'h0, up_tracks_out[10], left_tracks_fwd[11], block_out[4], block_out[0], 1'h0, inputs_i[69], 1'h0, up_tracks_out[11], left_tracks_fwd[12], block_out[4], block_out[0], 1'h0, inputs_i[70], 1'h0, up_tracks_out[12], left_tracks_fwd[13], block_out[4], block_out[0], 1'h0, inputs_i[70], 1'h0, up_tracks_out[13], left_tracks_fwd[14], block_out[4], block_out[0], 1'h0, inputs_i[71], 1'h0, up_tracks_out[14], left_tracks_fwd[15], block_out[4], block_out[0], 1'h0, inputs_i[71] }; - assign left_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31083 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32225 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33367 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34509 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35651 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36793 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37935 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37957 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40888 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42030 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43172 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44314 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45456 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46598 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47740 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47762 }; + assign left_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31127 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32269 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33411 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34553 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35695 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36837 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37979 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:38001 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40932 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42074 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43216 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44358 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45500 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46642 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47784 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47806 }; assign right_tracks_in = { 1'h0, down_tracks_out[335], right_tracks_fwd[240], 1'h0, inputs_i[128], block_out[110], block_out[106], 1'h0, down_tracks_out[320], right_tracks_fwd[241], 1'h0, inputs_i[128], block_out[110], block_out[106], 1'h0, down_tracks_out[321], right_tracks_fwd[242], 1'h0, inputs_i[129], block_out[110], block_out[106], 1'h0, down_tracks_out[322], right_tracks_fwd[243], 1'h0, inputs_i[129], block_out[110], block_out[106], 1'h0, down_tracks_out[323], right_tracks_fwd[244], 1'h0, inputs_i[130], block_out[110], block_out[106], 1'h0, down_tracks_out[324], right_tracks_fwd[245], 1'h0, inputs_i[130], block_out[110], block_out[106], 1'h0, down_tracks_out[325], right_tracks_fwd[246], 1'h0, inputs_i[131], block_out[110], block_out[106], 1'h0, down_tracks_out[326], right_tracks_fwd[247], 1'h0, inputs_i[131], block_out[110], block_out[106], 1'h0, down_tracks_out[327], right_tracks_fwd[248], 1'h0, inputs_i[132], block_out[110], block_out[106], 1'h0, down_tracks_out[328], right_tracks_fwd[249], 1'h0, inputs_i[132], block_out[110], block_out[106], 1'h0, down_tracks_out[329], right_tracks_fwd[250], 1'h0, inputs_i[133], block_out[110], block_out[106], 1'h0, down_tracks_out[330], right_tracks_fwd[251], 1'h0, inputs_i[133], block_out[110], block_out[106], 1'h0, down_tracks_out[331], right_tracks_fwd[252], 1'h0, inputs_i[134], block_out[110], block_out[106], 1'h0, down_tracks_out[332], right_tracks_fwd[253], 1'h0, inputs_i[134], block_out[110], block_out[106], 1'h0, down_tracks_out[333], right_tracks_fwd[254], 1'h0, inputs_i[135], block_out[110], block_out[106], 1'h0, down_tracks_out[334], right_tracks_fwd[255], 1'h0, inputs_i[135], block_out[110], block_out[106], up_tracks_out[334], down_tracks_out[319], right_tracks_fwd[224], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[333], down_tracks_out[304], right_tracks_fwd[225], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[332], down_tracks_out[305], right_tracks_fwd[226], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[331], down_tracks_out[306], right_tracks_fwd[227], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[330], down_tracks_out[307], right_tracks_fwd[228], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[329], down_tracks_out[308], right_tracks_fwd[229], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[328], down_tracks_out[309], right_tracks_fwd[230], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[327], down_tracks_out[310], right_tracks_fwd[231], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[326], down_tracks_out[311], right_tracks_fwd[232], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[325], down_tracks_out[312], right_tracks_fwd[233], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[324], down_tracks_out[313], right_tracks_fwd[234], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[323], down_tracks_out[314], right_tracks_fwd[235], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[322], down_tracks_out[315], right_tracks_fwd[236], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[321], down_tracks_out[316], right_tracks_fwd[237], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[320], down_tracks_out[317], right_tracks_fwd[238], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[335], down_tracks_out[318], right_tracks_fwd[239], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[318], down_tracks_out[303], right_tracks_fwd[208], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[317], down_tracks_out[288], right_tracks_fwd[209], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[316], down_tracks_out[289], right_tracks_fwd[210], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[315], down_tracks_out[290], right_tracks_fwd[211], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[314], down_tracks_out[291], right_tracks_fwd[212], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[313], down_tracks_out[292], right_tracks_fwd[213], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[312], down_tracks_out[293], right_tracks_fwd[214], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[311], down_tracks_out[294], right_tracks_fwd[215], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[310], down_tracks_out[295], right_tracks_fwd[216], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[309], down_tracks_out[296], right_tracks_fwd[217], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[308], down_tracks_out[297], right_tracks_fwd[218], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[307], down_tracks_out[298], right_tracks_fwd[219], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[306], down_tracks_out[299], right_tracks_fwd[220], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[305], down_tracks_out[300], right_tracks_fwd[221], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[304], down_tracks_out[301], right_tracks_fwd[222], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[319], down_tracks_out[302], right_tracks_fwd[223], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[302], down_tracks_out[287], right_tracks_fwd[192], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[301], down_tracks_out[272], right_tracks_fwd[193], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[300], down_tracks_out[273], right_tracks_fwd[194], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[299], down_tracks_out[274], right_tracks_fwd[195], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[298], down_tracks_out[275], right_tracks_fwd[196], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[297], down_tracks_out[276], right_tracks_fwd[197], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[296], down_tracks_out[277], right_tracks_fwd[198], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[295], down_tracks_out[278], right_tracks_fwd[199], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[294], down_tracks_out[279], right_tracks_fwd[200], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[293], down_tracks_out[280], right_tracks_fwd[201], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[292], down_tracks_out[281], right_tracks_fwd[202], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[291], down_tracks_out[282], right_tracks_fwd[203], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[290], down_tracks_out[283], right_tracks_fwd[204], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[289], down_tracks_out[284], right_tracks_fwd[205], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[288], down_tracks_out[285], right_tracks_fwd[206], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[303], down_tracks_out[286], right_tracks_fwd[207], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[286], down_tracks_out[271], right_tracks_fwd[176], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[285], down_tracks_out[256], right_tracks_fwd[177], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[284], down_tracks_out[257], right_tracks_fwd[178], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[283], down_tracks_out[258], right_tracks_fwd[179], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[282], down_tracks_out[259], right_tracks_fwd[180], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[281], down_tracks_out[260], right_tracks_fwd[181], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[280], down_tracks_out[261], right_tracks_fwd[182], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[279], down_tracks_out[262], right_tracks_fwd[183], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[278], down_tracks_out[263], right_tracks_fwd[184], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[277], down_tracks_out[264], right_tracks_fwd[185], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[276], down_tracks_out[265], right_tracks_fwd[186], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[275], down_tracks_out[266], right_tracks_fwd[187], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[274], down_tracks_out[267], right_tracks_fwd[188], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[273], down_tracks_out[268], right_tracks_fwd[189], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[272], down_tracks_out[269], right_tracks_fwd[190], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[287], down_tracks_out[270], right_tracks_fwd[191], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[270], down_tracks_out[255], right_tracks_fwd[160], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[269], down_tracks_out[240], right_tracks_fwd[161], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[268], down_tracks_out[241], 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block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[133], down_tracks_out[120], right_tracks_fwd[25], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[132], down_tracks_out[121], right_tracks_fwd[26], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[131], down_tracks_out[122], right_tracks_fwd[27], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[130], down_tracks_out[123], right_tracks_fwd[28], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[129], down_tracks_out[124], right_tracks_fwd[29], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[128], down_tracks_out[125], right_tracks_fwd[30], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[143], down_tracks_out[126], right_tracks_fwd[31], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[126], 1'h0, right_tracks_fwd[0], block_out[4], block_out[0], 1'h0, inputs_i[64], up_tracks_out[125], 1'h0, right_tracks_fwd[1], block_out[4], block_out[0], 1'h0, inputs_i[64], up_tracks_out[124], 1'h0, right_tracks_fwd[2], block_out[4], block_out[0], 1'h0, inputs_i[65], up_tracks_out[123], 1'h0, right_tracks_fwd[3], block_out[4], block_out[0], 1'h0, inputs_i[65], up_tracks_out[122], 1'h0, right_tracks_fwd[4], block_out[4], block_out[0], 1'h0, inputs_i[66], up_tracks_out[121], 1'h0, right_tracks_fwd[5], block_out[4], block_out[0], 1'h0, inputs_i[66], up_tracks_out[120], 1'h0, right_tracks_fwd[6], block_out[4], block_out[0], 1'h0, inputs_i[67], up_tracks_out[119], 1'h0, right_tracks_fwd[7], block_out[4], block_out[0], 1'h0, inputs_i[67], up_tracks_out[118], 1'h0, right_tracks_fwd[8], block_out[4], block_out[0], 1'h0, inputs_i[68], up_tracks_out[117], 1'h0, right_tracks_fwd[9], block_out[4], block_out[0], 1'h0, inputs_i[68], up_tracks_out[116], 1'h0, right_tracks_fwd[10], block_out[4], block_out[0], 1'h0, inputs_i[69], up_tracks_out[115], 1'h0, right_tracks_fwd[11], block_out[4], block_out[0], 1'h0, inputs_i[69], up_tracks_out[114], 1'h0, right_tracks_fwd[12], block_out[4], block_out[0], 1'h0, inputs_i[70], up_tracks_out[113], 1'h0, right_tracks_fwd[13], block_out[4], block_out[0], 1'h0, inputs_i[70], up_tracks_out[112], 1'h0, right_tracks_fwd[14], block_out[4], block_out[0], 1'h0, inputs_i[71], up_tracks_out[127], 1'h0, right_tracks_fwd[15], block_out[4], block_out[0], 1'h0, inputs_i[71] }; - assign right_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31093 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32235 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33377 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34519 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35661 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36803 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37945 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39420 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40898 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42040 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43182 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44324 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45466 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46608 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47750 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49225 }; + assign right_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31137 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32279 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33421 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34563 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35705 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36847 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37989 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39464 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40942 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42084 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43226 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44368 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45510 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46652 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47794 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49269 }; assign up_tracks_fwd = { 16'h0000, up_tracks_out[335:240], 16'h0000, up_tracks_out[223:128], 16'h0000, up_tracks_out[111:16] }; assign down_tracks_fwd = { down_tracks_out[319:224], 16'h0000, down_tracks_out[207:112], 16'h0000, down_tracks_out[95:0], 16'h0000 }; assign left_tracks_fwd = { left_tracks_out[127:0], 128'h00000000000000000000000000000000 }; assign right_tracks_fwd = { 128'h00000000000000000000000000000000, right_tracks_out[255:128] }; - assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2416 = _031_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2418 = _032_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2426 = _033_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2428 = _034_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3894 = _037_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3896 = _038_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3904 = _039_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3906 = _040_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5372 = _043_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5374 = _044_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5382 = _045_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5384 = _046_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6850 = _049_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6852 = _050_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6860 = _051_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6862 = _052_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8328 = _055_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8330 = _056_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8338 = _057_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8340 = _058_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9806 = _061_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9808 = _062_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9816 = _063_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9818 = _064_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11284 = _067_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11286 = _068_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11294 = _069_; - assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11296 = _070_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12426 = _071_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12428 = _072_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12436 = _073_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12438 = _074_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13568 = _075_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13570 = _076_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13578 = _077_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13580 = _078_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14710 = _079_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14712 = _080_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14720 = _081_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14722 = _082_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15852 = _083_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15854 = _084_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15862 = _085_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15864 = _086_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16994 = _087_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16996 = _088_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17004 = _089_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17006 = _090_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18136 = _091_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18138 = _092_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18146 = _093_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18148 = _094_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19278 = _095_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19280 = _096_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19288 = _097_; - assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19290 = _098_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19300 = _099_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19302 = _100_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20763 = _103_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20765 = _104_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20775 = _105_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20777 = _106_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22238 = _109_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22240 = _110_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22250 = _111_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22252 = _112_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23713 = _115_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23715 = _116_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23725 = _117_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23727 = _118_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25188 = _121_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25190 = _122_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25200 = _123_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25202 = _124_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26663 = _127_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26665 = _128_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26675 = _129_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26677 = _130_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28138 = _133_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28140 = _134_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28150 = _135_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28152 = _136_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29613 = _139_; - assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29615 = _140_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31081 = _143_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31083 = _144_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31091 = _145_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31093 = _146_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32223 = _147_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32225 = _148_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32233 = _149_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32235 = _150_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33365 = _151_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33367 = _152_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33375 = _153_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33377 = _154_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34507 = _155_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34509 = _156_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34517 = _157_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34519 = _158_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35649 = _159_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35651 = _160_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35659 = _161_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35661 = _162_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36791 = _163_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36793 = _164_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36801 = _165_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36803 = _166_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37933 = _167_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37935 = _168_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37943 = _169_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37945 = _170_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37955 = _171_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37957 = _172_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39418 = _175_; - assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39420 = _176_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40886 = _179_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40888 = _180_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40896 = _181_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40898 = _182_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42028 = _183_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42030 = _184_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42038 = _185_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42040 = _186_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43170 = _187_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43172 = _188_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43180 = _189_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43182 = _190_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44312 = _191_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44314 = _192_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44322 = _193_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44324 = _194_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45454 = _195_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45456 = _196_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45464 = _197_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45466 = _198_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46596 = _199_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46598 = _200_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46606 = _201_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46608 = _202_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47738 = _203_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47740 = _204_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47748 = _205_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47750 = _206_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47760 = _207_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47762 = _208_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49223 = _211_; - assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49225 = _212_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2460 = _031_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2462 = _032_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2470 = _033_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2472 = _034_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3938 = _037_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3940 = _038_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3948 = _039_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3950 = _040_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5416 = _043_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5418 = _044_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5426 = _045_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5428 = _046_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6894 = _049_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6896 = _050_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6904 = _051_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6906 = _052_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8372 = _055_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8374 = _056_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8382 = _057_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8384 = _058_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9850 = _061_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9852 = _062_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9860 = _063_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9862 = _064_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11328 = _067_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11330 = _068_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11338 = _069_; + assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11340 = _070_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12470 = _071_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12472 = _072_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12480 = _073_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12482 = _074_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13612 = _075_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13614 = _076_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13622 = _077_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13624 = _078_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14754 = _079_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14756 = _080_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14764 = _081_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14766 = _082_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15896 = _083_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15898 = _084_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15906 = _085_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15908 = _086_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17038 = _087_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17040 = _088_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17048 = _089_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17050 = _090_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18180 = _091_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18182 = _092_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18190 = _093_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18192 = _094_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19322 = _095_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19324 = _096_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19332 = _097_; + assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19334 = _098_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19344 = _099_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19346 = _100_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20807 = _103_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20809 = _104_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20819 = _105_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20821 = _106_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22282 = _109_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22284 = _110_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22294 = _111_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22296 = _112_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23757 = _115_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23759 = _116_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23769 = _117_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23771 = _118_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25232 = _121_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25234 = _122_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25244 = _123_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25246 = _124_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26707 = _127_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26709 = _128_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26719 = _129_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26721 = _130_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28182 = _133_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28184 = _134_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28194 = _135_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28196 = _136_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29657 = _139_; + assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29659 = _140_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31125 = _143_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31127 = _144_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31135 = _145_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31137 = _146_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32267 = _147_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32269 = _148_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32277 = _149_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32279 = _150_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33409 = _151_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33411 = _152_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33419 = _153_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33421 = _154_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34551 = _155_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34553 = _156_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34561 = _157_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34563 = _158_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35693 = _159_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35695 = _160_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35703 = _161_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35705 = _162_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36835 = _163_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36837 = _164_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36845 = _165_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36847 = _166_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37977 = _167_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37979 = _168_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37987 = _169_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37989 = _170_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37999 = _171_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:38001 = _172_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39462 = _175_; + assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39464 = _176_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40930 = _179_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40932 = _180_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40940 = _181_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40942 = _182_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42072 = _183_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42074 = _184_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42082 = _185_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42084 = _186_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43214 = _187_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43216 = _188_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43224 = _189_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43226 = _190_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44356 = _191_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44358 = _192_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44366 = _193_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44368 = _194_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45498 = _195_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45500 = _196_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45508 = _197_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45510 = _198_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46640 = _199_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46642 = _200_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46650 = _201_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46652 = _202_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47782 = _203_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47784 = _204_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47792 = _205_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47794 = _206_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47804 = _207_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47806 = _208_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49267 = _211_; + assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49269 = _212_; assign config_block_o = { block_cfg_shift_chain[0], block_cfg_shift_chain[8] }; assign config_vrnode_o = { vrnode_cfg_shift_chain[8], vrnode_cfg_shift_chain[17], vrnode_cfg_shift_chain[26], vrnode_cfg_shift_chain[35], vrnode_cfg_shift_chain[44], vrnode_cfg_shift_chain[53], vrnode_cfg_shift_chain[62] }; assign config_hrnode_o = { hrnode_cfg_shift_chain[18], hrnode_cfg_shift_chain[37] }; @@ -2882,7 +2882,7 @@ wire config_shift_i; output config_shift_o; wire config_shift_o; - wire [15:0] \node:49485 ; + wire [15:0] \node:49529 ; input [111:0] route_i; wire [111:0] route_i; output [15:0] route_o; @@ -2901,99 +2901,109 @@ ); assign config_data = _2_; assign config_data_gated = config_data; - assign \node:49485 = _0_; + assign \node:49529 = _0_; assign config_shift_o = _1_; - assign route_o = \node:49485 ; + assign route_o = \node:49529 ; endmodule -module wb_arbiter_sync_6(wb_clk_i, wb_rst_i, \wb_i_up.stb_i , \wb_i_up.cyc_i , \wb_i_up.we_i , \wb_i_up.dat_i , \wb_i_up.adr_i , addr_map, wb_i_bottom, \wb_o_up.ack_o , \wb_o_up.dat_o , wb_o_bottom); +module wb_arbiter_sync_7(wb_clk_i, wb_rst_i, \wb_i_up.stb_i , \wb_i_up.cyc_i , \wb_i_up.we_i , \wb_i_up.dat_i , \wb_i_up.adr_i , addr_map, wb_i_bottom, \wb_o_up.ack_o , \wb_o_up.dat_o , wb_o_bottom); wire [32:0] _00_; wire [32:0] _01_; wire [32:0] _02_; wire [32:0] _03_; - wire [66:0] _04_; - wire [66:0] _05_; - wire [66:0] _06_; - wire [66:0] _07_; - wire [32:0] _08_; - wire [32:0] _09_; - wire [32:0] _10_; - wire _11_; - wire _12_; - wire _13_; - wire _14_; - wire [2:0] _15_; - wire _16_; - wire [2:0] _17_; - wire _18_; - wire [2:0] _19_; - wire _20_; - wire [2:0] _21_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire [66:0] _10_; + wire [66:0] _11_; + wire [66:0] _12_; + wire [66:0] _13_; + wire [66:0] _14_; + wire [66:0] _15_; + wire [66:0] _16_; + wire [32:0] _17_; + wire [32:0] _18_; + wire [32:0] _19_; + wire [32:0] _20_; + wire _21_; wire _22_; - wire [2:0] _23_; + wire _23_; wire _24_; wire [2:0] _25_; - wire [401:0] _26_; - wire _27_; - wire [2:0] _28_; - wire _29_; - wire [32:0] _30_; - wire [401:0] _31_; + wire _26_; + wire [2:0] _27_; + wire _28_; + wire [2:0] _29_; + wire _30_; + wire [2:0] _31_; wire _32_; - wire _33_; - wire [32:0] _34_; - wire [401:0] _35_; + wire [2:0] _33_; + wire _34_; + wire [2:0] _35_; wire _36_; wire [2:0] _37_; - wire _38_; - wire [2:0] _39_; - reg [2:0] _40_ = 3'h0; - reg _41_; - reg [32:0] _42_; - reg [401:0] _43_; + wire [468:0] _38_; + wire _39_; + wire [2:0] _40_; + wire _41_; + wire [32:0] _42_; + wire [468:0] _43_; wire _44_; wire _45_; - wire _46_; - wire _47_; + wire [32:0] _46_; + wire [468:0] _47_; wire _48_; - wire _49_; + wire [2:0] _49_; wire _50_; - wire _51_; - wire _52_; - wire _53_; - wire _54_; - wire _55_; - wire [66:0] _56_; - wire [66:0] _57_; - wire [66:0] _58_; - wire [66:0] _59_; - wire [66:0] _60_; - wire [66:0] _61_; - wire [32:0] _62_; - wire [32:0] _63_; - wire [32:0] _64_; + wire [2:0] _51_; + reg [2:0] _52_ = 3'h0; + reg _53_; + reg [32:0] _54_; + reg [468:0] _55_; + wire _56_; + wire _57_; + wire _58_; + wire _59_; + wire _60_; + wire _61_; + wire _62_; + wire _63_; + wire _64_; wire _65_; wire _66_; wire _67_; wire _68_; wire _69_; - wire _70_; - wire _71_; - wire _72_; - wire _73_; - wire _74_; - wire _75_; - wire _76_; - wire [66:0] _77_; - wire [66:0] _78_; - input [191:0] addr_map; - wire [191:0] addr_map; + wire [66:0] _70_; + wire [66:0] _71_; + wire [66:0] _72_; + wire [66:0] _73_; + wire [66:0] _74_; + wire [66:0] _75_; + wire [66:0] _76_; + wire [32:0] _77_; + wire [32:0] _78_; + wire [32:0] _79_; + wire [32:0] _80_; + wire _81_; + wire _82_; + wire _83_; + wire _84_; + wire _85_; + wire _86_; + wire _87_; + wire _88_; + input [223:0] addr_map; + wire [223:0] addr_map; wire state; wire [2:0] \sync.pn_buf ; input wb_clk_i; wire wb_clk_i; - input [197:0] wb_i_bottom; - wire [197:0] wb_i_bottom; + input [230:0] wb_i_bottom; + wire [230:0] wb_i_bottom; input [31:0] \wb_i_up.adr_i ; wire [31:0] \wb_i_up.adr_i ; input \wb_i_up.cyc_i ; @@ -3004,8 +3014,8 @@ wire \wb_i_up.stb_i ; input \wb_i_up.we_i ; wire \wb_i_up.we_i ; - output [401:0] wb_o_bottom; - wire [401:0] wb_o_bottom; + output [468:0] wb_o_bottom; + wire [468:0] wb_o_bottom; output \wb_o_up.ack_o ; wire \wb_o_up.ack_o ; output [31:0] \wb_o_up.dat_o ; @@ -3016,149 +3026,159 @@ assign _01_ = \sync.pn_buf [0] ? wb_i_bottom[65:33] : wb_i_bottom[32:0]; assign _02_ = \sync.pn_buf [0] ? wb_i_bottom[131:99] : wb_i_bottom[98:66]; assign _03_ = \sync.pn_buf [0] ? wb_i_bottom[131:99] : wb_i_bottom[98:66]; - assign _62_ = \sync.pn_buf [1] ? _02_ : _00_; - assign _08_ = \sync.pn_buf [1] ? _03_ : _01_; - assign _11_ = \wb_i_up.cyc_i & \wb_i_up.stb_i ; - assign _12_ = ~ _42_[0]; - assign _13_ = _11_ & _12_; - assign _14_ = \wb_i_up.adr_i >= addr_map[31:0]; - assign _15_ = _14_ ? 3'h0 : \sync.pn_buf ; - assign _16_ = \wb_i_up.adr_i >= addr_map[63:32]; - assign _17_ = _16_ ? 3'h1 : _15_; - assign _18_ = \wb_i_up.adr_i >= addr_map[95:64]; - assign _19_ = _18_ ? 3'h2 : _17_; - assign _20_ = \wb_i_up.adr_i >= addr_map[127:96]; - assign _21_ = _20_ ? 3'h3 : _19_; - assign _22_ = \wb_i_up.adr_i >= addr_map[159:128]; - assign _23_ = _22_ ? 3'h4 : _21_; - assign _24_ = \wb_i_up.adr_i >= addr_map[191:160]; - assign _25_ = _24_ ? 3'h5 : _23_; - assign _26_ = _13_ ? { _61_, _60_, _59_, _58_, _57_, _56_ } : _43_; - assign _27_ = _13_ ? 1'h1 : state; - assign _28_ = _13_ ? _25_ : \sync.pn_buf ; - assign _29_ = state == 1'h0; - assign _30_ = _64_[0] ? { _10_[32:1], 1'h1 } : _42_; - assign _31_ = _64_[0] ? { _07_, _06_, _05_, _04_, _78_, _77_ } : _43_; - assign _32_ = _64_[0] ? 1'h0 : state; - assign _33_ = state == 1'h1; - function [32:0] \594 ; + assign _77_ = \sync.pn_buf [1] ? _02_ : _00_; + assign _17_ = \sync.pn_buf [1] ? _03_ : _01_; + assign _21_ = \wb_i_up.cyc_i & \wb_i_up.stb_i ; + assign _22_ = ~ _54_[0]; + assign _23_ = _21_ & _22_; + assign _24_ = \wb_i_up.adr_i >= addr_map[31:0]; + assign _25_ = _24_ ? 3'h0 : \sync.pn_buf ; + assign _26_ = \wb_i_up.adr_i >= addr_map[63:32]; + assign _27_ = _26_ ? 3'h1 : _25_; + assign _28_ = \wb_i_up.adr_i >= addr_map[95:64]; + assign _29_ = _28_ ? 3'h2 : _27_; + assign _30_ = \wb_i_up.adr_i >= addr_map[127:96]; + assign _31_ = _30_ ? 3'h3 : _29_; + assign _32_ = \wb_i_up.adr_i >= addr_map[159:128]; + assign _33_ = _32_ ? 3'h4 : _31_; + assign _34_ = \wb_i_up.adr_i >= addr_map[191:160]; + assign _35_ = _34_ ? 3'h5 : _33_; + assign _36_ = \wb_i_up.adr_i >= addr_map[223:192]; + assign _37_ = _36_ ? 3'h6 : _35_; + assign _38_ = _23_ ? { _76_, _75_, _74_, _73_, _72_, _71_, _70_ } : _55_; + assign _39_ = _23_ ? 1'h1 : state; + assign _40_ = _23_ ? _37_ : \sync.pn_buf ; + assign _41_ = state == 1'h0; + assign _42_ = _80_[0] ? { _20_[32:1], 1'h1 } : _54_; + assign _43_ = _80_[0] ? { _16_, _15_, _14_, _13_, _12_, _11_, _10_ } : _55_; + assign _44_ = _80_[0] ? 1'h0 : state; + assign _45_ = state == 1'h1; + function [32:0] \624 ; input [32:0] a; input [65:0] b; input [1:0] s; (* parallel_case *) casez (s) 2'b?1: - \594 = b[32:0]; + \624 = b[32:0]; 2'b1?: - \594 = b[65:33]; + \624 = b[65:33]; default: - \594 = a; + \624 = a; endcase endfunction - assign _34_ = \594 (33'hxxxxxxxxx, { _30_, 33'h000000000 }, { _33_, _29_ }); - function [401:0] \596 ; - input [401:0] a; - input [803:0] b; + assign _46_ = \624 (33'hxxxxxxxxx, { _42_, 33'h000000000 }, { _45_, _41_ }); + function [468:0] \626 ; + input [468:0] a; + input [937:0] b; input [1:0] s; (* parallel_case *) casez (s) 2'b?1: - \596 = b[401:0]; + \626 = b[468:0]; 2'b1?: - \596 = b[803:402]; + \626 = b[937:469]; default: - \596 = a; + \626 = a; endcase endfunction - assign _35_ = \596 (402'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _31_, _26_ }, { _33_, _29_ }); - function [0:0] \598 ; + assign _47_ = \626 (469'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _43_, _38_ }, { _45_, _41_ }); + function [0:0] \628 ; input [0:0] a; input [1:0] b; input [1:0] s; (* parallel_case *) casez (s) 2'b?1: - \598 = b[0:0]; + \628 = b[0:0]; 2'b1?: - \598 = b[1:1]; + \628 = b[1:1]; default: - \598 = a; + \628 = a; endcase endfunction - assign _36_ = \598 (1'hx, { _32_, _27_ }, { _33_, _29_ }); - function [2:0] \602 ; + assign _48_ = \628 (1'hx, { _44_, _39_ }, { _45_, _41_ }); + function [2:0] \632 ; input [2:0] a; input [5:0] b; input [1:0] s; (* parallel_case *) casez (s) 2'b?1: - \602 = b[2:0]; + \632 = b[2:0]; 2'b1?: - \602 = b[5:3]; + \632 = b[5:3]; default: - \602 = a; + \632 = a; endcase endfunction - assign _37_ = \602 (3'hx, { \sync.pn_buf , _28_ }, { _33_, _29_ }); - assign _38_ = ~ wb_rst_i; - assign _39_ = _38_ ? _37_ : \sync.pn_buf ; + assign _49_ = \632 (3'hx, { \sync.pn_buf , _40_ }, { _45_, _41_ }); + assign _50_ = ~ wb_rst_i; + assign _51_ = _50_ ? _49_ : \sync.pn_buf ; always @(posedge wb_clk_i) - _40_ <= _39_; + _52_ <= _51_; always @(posedge wb_clk_i, posedge wb_rst_i) - if (wb_rst_i) _41_ <= 1'h0; - else _41_ <= _36_; + if (wb_rst_i) _53_ <= 1'h0; + else _53_ <= _48_; always @(posedge wb_clk_i, posedge wb_rst_i) - if (wb_rst_i) _42_ <= 33'h000000000; - else _42_ <= _34_; + if (wb_rst_i) _54_ <= 33'h000000000; + else _54_ <= _46_; always @(posedge wb_clk_i, posedge wb_rst_i) - if (wb_rst_i) _43_ <= 402'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - else _43_ <= _35_; - assign _44_ = ~ _25_[2]; - assign _45_ = ~ _25_[1]; - assign _46_ = _44_ & _45_; - assign _47_ = _44_ & _25_[1]; - assign _48_ = _25_[2] & _45_; - assign _49_ = ~ _25_[0]; - assign _50_ = _46_ & _49_; - assign _51_ = _46_ & _25_[0]; - assign _52_ = _47_ & _49_; - assign _53_ = _47_ & _25_[0]; - assign _54_ = _48_ & _49_; - assign _55_ = _48_ & _25_[0]; - assign _56_ = _50_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[66:0]; - assign _57_ = _51_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[133:67]; - assign _58_ = _52_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[200:134]; - assign _59_ = _53_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[267:201]; - assign _60_ = _54_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[334:268]; - assign _61_ = _55_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[401:335]; - assign _63_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132]; - assign _64_ = \sync.pn_buf [2] ? _63_ : _62_; - assign _65_ = ~ \sync.pn_buf [2]; - assign _66_ = ~ \sync.pn_buf [1]; - assign _67_ = _65_ & _66_; - assign _68_ = _65_ & \sync.pn_buf [1]; - assign _69_ = \sync.pn_buf [2] & _66_; - assign _70_ = ~ \sync.pn_buf [0]; - assign _71_ = _67_ & _70_; - assign _72_ = _67_ & \sync.pn_buf [0]; - assign _73_ = _68_ & _70_; - assign _74_ = _68_ & \sync.pn_buf [0]; - assign _75_ = _69_ & _70_; - assign _76_ = _69_ & \sync.pn_buf [0]; - assign _77_ = _71_ ? 67'h00000000000000000 : _43_[66:0]; - assign _78_ = _72_ ? 67'h00000000000000000 : _43_[133:67]; - assign _04_ = _73_ ? 67'h00000000000000000 : _43_[200:134]; - assign _05_ = _74_ ? 67'h00000000000000000 : _43_[267:201]; - assign _06_ = _75_ ? 67'h00000000000000000 : _43_[334:268]; - assign _07_ = _76_ ? 67'h00000000000000000 : _43_[401:335]; - assign _09_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132]; - assign _10_ = \sync.pn_buf [2] ? _09_ : _08_; - assign state = _41_; - assign \sync.pn_buf = _40_; - assign \wb_o_up.ack_o = _42_[0]; - assign \wb_o_up.dat_o = _42_[32:1]; - assign wb_o_bottom = _43_; + if (wb_rst_i) _55_ <= 469'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + else _55_ <= _47_; + assign _56_ = ~ _37_[2]; + assign _57_ = ~ _37_[1]; + assign _58_ = _56_ & _57_; + assign _59_ = _56_ & _37_[1]; + assign _60_ = _37_[2] & _57_; + assign _61_ = _37_[2] & _37_[1]; + assign _62_ = ~ _37_[0]; + assign _63_ = _58_ & _62_; + assign _64_ = _58_ & _37_[0]; + assign _65_ = _59_ & _62_; + assign _66_ = _59_ & _37_[0]; + assign _67_ = _60_ & _62_; + assign _68_ = _60_ & _37_[0]; + assign _69_ = _61_ & _62_; + assign _70_ = _63_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[66:0]; + assign _71_ = _64_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[133:67]; + assign _72_ = _65_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[200:134]; + assign _73_ = _66_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[267:201]; + assign _74_ = _67_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[334:268]; + assign _75_ = _68_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[401:335]; + assign _76_ = _69_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[468:402]; + assign _78_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132]; + assign _79_ = \sync.pn_buf [1] ? wb_i_bottom[230:198] : _78_; + assign _80_ = \sync.pn_buf [2] ? _79_ : _77_; + assign _81_ = ~ \sync.pn_buf [2]; + assign _82_ = ~ \sync.pn_buf [1]; + assign _83_ = _81_ & _82_; + assign _84_ = _81_ & \sync.pn_buf [1]; + assign _85_ = \sync.pn_buf [2] & _82_; + assign _86_ = \sync.pn_buf [2] & \sync.pn_buf [1]; + assign _87_ = ~ \sync.pn_buf [0]; + assign _88_ = _83_ & _87_; + assign _04_ = _83_ & \sync.pn_buf [0]; + assign _05_ = _84_ & _87_; + assign _06_ = _84_ & \sync.pn_buf [0]; + assign _07_ = _85_ & _87_; + assign _08_ = _85_ & \sync.pn_buf [0]; + assign _09_ = _86_ & _87_; + assign _10_ = _88_ ? 67'h00000000000000000 : _55_[66:0]; + assign _11_ = _04_ ? 67'h00000000000000000 : _55_[133:67]; + assign _12_ = _05_ ? 67'h00000000000000000 : _55_[200:134]; + assign _13_ = _06_ ? 67'h00000000000000000 : _55_[267:201]; + assign _14_ = _07_ ? 67'h00000000000000000 : _55_[334:268]; + assign _15_ = _08_ ? 67'h00000000000000000 : _55_[401:335]; + assign _16_ = _09_ ? 67'h00000000000000000 : _55_[468:402]; + assign _18_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132]; + assign _19_ = \sync.pn_buf [1] ? wb_i_bottom[230:198] : _18_; + assign _20_ = \sync.pn_buf [2] ? _19_ : _17_; + assign state = _53_; + assign \sync.pn_buf = _52_; + assign \wb_o_up.ack_o = _54_[0]; + assign \wb_o_up.dat_o = _54_[32:1]; + assign wb_o_bottom = _55_; endmodule module wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o);
diff --git a/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v b/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v index 8f5e281..d59b678 100644 --- a/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v +++ b/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
@@ -351,6 +351,7 @@ wire _5_; wire _6_; wire _7_; + wire _8_; input clk_i; wire clk_i; input [15:0] \config_i.lut_config ; @@ -367,7 +368,8 @@ wire lut_out; wire register_out; assign _6_ = ~ \config_i.mux_config ; - assign _7_ = _6_ ? lut_out : register_out; + assign _7_ = _6_ & glb_rstn_i; + assign _8_ = _7_ ? lut_out : register_out; fpga_tech_register cell_reg ( .clk_i(clk_i), .config_i_rst_polarity(1'h0), @@ -401,7 +403,7 @@ assign lut_out = _4_; assign register_out = _5_; assign logic_in_buf = { _3_, _2_, _1_, _0_ }; - assign logic_o = _7_; + assign logic_o = _8_; endmodule module fpga_lut_1(glb_rstn_i, config_i, logic_i, logic_o);
diff --git a/verilog/rtl/fpga_struct_block/fpga_tech.v b/verilog/rtl/fpga_struct_block/fpga_tech.v index 276d1c6..d57ae7c 100644 --- a/verilog/rtl/fpga_struct_block/fpga_tech.v +++ b/verilog/rtl/fpga_struct_block/fpga_tech.v
@@ -45,8 +45,33 @@ module fpga_tech_clkbuffer (input i, output z); - + wire buf_X; + assign z = buf_X; + gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 tech_buf ( .I(i), .Z(buf_X)); endmodule + + +module efuse_ctrl (wb_ack_o, + wb_clk_i, + wb_cyc_i, + wb_rst_i, + wb_sel_i, + wb_stb_i, + wb_we_i, + wb_adr_i, + wb_dat_i, + wb_dat_o); + output wb_ack_o; + input wb_clk_i; + input wb_cyc_i; + input wb_rst_i; + input wb_sel_i; + input wb_stb_i; + input wb_we_i; + input [10:0] wb_adr_i; + input [7:0] wb_dat_i; + output [7:0] wb_dat_o; +endmodule
diff --git a/verilog/rtl/fpga_tech.v b/verilog/rtl/fpga_tech.v index c9031e2..d57ae7c 100644 --- a/verilog/rtl/fpga_tech.v +++ b/verilog/rtl/fpga_tech.v
@@ -45,7 +45,9 @@ module fpga_tech_clkbuffer (input i, output z); - + wire buf_X; + assign z = buf_X; + gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 tech_buf ( .I(i), .Z(buf_X)); @@ -69,7 +71,7 @@ input wb_sel_i; input wb_stb_i; input wb_we_i; - input [9:0] wb_adr_i; + input [10:0] wb_adr_i; input [7:0] wb_dat_i; output [7:0] wb_dat_o; endmodule