| /* Generated by Yosys 0.22 (git sha1 f109fa3d4, gcc 10.2.1-6 -fPIC -Os) */ |
| |
| (* top = 1 *) |
| module ariel_fpga_top(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_dat_i, wbs_adr_i, la_data_in, la_oenb, io_in, user_clock2, wbs_ack_o, wbs_dat_o, la_data_out, io_out, io_oeb, user_irq); |
| wire _00_; |
| wire [31:0] _01_; |
| wire _02_; |
| wire [31:0] _03_; |
| wire [31:0] _04_; |
| wire _05_; |
| wire [31:0] _06_; |
| wire [31:0] _07_; |
| wire _08_; |
| wire [31:0] _09_; |
| wire [31:0] _10_; |
| wire [31:0] _11_; |
| wire _12_; |
| wire [31:0] _13_; |
| wire [31:0] _14_; |
| wire [7:0] _15_; |
| wire _16_; |
| wire _17_; |
| wire _18_; |
| wire _19_; |
| wire _20_; |
| wire [143:0] _21_; |
| wire [468:0] _22_; |
| wire _23_; |
| wire [143:0] _24_; |
| wire [1:0] _25_; |
| wire [6:0] _26_; |
| wire [1:0] _27_; |
| wire [143:0] _28_; |
| wire _29_; |
| wire [31:0] _30_; |
| wire [31:0] block_data; |
| wire [31:0] block_data_out; |
| wire config_block_clk; |
| wire [3:0] config_block_i; |
| wire [1:0] config_block_o; |
| wire config_hrnode_clk; |
| wire [3:0] config_hrnode_i; |
| wire [1:0] config_hrnode_o; |
| wire config_vrnode_clk; |
| wire [13:0] config_vrnode_i; |
| wire [6:0] config_vrnode_o; |
| wire [31:0] fpga_rst; |
| wire [31:0] fw_tap_bus; |
| wire [31:0] hrnode_data; |
| wire [31:0] hrnode_data_out; |
| wire [143:0] inputs_i; |
| wire [143:0] inputs_i_buf; |
| input [37:0] io_in; |
| wire [37:0] io_in; |
| output [37:0] io_oeb; |
| wire [37:0] io_oeb; |
| output [37:0] io_out; |
| wire [37:0] io_out; |
| input [63:0] la_data_in; |
| wire [63:0] la_data_in; |
| output [63:0] la_data_out; |
| wire [63:0] la_data_out; |
| input [63:0] la_oenb; |
| wire [63:0] la_oenb; |
| wire [143:0] outputs_o; |
| wire [143:0] outputs_o_buf; |
| input user_clock2; |
| wire user_clock2; |
| output [2:0] user_irq; |
| wire [2:0] user_irq; |
| wire [31:0] vrnode_data; |
| wire [31:0] vrnode_data_out; |
| wire [32:0] \wb_arbiter_inst:11 ; |
| wire [468:0] \wb_arbiter_inst:13 ; |
| input wb_clk_i; |
| wire wb_clk_i; |
| wire [66:0] wb_from_caravel; |
| wire [230:0] wb_i_bottom; |
| wire [468:0] wb_o_bottom; |
| input wb_rst_i; |
| wire wb_rst_i; |
| wire [32:0] wb_to_caravel; |
| output wbs_ack_o; |
| wire wbs_ack_o; |
| input [31:0] wbs_adr_i; |
| wire [31:0] wbs_adr_i; |
| input wbs_cyc_i; |
| wire wbs_cyc_i; |
| input [31:0] wbs_dat_i; |
| wire [31:0] wbs_dat_i; |
| output [31:0] wbs_dat_o; |
| wire [31:0] wbs_dat_o; |
| input wbs_stb_i; |
| wire wbs_stb_i; |
| input wbs_we_i; |
| wire wbs_we_i; |
| assign _20_ = ~ fpga_rst[1]; |
| assign _21_ = _20_ ? inputs_i : { fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2] }; |
| assign _23_ = ~ fpga_rst[1]; |
| assign _24_ = _23_ ? outputs_o_buf : { fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2] }; |
| wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe block_write_fw_reg_inst ( |
| .reg_i(block_data_out), |
| .reg_o(_01_), |
| .wb_clk_i(wb_clk_i), |
| .\wb_i.adr_i (wb_o_bottom[66:35]), |
| .\wb_i.cyc_i (wb_o_bottom[1]), |
| .\wb_i.dat_i (wb_o_bottom[34:3]), |
| .\wb_i.stb_i (wb_o_bottom[0]), |
| .\wb_i.we_i (wb_o_bottom[2]), |
| .\wb_o.ack_o (_29_), |
| .\wb_o.dat_o (_30_), |
| .wb_rst_i(wb_rst_i) |
| ); |
| fpga_tech_clkbuffer config_block_clk_buf ( |
| .i(fw_tap_bus[0]), |
| .z(_17_) |
| ); |
| fpga_tech_clkbuffer config_hrnode_clk_buf ( |
| .i(fw_tap_bus[2]), |
| .z(_19_) |
| ); |
| fpga_tech_clkbuffer config_vrnode_clk_buf ( |
| .i(fw_tap_bus[1]), |
| .z(_18_) |
| ); |
| efuse_ctrl efuse_mem_inst ( |
| .wb_ack_o(_16_), |
| .wb_adr_i(wb_o_bottom[447:437]), |
| .wb_clk_i(wb_clk_i), |
| .wb_cyc_i(wb_o_bottom[403]), |
| .wb_dat_i(wb_o_bottom[412:405]), |
| .wb_dat_o(_15_), |
| .wb_rst_i(wb_rst_i), |
| .wb_sel_i(1'h0), |
| .wb_stb_i(wb_o_bottom[402]), |
| .wb_we_i(wb_o_bottom[404]) |
| ); |
| wb_register32_81b45b9a32734d4367912d54c45d3716474431dc fabric_reset_reg_inst ( |
| .reg_i(32'd0), |
| .reg_o(_10_), |
| .wb_clk_i(wb_clk_i), |
| .\wb_i.adr_i (wb_o_bottom[267:236]), |
| .\wb_i.cyc_i (wb_o_bottom[202]), |
| .\wb_i.dat_i (wb_o_bottom[235:204]), |
| .\wb_i.stb_i (wb_o_bottom[201]), |
| .\wb_i.we_i (wb_o_bottom[203]), |
| .\wb_o.ack_o (_08_), |
| .\wb_o.dat_o (_09_), |
| .wb_rst_i(wb_rst_i) |
| ); |
| fpga_fabric_4_9_144_144 fpga_fabric_inst ( |
| .clk_i(wb_clk_i), |
| .config_block_i(config_block_i), |
| .config_block_o(_25_), |
| .config_hrnode_i(config_hrnode_i), |
| .config_hrnode_o(_27_), |
| .config_vrnode_i(config_vrnode_i), |
| .config_vrnode_o(_26_), |
| .glb_rst_i(fpga_rst[0]), |
| .inputs_i(inputs_i_buf), |
| .outputs_o(_28_) |
| ); |
| wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe hrnode_write_fw_reg_inst ( |
| .reg_i(hrnode_data_out), |
| .reg_o(_07_), |
| .wb_clk_i(wb_clk_i), |
| .\wb_i.adr_i (wb_o_bottom[200:169]), |
| .\wb_i.cyc_i (wb_o_bottom[135]), |
| .\wb_i.dat_i (wb_o_bottom[168:137]), |
| .\wb_i.stb_i (wb_o_bottom[134]), |
| .\wb_i.we_i (wb_o_bottom[136]), |
| .\wb_o.ack_o (_05_), |
| .\wb_o.dat_o (_06_), |
| .wb_rst_i(wb_rst_i) |
| ); |
| wb_register32_91a7f356ca6ce41b6122bd41e60c1f2eb8f0f0e3 tap_write_fw_reg_inst ( |
| .reg_i(32'd0), |
| .reg_o(_14_), |
| .wb_clk_i(wb_clk_i), |
| .\wb_i.adr_i (wb_o_bottom[334:303]), |
| .\wb_i.cyc_i (wb_o_bottom[269]), |
| .\wb_i.dat_i (wb_o_bottom[302:271]), |
| .\wb_i.stb_i (wb_o_bottom[268]), |
| .\wb_i.we_i (wb_o_bottom[270]), |
| .\wb_o.ack_o (_12_), |
| .\wb_o.dat_o (_13_), |
| .wb_rst_i(wb_rst_i) |
| ); |
| wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe vrnode_write_fw_reg_inst ( |
| .reg_i(vrnode_data_out), |
| .reg_o(_04_), |
| .wb_clk_i(wb_clk_i), |
| .\wb_i.adr_i (wb_o_bottom[133:102]), |
| .\wb_i.cyc_i (wb_o_bottom[68]), |
| .\wb_i.dat_i (wb_o_bottom[101:70]), |
| .\wb_i.stb_i (wb_o_bottom[67]), |
| .\wb_i.we_i (wb_o_bottom[69]), |
| .\wb_o.ack_o (_02_), |
| .\wb_o.dat_o (_03_), |
| .wb_rst_i(wb_rst_i) |
| ); |
| wb_arbiter_sync_7 wb_arbiter_inst ( |
| .addr_map(224'h30030000300200003001e0003001a000300120003001100030010000), |
| .wb_clk_i(wb_clk_i), |
| .wb_i_bottom(wb_i_bottom), |
| .\wb_i_up.adr_i (wb_from_caravel[66:35]), |
| .\wb_i_up.cyc_i (wb_from_caravel[1]), |
| .\wb_i_up.dat_i (wb_from_caravel[34:3]), |
| .\wb_i_up.stb_i (wb_from_caravel[0]), |
| .\wb_i_up.we_i (wb_from_caravel[2]), |
| .wb_o_bottom(_22_), |
| .\wb_o_up.ack_o (_00_), |
| .\wb_o_up.dat_o (_11_), |
| .wb_rst_i(wb_rst_i) |
| ); |
| assign block_data = _01_; |
| assign block_data_out = { 30'h00000000, config_block_o }; |
| assign vrnode_data = _04_; |
| assign vrnode_data_out = { 25'h0000000, config_vrnode_o }; |
| assign hrnode_data = _07_; |
| assign hrnode_data_out = { 30'h00000000, config_hrnode_o }; |
| assign fw_tap_bus = _14_; |
| assign fpga_rst = _10_; |
| assign config_block_clk = _17_; |
| assign config_vrnode_clk = _18_; |
| assign config_hrnode_clk = _19_; |
| assign config_block_i = { block_data[1], config_block_clk, block_data[0], config_block_clk }; |
| assign config_block_o = _25_; |
| assign config_vrnode_i = { vrnode_data[6], config_vrnode_clk, vrnode_data[5], config_vrnode_clk, vrnode_data[4], config_vrnode_clk, vrnode_data[3], config_vrnode_clk, vrnode_data[2], config_vrnode_clk, vrnode_data[1], config_vrnode_clk, vrnode_data[0], config_vrnode_clk }; |
| assign config_vrnode_o = _26_; |
| assign config_hrnode_i = { hrnode_data[1], config_hrnode_clk, hrnode_data[0], config_hrnode_clk }; |
| assign config_hrnode_o = _27_; |
| assign inputs_i = { 69'h000000000000000000, io_in[30:0], fpga_rst[3], wb_o_bottom[335], wb_o_bottom[336], wb_o_bottom[337], wb_o_bottom[377:338] }; |
| assign outputs_o = _24_; |
| assign outputs_o_buf = _28_; |
| assign inputs_i_buf = _21_; |
| assign wb_from_caravel = { wbs_adr_i, wbs_dat_i, wbs_we_i, wbs_cyc_i, wbs_stb_i }; |
| assign wb_to_caravel = \wb_arbiter_inst:11 ; |
| assign wb_i_bottom = { 24'h000000, _15_, _16_, outputs_o[107:76], outputs_o[108], _13_, _12_, _09_, _08_, _06_, _05_, _03_, _02_, _30_, _29_ }; |
| assign wb_o_bottom = \wb_arbiter_inst:13 ; |
| assign \wb_arbiter_inst:11 = { _11_, _00_ }; |
| assign \wb_arbiter_inst:13 = _22_; |
| assign wbs_ack_o = wb_to_caravel[0]; |
| assign wbs_dat_o = wb_to_caravel[32:1]; |
| assign la_data_out = 64'h0000000000000000; |
| assign io_out = outputs_o[37:0]; |
| assign io_oeb = { 35'h000000000, outputs_o[143:141] }; |
| assign user_irq = 3'h0; |
| endmodule |
| |
| module fpga_cfg_shiftreg_2(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o); |
| reg [1:0] _0_; |
| input config_clk_i; |
| wire config_clk_i; |
| wire [1:0] config_data; |
| input config_ena_i; |
| wire config_ena_i; |
| output [1:0] config_o; |
| wire [1:0] config_o; |
| input config_shift_i; |
| wire config_shift_i; |
| output config_shift_o; |
| wire config_shift_o; |
| always @(posedge config_clk_i) |
| _0_ <= { config_shift_i, config_data[1] }; |
| assign config_data = _0_; |
| assign config_shift_o = config_data[0]; |
| assign config_o = config_data; |
| endmodule |
| |
| module fpga_cfg_shiftreg_48(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o); |
| reg [47:0] _0_; |
| input config_clk_i; |
| wire config_clk_i; |
| wire [47:0] config_data; |
| input config_ena_i; |
| wire config_ena_i; |
| output [47:0] config_o; |
| wire [47:0] config_o; |
| input config_shift_i; |
| wire config_shift_i; |
| output config_shift_o; |
| wire config_shift_o; |
| always @(posedge config_clk_i) |
| _0_ <= { config_shift_i, config_data[47:1] }; |
| assign config_data = _0_; |
| assign config_shift_o = config_data[0]; |
| assign config_o = config_data; |
| endmodule |
| |
| module fpga_fabric_4_9_144_144(clk_i, glb_rst_i, config_block_i, config_vrnode_i, config_hrnode_i, inputs_i, config_block_o, config_vrnode_o, config_hrnode_o, outputs_o); |
| wire _000_; |
| wire _001_; |
| wire [7:0] _002_; |
| wire _003_; |
| wire [7:0] _004_; |
| wire _005_; |
| wire [7:0] _006_; |
| wire _007_; |
| wire [7:0] _008_; |
| wire _009_; |
| wire [7:0] _010_; |
| wire _011_; |
| wire [7:0] _012_; |
| wire _013_; |
| wire [7:0] _014_; |
| wire _015_; |
| wire [7:0] _016_; |
| wire _017_; |
| wire [7:0] _018_; |
| wire _019_; |
| wire [7:0] _020_; |
| wire _021_; |
| wire [7:0] _022_; |
| wire _023_; |
| wire [7:0] _024_; |
| wire _025_; |
| wire [7:0] _026_; |
| wire _027_; |
| wire [7:0] _028_; |
| wire _029_; |
| wire [7:0] _030_; |
| wire _031_; |
| wire [15:0] _032_; |
| wire _033_; |
| wire [15:0] _034_; |
| wire _035_; |
| wire [7:0] _036_; |
| wire _037_; |
| wire [15:0] _038_; |
| wire _039_; |
| wire [15:0] _040_; |
| wire _041_; |
| wire [7:0] _042_; |
| wire _043_; |
| wire [15:0] _044_; |
| wire _045_; |
| wire [15:0] _046_; |
| wire _047_; |
| wire [7:0] _048_; |
| wire _049_; |
| wire [15:0] _050_; |
| wire _051_; |
| wire [15:0] _052_; |
| wire _053_; |
| wire [7:0] _054_; |
| wire _055_; |
| wire [15:0] _056_; |
| wire _057_; |
| wire [15:0] _058_; |
| wire _059_; |
| wire [7:0] _060_; |
| wire _061_; |
| wire [15:0] _062_; |
| wire _063_; |
| wire [15:0] _064_; |
| wire _065_; |
| wire [7:0] _066_; |
| wire _067_; |
| wire [15:0] _068_; |
| wire _069_; |
| wire [15:0] _070_; |
| wire _071_; |
| wire [15:0] _072_; |
| wire _073_; |
| wire [15:0] _074_; |
| wire _075_; |
| wire [15:0] _076_; |
| wire _077_; |
| wire [15:0] _078_; |
| wire _079_; |
| wire [15:0] _080_; |
| wire _081_; |
| wire [15:0] _082_; |
| wire _083_; |
| wire [15:0] _084_; |
| wire _085_; |
| wire [15:0] _086_; |
| wire _087_; |
| wire [15:0] _088_; |
| wire _089_; |
| wire [15:0] _090_; |
| wire _091_; |
| wire [15:0] _092_; |
| wire _093_; |
| wire [15:0] _094_; |
| wire _095_; |
| wire [15:0] _096_; |
| wire _097_; |
| wire [15:0] _098_; |
| wire _099_; |
| wire [15:0] _100_; |
| wire _101_; |
| wire [7:0] _102_; |
| wire _103_; |
| wire [15:0] _104_; |
| wire _105_; |
| wire [15:0] _106_; |
| wire _107_; |
| wire [7:0] _108_; |
| wire _109_; |
| wire [15:0] _110_; |
| wire _111_; |
| wire [15:0] _112_; |
| wire _113_; |
| wire [7:0] _114_; |
| wire _115_; |
| wire [15:0] _116_; |
| wire _117_; |
| wire [15:0] _118_; |
| wire _119_; |
| wire [7:0] _120_; |
| wire _121_; |
| wire [15:0] _122_; |
| wire _123_; |
| wire [15:0] _124_; |
| wire _125_; |
| wire [7:0] _126_; |
| wire _127_; |
| wire [15:0] _128_; |
| wire _129_; |
| wire [15:0] _130_; |
| wire _131_; |
| wire [7:0] _132_; |
| wire _133_; |
| wire [15:0] _134_; |
| wire _135_; |
| wire [15:0] _136_; |
| wire _137_; |
| wire [7:0] _138_; |
| wire _139_; |
| wire [15:0] _140_; |
| wire _141_; |
| wire [7:0] _142_; |
| wire _143_; |
| wire [15:0] _144_; |
| wire _145_; |
| wire [15:0] _146_; |
| wire _147_; |
| wire [15:0] _148_; |
| wire _149_; |
| wire [15:0] _150_; |
| wire _151_; |
| wire [15:0] _152_; |
| wire _153_; |
| wire [15:0] _154_; |
| wire _155_; |
| wire [15:0] _156_; |
| wire _157_; |
| wire [15:0] _158_; |
| wire _159_; |
| wire [15:0] _160_; |
| wire _161_; |
| wire [15:0] _162_; |
| wire _163_; |
| wire [15:0] _164_; |
| wire _165_; |
| wire [15:0] _166_; |
| wire _167_; |
| wire [15:0] _168_; |
| wire _169_; |
| wire [15:0] _170_; |
| wire _171_; |
| wire [15:0] _172_; |
| wire _173_; |
| wire [7:0] _174_; |
| wire _175_; |
| wire [15:0] _176_; |
| wire _177_; |
| wire [7:0] _178_; |
| wire _179_; |
| wire [15:0] _180_; |
| wire _181_; |
| wire [15:0] _182_; |
| wire _183_; |
| wire [15:0] _184_; |
| wire _185_; |
| wire [15:0] _186_; |
| wire _187_; |
| wire [15:0] _188_; |
| wire _189_; |
| wire [15:0] _190_; |
| wire _191_; |
| wire [15:0] _192_; |
| wire _193_; |
| wire [15:0] _194_; |
| wire _195_; |
| wire [15:0] _196_; |
| wire _197_; |
| wire [15:0] _198_; |
| wire _199_; |
| wire [15:0] _200_; |
| wire _201_; |
| wire [15:0] _202_; |
| wire _203_; |
| wire [15:0] _204_; |
| wire _205_; |
| wire [15:0] _206_; |
| wire _207_; |
| wire [15:0] _208_; |
| wire _209_; |
| wire [7:0] _210_; |
| wire _211_; |
| wire [15:0] _212_; |
| wire [15:0] block_cfg_shift_chain; |
| wire [111:0] block_out; |
| input clk_i; |
| wire clk_i; |
| input [3:0] config_block_i; |
| wire [3:0] config_block_i; |
| output [1:0] config_block_o; |
| wire [1:0] config_block_o; |
| input [3:0] config_hrnode_i; |
| wire [3:0] config_hrnode_i; |
| output [1:0] config_hrnode_o; |
| wire [1:0] config_hrnode_o; |
| input [13:0] config_vrnode_i; |
| wire [13:0] config_vrnode_i; |
| output [6:0] config_vrnode_o; |
| wire [6:0] config_vrnode_o; |
| wire [335:0] down_tracks_fwd; |
| wire [2351:0] down_tracks_in; |
| wire [335:0] down_tracks_out; |
| input glb_rst_i; |
| wire glb_rst_i; |
| wire glb_rstn; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31125 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31127 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31135 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31137 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32267 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32269 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32277 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32279 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33409 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33411 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33419 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33421 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34551 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34553 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34561 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34563 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35693 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35695 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35703 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35705 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36835 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36837 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36845 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36847 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37977 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37979 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37987 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37989 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37999 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:38001 ; |
| wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39462 ; |
| wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39464 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40930 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40932 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40940 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40942 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42072 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42074 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42082 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42084 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43214 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43216 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43224 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43226 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44356 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44358 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44366 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44368 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45498 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45500 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45508 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45510 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46640 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46642 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46650 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46652 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47782 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47784 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47792 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47794 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47804 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47806 ; |
| wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49267 ; |
| wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49269 ; |
| wire [37:0] hrnode_cfg_shift_chain; |
| input [143:0] inputs_i; |
| wire [143:0] inputs_i; |
| wire [255:0] left_tracks_fwd; |
| wire [1791:0] left_tracks_in; |
| wire [255:0] left_tracks_out; |
| output [143:0] outputs_o; |
| wire [143:0] outputs_o; |
| wire [255:0] right_tracks_fwd; |
| wire [1791:0] right_tracks_in; |
| wire [255:0] right_tracks_out; |
| wire [335:0] up_tracks_fwd; |
| wire [2351:0] up_tracks_in; |
| wire [335:0] up_tracks_out; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2470 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2472 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2460 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2462 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3948 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3950 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3938 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3940 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5426 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5428 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5416 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5418 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6904 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6906 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6894 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6896 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8382 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8384 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8372 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8374 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9860 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9862 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9850 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9852 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11338 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11340 ; |
| wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11328 ; |
| wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11330 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12480 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12482 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12470 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12472 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13622 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13624 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13612 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13614 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14764 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14766 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14754 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14756 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15906 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15908 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15896 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15898 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17048 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17050 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17038 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17040 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18190 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18192 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18180 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18182 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19332 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19334 ; |
| wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19322 ; |
| wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19324 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20807 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20809 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19344 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19346 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22282 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22284 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20819 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20821 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23757 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23759 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22294 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22296 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25232 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25234 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23769 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23771 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26707 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26709 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25244 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25246 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28182 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28184 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26719 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26721 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29657 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29659 ; |
| wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28194 ; |
| wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28196 ; |
| wire [62:0] vrnode_cfg_shift_chain; |
| assign _000_ = ~ glb_rst_i; |
| fpga_io_mux \horizontal_routing_network_x:1.horizontal_routing_network_y:1.down_io.routing_down_io ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[36]), |
| .config_shift_o(_141_), |
| .pins_o(_142_), |
| .route_i({ right_tracks_out[255:240], left_tracks_out[255:240] }) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[35]), |
| .config_shift_o(_143_), |
| .route_i(left_tracks_in[1791:1680]), |
| .route_o(_144_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[34]), |
| .config_shift_o(_145_), |
| .route_i(right_tracks_in[1791:1680]), |
| .route_o(_146_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[33]), |
| .config_shift_o(_147_), |
| .route_i(left_tracks_in[1679:1568]), |
| .route_o(_148_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[32]), |
| .config_shift_o(_149_), |
| .route_i(right_tracks_in[1679:1568]), |
| .route_o(_150_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[31]), |
| .config_shift_o(_151_), |
| .route_i(left_tracks_in[1567:1456]), |
| .route_o(_152_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[30]), |
| .config_shift_o(_153_), |
| .route_i(right_tracks_in[1567:1456]), |
| .route_o(_154_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[29]), |
| .config_shift_o(_155_), |
| .route_i(left_tracks_in[1455:1344]), |
| .route_o(_156_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[28]), |
| .config_shift_o(_157_), |
| .route_i(right_tracks_in[1455:1344]), |
| .route_o(_158_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[27]), |
| .config_shift_o(_159_), |
| .route_i(left_tracks_in[1343:1232]), |
| .route_o(_160_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[26]), |
| .config_shift_o(_161_), |
| .route_i(right_tracks_in[1343:1232]), |
| .route_o(_162_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[25]), |
| .config_shift_o(_163_), |
| .route_i(left_tracks_in[1231:1120]), |
| .route_o(_164_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[24]), |
| .config_shift_o(_165_), |
| .route_i(right_tracks_in[1231:1120]), |
| .route_o(_166_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[23]), |
| .config_shift_o(_167_), |
| .route_i(left_tracks_in[1119:1008]), |
| .route_o(_168_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[22]), |
| .config_shift_o(_169_), |
| .route_i(right_tracks_in[1119:1008]), |
| .route_o(_170_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[21]), |
| .config_shift_o(_171_), |
| .route_i(left_tracks_in[1007:896]), |
| .route_o(_172_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[20]), |
| .config_shift_o(_175_), |
| .route_i(right_tracks_in[1007:896]), |
| .route_o(_176_) |
| ); |
| fpga_io_mux \horizontal_routing_network_x:1.horizontal_routing_network_y:8.up_io.routing_up_io ( |
| .config_clk_i(config_hrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[19]), |
| .config_shift_o(_173_), |
| .pins_o(_174_), |
| .route_i({ right_tracks_out[143:128], left_tracks_out[143:128] }) |
| ); |
| fpga_io_mux \horizontal_routing_network_x:2.horizontal_routing_network_y:1.down_io.routing_down_io ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[17]), |
| .config_shift_o(_177_), |
| .pins_o(_178_), |
| .route_i({ right_tracks_out[127:112], left_tracks_out[127:112] }) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[16]), |
| .config_shift_o(_179_), |
| .route_i(left_tracks_in[895:784]), |
| .route_o(_180_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[15]), |
| .config_shift_o(_181_), |
| .route_i(right_tracks_in[895:784]), |
| .route_o(_182_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[14]), |
| .config_shift_o(_183_), |
| .route_i(left_tracks_in[783:672]), |
| .route_o(_184_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[13]), |
| .config_shift_o(_185_), |
| .route_i(right_tracks_in[783:672]), |
| .route_o(_186_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[12]), |
| .config_shift_o(_187_), |
| .route_i(left_tracks_in[671:560]), |
| .route_o(_188_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[11]), |
| .config_shift_o(_189_), |
| .route_i(right_tracks_in[671:560]), |
| .route_o(_190_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[10]), |
| .config_shift_o(_191_), |
| .route_i(left_tracks_in[559:448]), |
| .route_o(_192_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[9]), |
| .config_shift_o(_193_), |
| .route_i(right_tracks_in[559:448]), |
| .route_o(_194_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[8]), |
| .config_shift_o(_195_), |
| .route_i(left_tracks_in[447:336]), |
| .route_o(_196_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[7]), |
| .config_shift_o(_197_), |
| .route_i(right_tracks_in[447:336]), |
| .route_o(_198_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[6]), |
| .config_shift_o(_199_), |
| .route_i(left_tracks_in[335:224]), |
| .route_o(_200_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[5]), |
| .config_shift_o(_201_), |
| .route_i(right_tracks_in[335:224]), |
| .route_o(_202_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[4]), |
| .config_shift_o(_203_), |
| .route_i(left_tracks_in[223:112]), |
| .route_o(_204_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[3]), |
| .config_shift_o(_205_), |
| .route_i(right_tracks_in[223:112]), |
| .route_o(_206_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[2]), |
| .config_shift_o(_207_), |
| .route_i(left_tracks_in[111:0]), |
| .route_o(_208_) |
| ); |
| fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[1]), |
| .config_shift_o(_211_), |
| .route_i(right_tracks_in[111:0]), |
| .route_o(_212_) |
| ); |
| fpga_io_mux \horizontal_routing_network_x:2.horizontal_routing_network_y:8.up_io.routing_up_io ( |
| .config_clk_i(config_hrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(hrnode_cfg_shift_chain[0]), |
| .config_shift_o(_209_), |
| .pins_o(_210_), |
| .route_i({ right_tracks_out[15:0], left_tracks_out[15:0] }) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:1.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[9]), |
| .config_shift_o(_001_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[255:240], left_tracks_out[255:240] }), |
| .inputs_left_i({ down_tracks_out[335:320], up_tracks_out[335:320] }), |
| .inputs_right_i({ down_tracks_out[223:208], up_tracks_out[223:208] }), |
| .inputs_up_i({ right_tracks_out[239:224], left_tracks_out[239:224] }), |
| .outputs_o(_002_) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:2.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[10]), |
| .config_shift_o(_003_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[239:224], left_tracks_out[239:224] }), |
| .inputs_left_i({ down_tracks_out[319:304], up_tracks_out[319:304] }), |
| .inputs_right_i({ down_tracks_out[207:192], up_tracks_out[207:192] }), |
| .inputs_up_i({ right_tracks_out[223:208], left_tracks_out[223:208] }), |
| .outputs_o(_004_) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:3.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[11]), |
| .config_shift_o(_005_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[223:208], left_tracks_out[223:208] }), |
| .inputs_left_i({ down_tracks_out[303:288], up_tracks_out[303:288] }), |
| .inputs_right_i({ down_tracks_out[191:176], up_tracks_out[191:176] }), |
| .inputs_up_i({ right_tracks_out[207:192], left_tracks_out[207:192] }), |
| .outputs_o(_006_) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:4.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[12]), |
| .config_shift_o(_007_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[207:192], left_tracks_out[207:192] }), |
| .inputs_left_i({ down_tracks_out[287:272], up_tracks_out[287:272] }), |
| .inputs_right_i({ down_tracks_out[175:160], up_tracks_out[175:160] }), |
| .inputs_up_i({ right_tracks_out[191:176], left_tracks_out[191:176] }), |
| .outputs_o(_008_) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:5.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[13]), |
| .config_shift_o(_009_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[191:176], left_tracks_out[191:176] }), |
| .inputs_left_i({ down_tracks_out[271:256], up_tracks_out[271:256] }), |
| .inputs_right_i({ down_tracks_out[159:144], up_tracks_out[159:144] }), |
| .inputs_up_i({ right_tracks_out[175:160], left_tracks_out[175:160] }), |
| .outputs_o(_010_) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:6.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[14]), |
| .config_shift_o(_011_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[175:160], left_tracks_out[175:160] }), |
| .inputs_left_i({ down_tracks_out[255:240], up_tracks_out[255:240] }), |
| .inputs_right_i({ down_tracks_out[143:128], up_tracks_out[143:128] }), |
| .inputs_up_i({ right_tracks_out[159:144], left_tracks_out[159:144] }), |
| .outputs_o(_012_) |
| ); |
| fpga_struct_block \struct_blocks_x:1.struct_blocks_y:7.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[15]), |
| .config_shift_o(_013_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[159:144], left_tracks_out[159:144] }), |
| .inputs_left_i({ down_tracks_out[239:224], up_tracks_out[239:224] }), |
| .inputs_right_i({ down_tracks_out[127:112], up_tracks_out[127:112] }), |
| .inputs_up_i({ right_tracks_out[143:128], left_tracks_out[143:128] }), |
| .outputs_o(_014_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:1.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[1]), |
| .config_shift_o(_015_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[127:112], left_tracks_out[127:112] }), |
| .inputs_left_i({ down_tracks_out[223:208], up_tracks_out[223:208] }), |
| .inputs_right_i({ down_tracks_out[111:96], up_tracks_out[111:96] }), |
| .inputs_up_i({ right_tracks_out[111:96], left_tracks_out[111:96] }), |
| .outputs_o(_016_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:2.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[2]), |
| .config_shift_o(_017_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[111:96], left_tracks_out[111:96] }), |
| .inputs_left_i({ down_tracks_out[207:192], up_tracks_out[207:192] }), |
| .inputs_right_i({ down_tracks_out[95:80], up_tracks_out[95:80] }), |
| .inputs_up_i({ right_tracks_out[95:80], left_tracks_out[95:80] }), |
| .outputs_o(_018_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:3.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[3]), |
| .config_shift_o(_019_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[95:80], left_tracks_out[95:80] }), |
| .inputs_left_i({ down_tracks_out[191:176], up_tracks_out[191:176] }), |
| .inputs_right_i({ down_tracks_out[79:64], up_tracks_out[79:64] }), |
| .inputs_up_i({ right_tracks_out[79:64], left_tracks_out[79:64] }), |
| .outputs_o(_020_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:4.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[4]), |
| .config_shift_o(_021_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[79:64], left_tracks_out[79:64] }), |
| .inputs_left_i({ down_tracks_out[175:160], up_tracks_out[175:160] }), |
| .inputs_right_i({ down_tracks_out[63:48], up_tracks_out[63:48] }), |
| .inputs_up_i({ right_tracks_out[63:48], left_tracks_out[63:48] }), |
| .outputs_o(_022_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:5.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[5]), |
| .config_shift_o(_023_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[63:48], left_tracks_out[63:48] }), |
| .inputs_left_i({ down_tracks_out[159:144], up_tracks_out[159:144] }), |
| .inputs_right_i({ down_tracks_out[47:32], up_tracks_out[47:32] }), |
| .inputs_up_i({ right_tracks_out[47:32], left_tracks_out[47:32] }), |
| .outputs_o(_024_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:6.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[6]), |
| .config_shift_o(_025_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[47:32], left_tracks_out[47:32] }), |
| .inputs_left_i({ down_tracks_out[143:128], up_tracks_out[143:128] }), |
| .inputs_right_i({ down_tracks_out[31:16], up_tracks_out[31:16] }), |
| .inputs_up_i({ right_tracks_out[31:16], left_tracks_out[31:16] }), |
| .outputs_o(_026_) |
| ); |
| fpga_struct_block \struct_blocks_x:2.struct_blocks_y:7.struct_block ( |
| .clk_i(clk_i), |
| .config_clk_i(config_block_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(block_cfg_shift_chain[7]), |
| .config_shift_o(_027_), |
| .glb_rstn_i(glb_rstn), |
| .inputs_down_i({ right_tracks_out[31:16], left_tracks_out[31:16] }), |
| .inputs_left_i({ down_tracks_out[127:112], up_tracks_out[127:112] }), |
| .inputs_right_i({ down_tracks_out[15:0], up_tracks_out[15:0] }), |
| .inputs_up_i({ right_tracks_out[15:0], left_tracks_out[15:0] }), |
| .outputs_o(_028_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:1.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[61]), |
| .config_shift_o(_029_), |
| .pins_o(_030_), |
| .route_i({ down_tracks_out[335:320], up_tracks_out[335:320] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[59]), |
| .config_shift_o(_033_), |
| .route_i(down_tracks_in[2351:2240]), |
| .route_o(_034_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[60]), |
| .config_shift_o(_031_), |
| .route_i(up_tracks_in[2351:2240]), |
| .route_o(_032_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:2.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[52]), |
| .config_shift_o(_035_), |
| .pins_o(_036_), |
| .route_i({ down_tracks_out[319:304], up_tracks_out[319:304] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[50]), |
| .config_shift_o(_039_), |
| .route_i(down_tracks_in[2239:2128]), |
| .route_o(_040_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[51]), |
| .config_shift_o(_037_), |
| .route_i(up_tracks_in[2239:2128]), |
| .route_o(_038_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:3.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[43]), |
| .config_shift_o(_041_), |
| .pins_o(_042_), |
| .route_i({ down_tracks_out[303:288], up_tracks_out[303:288] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[41]), |
| .config_shift_o(_045_), |
| .route_i(down_tracks_in[2127:2016]), |
| .route_o(_046_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[42]), |
| .config_shift_o(_043_), |
| .route_i(up_tracks_in[2127:2016]), |
| .route_o(_044_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:4.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[34]), |
| .config_shift_o(_047_), |
| .pins_o(_048_), |
| .route_i({ down_tracks_out[287:272], up_tracks_out[287:272] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[32]), |
| .config_shift_o(_051_), |
| .route_i(down_tracks_in[2015:1904]), |
| .route_o(_052_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[33]), |
| .config_shift_o(_049_), |
| .route_i(up_tracks_in[2015:1904]), |
| .route_o(_050_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:5.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[25]), |
| .config_shift_o(_053_), |
| .pins_o(_054_), |
| .route_i({ down_tracks_out[271:256], up_tracks_out[271:256] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[23]), |
| .config_shift_o(_057_), |
| .route_i(down_tracks_in[1903:1792]), |
| .route_o(_058_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[24]), |
| .config_shift_o(_055_), |
| .route_i(up_tracks_in[1903:1792]), |
| .route_o(_056_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:6.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[16]), |
| .config_shift_o(_059_), |
| .pins_o(_060_), |
| .route_i({ down_tracks_out[255:240], up_tracks_out[255:240] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[14]), |
| .config_shift_o(_063_), |
| .route_i(down_tracks_in[1791:1680]), |
| .route_o(_064_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[15]), |
| .config_shift_o(_061_), |
| .route_i(up_tracks_in[1791:1680]), |
| .route_o(_062_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:7.left_io.routing_left_io ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[7]), |
| .config_shift_o(_065_), |
| .pins_o(_066_), |
| .route_i({ down_tracks_out[239:224], up_tracks_out[239:224] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[5]), |
| .config_shift_o(_069_), |
| .route_i(down_tracks_in[1679:1568]), |
| .route_o(_070_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[6]), |
| .config_shift_o(_067_), |
| .route_i(up_tracks_in[1679:1568]), |
| .route_o(_068_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[57]), |
| .config_shift_o(_073_), |
| .route_i(down_tracks_in[1567:1456]), |
| .route_o(_074_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[58]), |
| .config_shift_o(_071_), |
| .route_i(up_tracks_in[1567:1456]), |
| .route_o(_072_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[48]), |
| .config_shift_o(_077_), |
| .route_i(down_tracks_in[1455:1344]), |
| .route_o(_078_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[49]), |
| .config_shift_o(_075_), |
| .route_i(up_tracks_in[1455:1344]), |
| .route_o(_076_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[39]), |
| .config_shift_o(_081_), |
| .route_i(down_tracks_in[1343:1232]), |
| .route_o(_082_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[40]), |
| .config_shift_o(_079_), |
| .route_i(up_tracks_in[1343:1232]), |
| .route_o(_080_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[30]), |
| .config_shift_o(_085_), |
| .route_i(down_tracks_in[1231:1120]), |
| .route_o(_086_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[31]), |
| .config_shift_o(_083_), |
| .route_i(up_tracks_in[1231:1120]), |
| .route_o(_084_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[21]), |
| .config_shift_o(_089_), |
| .route_i(down_tracks_in[1119:1008]), |
| .route_o(_090_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[22]), |
| .config_shift_o(_087_), |
| .route_i(up_tracks_in[1119:1008]), |
| .route_o(_088_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[12]), |
| .config_shift_o(_093_), |
| .route_i(down_tracks_in[1007:896]), |
| .route_o(_094_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[13]), |
| .config_shift_o(_091_), |
| .route_i(up_tracks_in[1007:896]), |
| .route_o(_092_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[3]), |
| .config_shift_o(_097_), |
| .route_i(down_tracks_in[895:784]), |
| .route_o(_098_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[4]), |
| .config_shift_o(_095_), |
| .route_i(up_tracks_in[895:784]), |
| .route_o(_096_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:1.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[54]), |
| .config_shift_o(_101_), |
| .pins_o(_102_), |
| .route_i({ down_tracks_out[111:96], up_tracks_out[111:96] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[55]), |
| .config_shift_o(_103_), |
| .route_i(down_tracks_in[783:672]), |
| .route_o(_104_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up ( |
| .config_clk_i(config_vrnode_i[0]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[56]), |
| .config_shift_o(_099_), |
| .route_i(up_tracks_in[783:672]), |
| .route_o(_100_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:2.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[45]), |
| .config_shift_o(_107_), |
| .pins_o(_108_), |
| .route_i({ down_tracks_out[95:80], up_tracks_out[95:80] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[46]), |
| .config_shift_o(_109_), |
| .route_i(down_tracks_in[671:560]), |
| .route_o(_110_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up ( |
| .config_clk_i(config_vrnode_i[2]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[47]), |
| .config_shift_o(_105_), |
| .route_i(up_tracks_in[671:560]), |
| .route_o(_106_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:3.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[36]), |
| .config_shift_o(_113_), |
| .pins_o(_114_), |
| .route_i({ down_tracks_out[79:64], up_tracks_out[79:64] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[37]), |
| .config_shift_o(_115_), |
| .route_i(down_tracks_in[559:448]), |
| .route_o(_116_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up ( |
| .config_clk_i(config_vrnode_i[4]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[38]), |
| .config_shift_o(_111_), |
| .route_i(up_tracks_in[559:448]), |
| .route_o(_112_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:4.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[27]), |
| .config_shift_o(_119_), |
| .pins_o(_120_), |
| .route_i({ down_tracks_out[63:48], up_tracks_out[63:48] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[28]), |
| .config_shift_o(_121_), |
| .route_i(down_tracks_in[447:336]), |
| .route_o(_122_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up ( |
| .config_clk_i(config_vrnode_i[6]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[29]), |
| .config_shift_o(_117_), |
| .route_i(up_tracks_in[447:336]), |
| .route_o(_118_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:5.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[18]), |
| .config_shift_o(_125_), |
| .pins_o(_126_), |
| .route_i({ down_tracks_out[47:32], up_tracks_out[47:32] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[19]), |
| .config_shift_o(_127_), |
| .route_i(down_tracks_in[335:224]), |
| .route_o(_128_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up ( |
| .config_clk_i(config_vrnode_i[8]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[20]), |
| .config_shift_o(_123_), |
| .route_i(up_tracks_in[335:224]), |
| .route_o(_124_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:6.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[9]), |
| .config_shift_o(_131_), |
| .pins_o(_132_), |
| .route_i({ down_tracks_out[31:16], up_tracks_out[31:16] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[10]), |
| .config_shift_o(_133_), |
| .route_i(down_tracks_in[223:112]), |
| .route_o(_134_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up ( |
| .config_clk_i(config_vrnode_i[10]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[11]), |
| .config_shift_o(_129_), |
| .route_i(up_tracks_in[223:112]), |
| .route_o(_130_) |
| ); |
| fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:7.right_io.routing_right_io ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[0]), |
| .config_shift_o(_137_), |
| .pins_o(_138_), |
| .route_i({ down_tracks_out[15:0], up_tracks_out[15:0] }) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[1]), |
| .config_shift_o(_139_), |
| .route_i(down_tracks_in[111:0]), |
| .route_o(_140_) |
| ); |
| fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up ( |
| .config_clk_i(config_vrnode_i[12]), |
| .config_ena_i(glb_rst_i), |
| .config_shift_i(vrnode_cfg_shift_chain[2]), |
| .config_shift_o(_135_), |
| .route_i(up_tracks_in[111:0]), |
| .route_o(_136_) |
| ); |
| assign block_out = { _002_, _004_, _006_, _008_, _010_, _012_, _014_, _016_, _018_, _020_, _022_, _024_, _026_, _028_ }; |
| assign glb_rstn = _000_; |
| assign block_cfg_shift_chain = { config_block_i[1], _013_, _011_, _009_, _007_, _005_, _003_, _001_, config_block_i[3], _027_, _025_, _023_, _021_, _019_, _017_, _015_ }; |
| assign hrnode_cfg_shift_chain = { _141_, \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31125 , \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31135 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32267 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32277 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33409 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33419 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34551 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34561 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35693 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35703 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36835 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36845 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37977 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37987 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37999 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39462 , _173_, config_hrnode_i[1], _177_, \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40930 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40940 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42072 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42082 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43214 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43224 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44356 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44366 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45498 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45508 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46640 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46650 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47782 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47792 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47804 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49267 , _209_, config_hrnode_i[3] }; |
| assign vrnode_cfg_shift_chain = { _029_, \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2460 , \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2470 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12470 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12480 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19344 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20807 , _101_, config_vrnode_i[1], _035_, \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3938 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3948 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13612 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13622 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20819 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22282 , _107_, config_vrnode_i[3], _041_, \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5416 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5426 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14754 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14764 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22294 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23757 , _113_, config_vrnode_i[5], _047_, \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6894 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6904 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15896 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15906 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23769 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25232 , _119_, config_vrnode_i[7], _053_, \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8372 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8382 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17038 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17048 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25244 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26707 , _125_, config_vrnode_i[9], _059_, \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9850 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9860 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18180 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18190 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26719 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28182 , _131_, config_vrnode_i[11], _065_, \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11328 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11338 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19322 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19332 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28194 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29657 , _137_, config_vrnode_i[13] }; |
| assign up_tracks_in = { left_tracks_out[241], 1'h0, up_tracks_fwd[320], block_out[111], block_out[107], 1'h0, inputs_i[0], left_tracks_out[242], 1'h0, up_tracks_fwd[321], block_out[111], block_out[107], 1'h0, inputs_i[0], left_tracks_out[243], 1'h0, up_tracks_fwd[322], block_out[111], block_out[107], 1'h0, inputs_i[1], left_tracks_out[244], 1'h0, up_tracks_fwd[323], block_out[111], block_out[107], 1'h0, inputs_i[1], left_tracks_out[245], 1'h0, up_tracks_fwd[324], block_out[111], block_out[107], 1'h0, inputs_i[2], left_tracks_out[246], 1'h0, up_tracks_fwd[325], block_out[111], block_out[107], 1'h0, inputs_i[2], left_tracks_out[247], 1'h0, up_tracks_fwd[326], block_out[111], block_out[107], 1'h0, inputs_i[3], left_tracks_out[248], 1'h0, up_tracks_fwd[327], block_out[111], block_out[107], 1'h0, inputs_i[3], left_tracks_out[249], 1'h0, up_tracks_fwd[328], block_out[111], block_out[107], 1'h0, inputs_i[4], left_tracks_out[250], 1'h0, up_tracks_fwd[329], block_out[111], block_out[107], 1'h0, inputs_i[4], left_tracks_out[251], 1'h0, up_tracks_fwd[330], block_out[111], block_out[107], 1'h0, inputs_i[5], left_tracks_out[252], 1'h0, up_tracks_fwd[331], block_out[111], block_out[107], 1'h0, inputs_i[5], left_tracks_out[253], 1'h0, up_tracks_fwd[332], block_out[111], block_out[107], 1'h0, inputs_i[6], left_tracks_out[254], 1'h0, up_tracks_fwd[333], block_out[111], block_out[107], 1'h0, inputs_i[6], left_tracks_out[255], 1'h0, up_tracks_fwd[334], block_out[111], block_out[107], 1'h0, inputs_i[7], left_tracks_out[240], 1'h0, up_tracks_fwd[335], block_out[111], block_out[107], 1'h0, inputs_i[7], left_tracks_out[225], 1'h0, up_tracks_fwd[304], block_out[103], block_out[99], 1'h0, inputs_i[8], left_tracks_out[226], 1'h0, up_tracks_fwd[305], block_out[103], block_out[99], 1'h0, inputs_i[8], left_tracks_out[227], 1'h0, up_tracks_fwd[306], block_out[103], block_out[99], 1'h0, inputs_i[9], left_tracks_out[228], 1'h0, up_tracks_fwd[307], block_out[103], block_out[99], 1'h0, inputs_i[9], left_tracks_out[229], 1'h0, up_tracks_fwd[308], block_out[103], block_out[99], 1'h0, inputs_i[10], left_tracks_out[230], 1'h0, up_tracks_fwd[309], block_out[103], block_out[99], 1'h0, inputs_i[10], left_tracks_out[231], 1'h0, up_tracks_fwd[310], block_out[103], block_out[99], 1'h0, inputs_i[11], left_tracks_out[232], 1'h0, up_tracks_fwd[311], block_out[103], block_out[99], 1'h0, inputs_i[11], left_tracks_out[233], 1'h0, up_tracks_fwd[312], block_out[103], block_out[99], 1'h0, inputs_i[12], left_tracks_out[234], 1'h0, up_tracks_fwd[313], block_out[103], block_out[99], 1'h0, inputs_i[12], left_tracks_out[235], 1'h0, up_tracks_fwd[314], block_out[103], block_out[99], 1'h0, inputs_i[13], left_tracks_out[236], 1'h0, up_tracks_fwd[315], block_out[103], block_out[99], 1'h0, inputs_i[13], left_tracks_out[237], 1'h0, up_tracks_fwd[316], block_out[103], block_out[99], 1'h0, inputs_i[14], left_tracks_out[238], 1'h0, up_tracks_fwd[317], block_out[103], block_out[99], 1'h0, inputs_i[14], left_tracks_out[239], 1'h0, up_tracks_fwd[318], block_out[103], block_out[99], 1'h0, inputs_i[15], left_tracks_out[224], 1'h0, up_tracks_fwd[319], block_out[103], block_out[99], 1'h0, inputs_i[15], left_tracks_out[209], 1'h0, up_tracks_fwd[288], block_out[95], block_out[91], 1'h0, inputs_i[16], left_tracks_out[210], 1'h0, up_tracks_fwd[289], block_out[95], block_out[91], 1'h0, inputs_i[16], left_tracks_out[211], 1'h0, up_tracks_fwd[290], block_out[95], block_out[91], 1'h0, inputs_i[17], left_tracks_out[212], 1'h0, up_tracks_fwd[291], block_out[95], block_out[91], 1'h0, inputs_i[17], left_tracks_out[213], 1'h0, up_tracks_fwd[292], block_out[95], block_out[91], 1'h0, inputs_i[18], left_tracks_out[214], 1'h0, up_tracks_fwd[293], block_out[95], block_out[91], 1'h0, inputs_i[18], left_tracks_out[215], 1'h0, up_tracks_fwd[294], block_out[95], block_out[91], 1'h0, inputs_i[19], left_tracks_out[216], 1'h0, up_tracks_fwd[295], block_out[95], block_out[91], 1'h0, inputs_i[19], left_tracks_out[217], 1'h0, up_tracks_fwd[296], block_out[95], block_out[91], 1'h0, inputs_i[20], left_tracks_out[218], 1'h0, up_tracks_fwd[297], block_out[95], block_out[91], 1'h0, inputs_i[20], left_tracks_out[219], 1'h0, up_tracks_fwd[298], block_out[95], block_out[91], 1'h0, inputs_i[21], left_tracks_out[220], 1'h0, up_tracks_fwd[299], block_out[95], block_out[91], 1'h0, inputs_i[21], left_tracks_out[221], 1'h0, up_tracks_fwd[300], block_out[95], block_out[91], 1'h0, inputs_i[22], left_tracks_out[222], 1'h0, up_tracks_fwd[301], block_out[95], block_out[91], 1'h0, inputs_i[22], left_tracks_out[223], 1'h0, up_tracks_fwd[302], block_out[95], block_out[91], 1'h0, inputs_i[23], left_tracks_out[208], 1'h0, up_tracks_fwd[303], block_out[95], block_out[91], 1'h0, inputs_i[23], left_tracks_out[193], 1'h0, up_tracks_fwd[272], block_out[87], block_out[83], 1'h0, inputs_i[24], left_tracks_out[194], 1'h0, up_tracks_fwd[273], block_out[87], block_out[83], 1'h0, inputs_i[24], left_tracks_out[195], 1'h0, up_tracks_fwd[274], block_out[87], block_out[83], 1'h0, inputs_i[25], left_tracks_out[196], 1'h0, up_tracks_fwd[275], block_out[87], block_out[83], 1'h0, inputs_i[25], left_tracks_out[197], 1'h0, up_tracks_fwd[276], block_out[87], block_out[83], 1'h0, inputs_i[26], left_tracks_out[198], 1'h0, up_tracks_fwd[277], block_out[87], block_out[83], 1'h0, inputs_i[26], left_tracks_out[199], 1'h0, up_tracks_fwd[278], block_out[87], block_out[83], 1'h0, inputs_i[27], left_tracks_out[200], 1'h0, up_tracks_fwd[279], block_out[87], block_out[83], 1'h0, inputs_i[27], left_tracks_out[201], 1'h0, up_tracks_fwd[280], block_out[87], block_out[83], 1'h0, inputs_i[28], left_tracks_out[202], 1'h0, up_tracks_fwd[281], block_out[87], block_out[83], 1'h0, inputs_i[28], left_tracks_out[203], 1'h0, up_tracks_fwd[282], block_out[87], block_out[83], 1'h0, inputs_i[29], left_tracks_out[204], 1'h0, up_tracks_fwd[283], block_out[87], block_out[83], 1'h0, inputs_i[29], left_tracks_out[205], 1'h0, up_tracks_fwd[284], block_out[87], block_out[83], 1'h0, inputs_i[30], left_tracks_out[206], 1'h0, up_tracks_fwd[285], block_out[87], block_out[83], 1'h0, inputs_i[30], left_tracks_out[207], 1'h0, up_tracks_fwd[286], block_out[87], block_out[83], 1'h0, inputs_i[31], left_tracks_out[192], 1'h0, up_tracks_fwd[287], block_out[87], block_out[83], 1'h0, inputs_i[31], left_tracks_out[177], 1'h0, up_tracks_fwd[256], block_out[79], block_out[75], 1'h0, inputs_i[32], left_tracks_out[178], 1'h0, up_tracks_fwd[257], block_out[79], block_out[75], 1'h0, inputs_i[32], left_tracks_out[179], 1'h0, up_tracks_fwd[258], block_out[79], block_out[75], 1'h0, inputs_i[33], left_tracks_out[180], 1'h0, up_tracks_fwd[259], block_out[79], block_out[75], 1'h0, inputs_i[33], left_tracks_out[181], 1'h0, up_tracks_fwd[260], block_out[79], block_out[75], 1'h0, inputs_i[34], left_tracks_out[182], 1'h0, up_tracks_fwd[261], block_out[79], block_out[75], 1'h0, inputs_i[34], left_tracks_out[183], 1'h0, up_tracks_fwd[262], block_out[79], block_out[75], 1'h0, inputs_i[35], left_tracks_out[184], 1'h0, up_tracks_fwd[263], block_out[79], block_out[75], 1'h0, inputs_i[35], left_tracks_out[185], 1'h0, up_tracks_fwd[264], block_out[79], block_out[75], 1'h0, inputs_i[36], left_tracks_out[186], 1'h0, up_tracks_fwd[265], block_out[79], block_out[75], 1'h0, inputs_i[36], left_tracks_out[187], 1'h0, up_tracks_fwd[266], block_out[79], block_out[75], 1'h0, inputs_i[37], left_tracks_out[188], 1'h0, up_tracks_fwd[267], block_out[79], block_out[75], 1'h0, inputs_i[37], left_tracks_out[189], 1'h0, up_tracks_fwd[268], block_out[79], block_out[75], 1'h0, inputs_i[38], left_tracks_out[190], 1'h0, up_tracks_fwd[269], block_out[79], block_out[75], 1'h0, inputs_i[38], left_tracks_out[191], 1'h0, up_tracks_fwd[270], block_out[79], block_out[75], 1'h0, inputs_i[39], left_tracks_out[176], 1'h0, up_tracks_fwd[271], block_out[79], block_out[75], 1'h0, inputs_i[39], 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block_out[57], left_tracks_out[23], right_tracks_out[154], up_tracks_fwd[118], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[24], right_tracks_out[153], up_tracks_fwd[119], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[25], right_tracks_out[152], up_tracks_fwd[120], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[26], right_tracks_out[151], up_tracks_fwd[121], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[27], right_tracks_out[150], up_tracks_fwd[122], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[28], right_tracks_out[149], up_tracks_fwd[123], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[29], right_tracks_out[148], up_tracks_fwd[124], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[30], right_tracks_out[147], up_tracks_fwd[125], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[31], right_tracks_out[146], up_tracks_fwd[126], block_out[7], block_out[3], block_out[61], block_out[57], left_tracks_out[16], right_tracks_out[145], up_tracks_fwd[127], block_out[7], block_out[3], block_out[61], block_out[57], 1'h0, right_tracks_out[112], up_tracks_fwd[96], 1'h0, inputs_i[72], block_out[53], block_out[49], 1'h0, right_tracks_out[127], up_tracks_fwd[97], 1'h0, inputs_i[72], block_out[53], block_out[49], 1'h0, right_tracks_out[126], up_tracks_fwd[98], 1'h0, inputs_i[73], block_out[53], block_out[49], 1'h0, right_tracks_out[125], up_tracks_fwd[99], 1'h0, inputs_i[73], block_out[53], block_out[49], 1'h0, right_tracks_out[124], up_tracks_fwd[100], 1'h0, inputs_i[74], block_out[53], block_out[49], 1'h0, right_tracks_out[123], up_tracks_fwd[101], 1'h0, inputs_i[74], block_out[53], block_out[49], 1'h0, right_tracks_out[122], up_tracks_fwd[102], 1'h0, inputs_i[75], block_out[53], block_out[49], 1'h0, right_tracks_out[121], up_tracks_fwd[103], 1'h0, inputs_i[75], block_out[53], block_out[49], 1'h0, right_tracks_out[120], up_tracks_fwd[104], 1'h0, inputs_i[76], block_out[53], block_out[49], 1'h0, right_tracks_out[119], up_tracks_fwd[105], 1'h0, inputs_i[76], block_out[53], block_out[49], 1'h0, right_tracks_out[118], up_tracks_fwd[106], 1'h0, inputs_i[77], block_out[53], block_out[49], 1'h0, right_tracks_out[117], up_tracks_fwd[107], 1'h0, inputs_i[77], block_out[53], block_out[49], 1'h0, right_tracks_out[116], up_tracks_fwd[108], 1'h0, inputs_i[78], block_out[53], block_out[49], 1'h0, right_tracks_out[115], up_tracks_fwd[109], 1'h0, inputs_i[78], block_out[53], block_out[49], 1'h0, right_tracks_out[114], up_tracks_fwd[110], 1'h0, inputs_i[79], block_out[53], block_out[49], 1'h0, right_tracks_out[113], up_tracks_fwd[111], 1'h0, inputs_i[79], block_out[53], block_out[49], 1'h0, right_tracks_out[96], up_tracks_fwd[80], 1'h0, inputs_i[80], block_out[45], block_out[41], 1'h0, right_tracks_out[111], up_tracks_fwd[81], 1'h0, inputs_i[80], block_out[45], block_out[41], 1'h0, right_tracks_out[110], up_tracks_fwd[82], 1'h0, inputs_i[81], block_out[45], block_out[41], 1'h0, right_tracks_out[109], up_tracks_fwd[83], 1'h0, inputs_i[81], block_out[45], block_out[41], 1'h0, right_tracks_out[108], up_tracks_fwd[84], 1'h0, inputs_i[82], block_out[45], block_out[41], 1'h0, right_tracks_out[107], up_tracks_fwd[85], 1'h0, inputs_i[82], block_out[45], block_out[41], 1'h0, right_tracks_out[106], up_tracks_fwd[86], 1'h0, inputs_i[83], block_out[45], block_out[41], 1'h0, right_tracks_out[105], up_tracks_fwd[87], 1'h0, inputs_i[83], block_out[45], block_out[41], 1'h0, right_tracks_out[104], up_tracks_fwd[88], 1'h0, inputs_i[84], block_out[45], block_out[41], 1'h0, right_tracks_out[103], up_tracks_fwd[89], 1'h0, inputs_i[84], block_out[45], block_out[41], 1'h0, right_tracks_out[102], up_tracks_fwd[90], 1'h0, inputs_i[85], block_out[45], block_out[41], 1'h0, right_tracks_out[101], up_tracks_fwd[91], 1'h0, inputs_i[85], block_out[45], block_out[41], 1'h0, right_tracks_out[100], up_tracks_fwd[92], 1'h0, inputs_i[86], block_out[45], block_out[41], 1'h0, right_tracks_out[99], up_tracks_fwd[93], 1'h0, inputs_i[86], block_out[45], block_out[41], 1'h0, right_tracks_out[98], up_tracks_fwd[94], 1'h0, inputs_i[87], block_out[45], block_out[41], 1'h0, right_tracks_out[97], up_tracks_fwd[95], 1'h0, inputs_i[87], block_out[45], block_out[41], 1'h0, right_tracks_out[80], up_tracks_fwd[64], 1'h0, inputs_i[88], block_out[37], block_out[33], 1'h0, right_tracks_out[95], up_tracks_fwd[65], 1'h0, inputs_i[88], block_out[37], block_out[33], 1'h0, right_tracks_out[94], up_tracks_fwd[66], 1'h0, inputs_i[89], block_out[37], block_out[33], 1'h0, right_tracks_out[93], up_tracks_fwd[67], 1'h0, inputs_i[89], block_out[37], block_out[33], 1'h0, right_tracks_out[92], up_tracks_fwd[68], 1'h0, inputs_i[90], block_out[37], block_out[33], 1'h0, right_tracks_out[91], up_tracks_fwd[69], 1'h0, inputs_i[90], block_out[37], block_out[33], 1'h0, right_tracks_out[90], up_tracks_fwd[70], 1'h0, inputs_i[91], block_out[37], block_out[33], 1'h0, right_tracks_out[89], up_tracks_fwd[71], 1'h0, inputs_i[91], block_out[37], block_out[33], 1'h0, right_tracks_out[88], up_tracks_fwd[72], 1'h0, inputs_i[92], block_out[37], block_out[33], 1'h0, right_tracks_out[87], up_tracks_fwd[73], 1'h0, inputs_i[92], block_out[37], block_out[33], 1'h0, right_tracks_out[86], up_tracks_fwd[74], 1'h0, inputs_i[93], block_out[37], block_out[33], 1'h0, right_tracks_out[85], up_tracks_fwd[75], 1'h0, inputs_i[93], block_out[37], block_out[33], 1'h0, right_tracks_out[84], up_tracks_fwd[76], 1'h0, inputs_i[94], block_out[37], block_out[33], 1'h0, right_tracks_out[83], up_tracks_fwd[77], 1'h0, inputs_i[94], block_out[37], block_out[33], 1'h0, right_tracks_out[82], up_tracks_fwd[78], 1'h0, inputs_i[95], block_out[37], block_out[33], 1'h0, right_tracks_out[81], up_tracks_fwd[79], 1'h0, inputs_i[95], block_out[37], block_out[33], 1'h0, right_tracks_out[64], up_tracks_fwd[48], 1'h0, inputs_i[96], block_out[29], block_out[25], 1'h0, right_tracks_out[79], up_tracks_fwd[49], 1'h0, inputs_i[96], block_out[29], block_out[25], 1'h0, right_tracks_out[78], up_tracks_fwd[50], 1'h0, inputs_i[97], block_out[29], block_out[25], 1'h0, right_tracks_out[77], up_tracks_fwd[51], 1'h0, inputs_i[97], block_out[29], block_out[25], 1'h0, right_tracks_out[76], up_tracks_fwd[52], 1'h0, inputs_i[98], block_out[29], block_out[25], 1'h0, right_tracks_out[75], up_tracks_fwd[53], 1'h0, inputs_i[98], block_out[29], block_out[25], 1'h0, right_tracks_out[74], up_tracks_fwd[54], 1'h0, inputs_i[99], block_out[29], block_out[25], 1'h0, right_tracks_out[73], up_tracks_fwd[55], 1'h0, inputs_i[99], block_out[29], block_out[25], 1'h0, right_tracks_out[72], up_tracks_fwd[56], 1'h0, inputs_i[100], block_out[29], block_out[25], 1'h0, right_tracks_out[71], up_tracks_fwd[57], 1'h0, inputs_i[100], block_out[29], block_out[25], 1'h0, right_tracks_out[70], up_tracks_fwd[58], 1'h0, inputs_i[101], block_out[29], block_out[25], 1'h0, right_tracks_out[69], up_tracks_fwd[59], 1'h0, inputs_i[101], block_out[29], block_out[25], 1'h0, right_tracks_out[68], up_tracks_fwd[60], 1'h0, inputs_i[102], block_out[29], block_out[25], 1'h0, right_tracks_out[67], up_tracks_fwd[61], 1'h0, inputs_i[102], block_out[29], block_out[25], 1'h0, right_tracks_out[66], up_tracks_fwd[62], 1'h0, inputs_i[103], block_out[29], block_out[25], 1'h0, right_tracks_out[65], up_tracks_fwd[63], 1'h0, inputs_i[103], block_out[29], block_out[25], 1'h0, right_tracks_out[48], up_tracks_fwd[32], 1'h0, inputs_i[104], block_out[21], block_out[17], 1'h0, right_tracks_out[63], up_tracks_fwd[33], 1'h0, inputs_i[104], block_out[21], block_out[17], 1'h0, right_tracks_out[62], up_tracks_fwd[34], 1'h0, inputs_i[105], block_out[21], block_out[17], 1'h0, right_tracks_out[61], up_tracks_fwd[35], 1'h0, inputs_i[105], block_out[21], block_out[17], 1'h0, right_tracks_out[60], up_tracks_fwd[36], 1'h0, inputs_i[106], block_out[21], block_out[17], 1'h0, right_tracks_out[59], up_tracks_fwd[37], 1'h0, inputs_i[106], block_out[21], block_out[17], 1'h0, right_tracks_out[58], up_tracks_fwd[38], 1'h0, inputs_i[107], block_out[21], block_out[17], 1'h0, right_tracks_out[57], up_tracks_fwd[39], 1'h0, inputs_i[107], block_out[21], block_out[17], 1'h0, right_tracks_out[56], up_tracks_fwd[40], 1'h0, inputs_i[108], block_out[21], block_out[17], 1'h0, right_tracks_out[55], up_tracks_fwd[41], 1'h0, inputs_i[108], block_out[21], block_out[17], 1'h0, right_tracks_out[54], up_tracks_fwd[42], 1'h0, inputs_i[109], block_out[21], block_out[17], 1'h0, right_tracks_out[53], up_tracks_fwd[43], 1'h0, inputs_i[109], block_out[21], block_out[17], 1'h0, right_tracks_out[52], up_tracks_fwd[44], 1'h0, inputs_i[110], block_out[21], block_out[17], 1'h0, right_tracks_out[51], up_tracks_fwd[45], 1'h0, inputs_i[110], block_out[21], block_out[17], 1'h0, right_tracks_out[50], up_tracks_fwd[46], 1'h0, inputs_i[111], block_out[21], block_out[17], 1'h0, right_tracks_out[49], up_tracks_fwd[47], 1'h0, inputs_i[111], block_out[21], block_out[17], 1'h0, right_tracks_out[32], up_tracks_fwd[16], 1'h0, inputs_i[112], block_out[13], block_out[9], 1'h0, right_tracks_out[47], up_tracks_fwd[17], 1'h0, inputs_i[112], block_out[13], block_out[9], 1'h0, right_tracks_out[46], up_tracks_fwd[18], 1'h0, inputs_i[113], block_out[13], block_out[9], 1'h0, right_tracks_out[45], up_tracks_fwd[19], 1'h0, inputs_i[113], block_out[13], block_out[9], 1'h0, right_tracks_out[44], up_tracks_fwd[20], 1'h0, inputs_i[114], block_out[13], block_out[9], 1'h0, right_tracks_out[43], up_tracks_fwd[21], 1'h0, inputs_i[114], block_out[13], block_out[9], 1'h0, right_tracks_out[42], up_tracks_fwd[22], 1'h0, inputs_i[115], block_out[13], block_out[9], 1'h0, right_tracks_out[41], up_tracks_fwd[23], 1'h0, inputs_i[115], block_out[13], block_out[9], 1'h0, right_tracks_out[40], up_tracks_fwd[24], 1'h0, inputs_i[116], block_out[13], block_out[9], 1'h0, right_tracks_out[39], up_tracks_fwd[25], 1'h0, inputs_i[116], block_out[13], block_out[9], 1'h0, right_tracks_out[38], up_tracks_fwd[26], 1'h0, inputs_i[117], block_out[13], block_out[9], 1'h0, right_tracks_out[37], up_tracks_fwd[27], 1'h0, inputs_i[117], block_out[13], block_out[9], 1'h0, right_tracks_out[36], up_tracks_fwd[28], 1'h0, inputs_i[118], block_out[13], block_out[9], 1'h0, right_tracks_out[35], up_tracks_fwd[29], 1'h0, inputs_i[118], block_out[13], block_out[9], 1'h0, right_tracks_out[34], up_tracks_fwd[30], 1'h0, inputs_i[119], block_out[13], block_out[9], 1'h0, right_tracks_out[33], up_tracks_fwd[31], 1'h0, inputs_i[119], block_out[13], block_out[9], 1'h0, right_tracks_out[16], up_tracks_fwd[0], 1'h0, inputs_i[120], block_out[5], block_out[1], 1'h0, right_tracks_out[31], up_tracks_fwd[1], 1'h0, inputs_i[120], block_out[5], block_out[1], 1'h0, right_tracks_out[30], up_tracks_fwd[2], 1'h0, inputs_i[121], block_out[5], block_out[1], 1'h0, right_tracks_out[29], up_tracks_fwd[3], 1'h0, inputs_i[121], block_out[5], block_out[1], 1'h0, right_tracks_out[28], up_tracks_fwd[4], 1'h0, inputs_i[122], block_out[5], block_out[1], 1'h0, right_tracks_out[27], up_tracks_fwd[5], 1'h0, inputs_i[122], block_out[5], block_out[1], 1'h0, right_tracks_out[26], up_tracks_fwd[6], 1'h0, inputs_i[123], block_out[5], block_out[1], 1'h0, right_tracks_out[25], up_tracks_fwd[7], 1'h0, inputs_i[123], block_out[5], block_out[1], 1'h0, right_tracks_out[24], up_tracks_fwd[8], 1'h0, inputs_i[124], block_out[5], block_out[1], 1'h0, right_tracks_out[23], up_tracks_fwd[9], 1'h0, inputs_i[124], block_out[5], block_out[1], 1'h0, right_tracks_out[22], up_tracks_fwd[10], 1'h0, inputs_i[125], block_out[5], block_out[1], 1'h0, right_tracks_out[21], up_tracks_fwd[11], 1'h0, inputs_i[125], block_out[5], block_out[1], 1'h0, right_tracks_out[20], up_tracks_fwd[12], 1'h0, inputs_i[126], block_out[5], block_out[1], 1'h0, right_tracks_out[19], up_tracks_fwd[13], 1'h0, inputs_i[126], block_out[5], block_out[1], 1'h0, right_tracks_out[18], up_tracks_fwd[14], 1'h0, inputs_i[127], block_out[5], block_out[1], 1'h0, right_tracks_out[17], up_tracks_fwd[15], 1'h0, inputs_i[127], block_out[5], block_out[1] }; |
| assign up_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2462 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3940 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5418 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6896 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8374 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9852 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11330 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12472 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13614 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14756 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15898 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17040 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18182 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19324 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19346 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20821 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22296 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23771 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25246 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26721 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28196 }; |
| assign down_tracks_in = { 1'h0, left_tracks_out[238], down_tracks_fwd[320], block_out[111], block_out[107], 1'h0, inputs_i[0], 1'h0, left_tracks_out[237], down_tracks_fwd[321], block_out[111], block_out[107], 1'h0, inputs_i[0], 1'h0, left_tracks_out[236], down_tracks_fwd[322], block_out[111], block_out[107], 1'h0, inputs_i[1], 1'h0, left_tracks_out[235], down_tracks_fwd[323], block_out[111], block_out[107], 1'h0, inputs_i[1], 1'h0, left_tracks_out[234], down_tracks_fwd[324], block_out[111], block_out[107], 1'h0, inputs_i[2], 1'h0, left_tracks_out[233], down_tracks_fwd[325], block_out[111], block_out[107], 1'h0, inputs_i[2], 1'h0, left_tracks_out[232], down_tracks_fwd[326], block_out[111], block_out[107], 1'h0, inputs_i[3], 1'h0, left_tracks_out[231], down_tracks_fwd[327], block_out[111], block_out[107], 1'h0, inputs_i[3], 1'h0, left_tracks_out[230], down_tracks_fwd[328], block_out[111], block_out[107], 1'h0, inputs_i[4], 1'h0, left_tracks_out[229], down_tracks_fwd[329], block_out[111], block_out[107], 1'h0, inputs_i[4], 1'h0, left_tracks_out[228], down_tracks_fwd[330], block_out[111], block_out[107], 1'h0, inputs_i[5], 1'h0, left_tracks_out[227], down_tracks_fwd[331], block_out[111], block_out[107], 1'h0, inputs_i[5], 1'h0, left_tracks_out[226], down_tracks_fwd[332], block_out[111], block_out[107], 1'h0, inputs_i[6], 1'h0, left_tracks_out[225], down_tracks_fwd[333], block_out[111], block_out[107], 1'h0, inputs_i[6], 1'h0, left_tracks_out[224], down_tracks_fwd[334], block_out[111], block_out[107], 1'h0, inputs_i[7], 1'h0, left_tracks_out[239], down_tracks_fwd[335], block_out[111], block_out[107], 1'h0, inputs_i[7], 1'h0, left_tracks_out[222], down_tracks_fwd[304], block_out[103], block_out[99], 1'h0, inputs_i[8], 1'h0, left_tracks_out[221], down_tracks_fwd[305], block_out[103], block_out[99], 1'h0, inputs_i[8], 1'h0, left_tracks_out[220], down_tracks_fwd[306], block_out[103], block_out[99], 1'h0, inputs_i[9], 1'h0, left_tracks_out[219], down_tracks_fwd[307], block_out[103], block_out[99], 1'h0, inputs_i[9], 1'h0, left_tracks_out[218], down_tracks_fwd[308], block_out[103], block_out[99], 1'h0, inputs_i[10], 1'h0, left_tracks_out[217], down_tracks_fwd[309], block_out[103], block_out[99], 1'h0, inputs_i[10], 1'h0, left_tracks_out[216], down_tracks_fwd[310], block_out[103], block_out[99], 1'h0, inputs_i[11], 1'h0, left_tracks_out[215], down_tracks_fwd[311], block_out[103], block_out[99], 1'h0, inputs_i[11], 1'h0, left_tracks_out[214], down_tracks_fwd[312], block_out[103], block_out[99], 1'h0, inputs_i[12], 1'h0, left_tracks_out[213], down_tracks_fwd[313], block_out[103], block_out[99], 1'h0, inputs_i[12], 1'h0, left_tracks_out[212], down_tracks_fwd[314], block_out[103], block_out[99], 1'h0, inputs_i[13], 1'h0, left_tracks_out[211], down_tracks_fwd[315], block_out[103], block_out[99], 1'h0, inputs_i[13], 1'h0, left_tracks_out[210], down_tracks_fwd[316], block_out[103], block_out[99], 1'h0, inputs_i[14], 1'h0, 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right_tracks_out[31], 1'h0, down_tracks_fwd[30], 1'h0, inputs_i[119], block_out[13], block_out[9], right_tracks_out[16], 1'h0, down_tracks_fwd[31], 1'h0, inputs_i[119], block_out[13], block_out[9], right_tracks_out[1], 1'h0, down_tracks_fwd[0], 1'h0, inputs_i[120], block_out[5], block_out[1], right_tracks_out[2], 1'h0, down_tracks_fwd[1], 1'h0, inputs_i[120], block_out[5], block_out[1], right_tracks_out[3], 1'h0, down_tracks_fwd[2], 1'h0, inputs_i[121], block_out[5], block_out[1], right_tracks_out[4], 1'h0, down_tracks_fwd[3], 1'h0, inputs_i[121], block_out[5], block_out[1], right_tracks_out[5], 1'h0, down_tracks_fwd[4], 1'h0, inputs_i[122], block_out[5], block_out[1], right_tracks_out[6], 1'h0, down_tracks_fwd[5], 1'h0, inputs_i[122], block_out[5], block_out[1], right_tracks_out[7], 1'h0, down_tracks_fwd[6], 1'h0, inputs_i[123], block_out[5], block_out[1], right_tracks_out[8], 1'h0, down_tracks_fwd[7], 1'h0, inputs_i[123], block_out[5], block_out[1], right_tracks_out[9], 1'h0, down_tracks_fwd[8], 1'h0, inputs_i[124], block_out[5], block_out[1], right_tracks_out[10], 1'h0, down_tracks_fwd[9], 1'h0, inputs_i[124], block_out[5], block_out[1], right_tracks_out[11], 1'h0, down_tracks_fwd[10], 1'h0, inputs_i[125], block_out[5], block_out[1], right_tracks_out[12], 1'h0, down_tracks_fwd[11], 1'h0, inputs_i[125], block_out[5], block_out[1], right_tracks_out[13], 1'h0, down_tracks_fwd[12], 1'h0, inputs_i[126], block_out[5], block_out[1], right_tracks_out[14], 1'h0, down_tracks_fwd[13], 1'h0, inputs_i[126], block_out[5], block_out[1], right_tracks_out[15], 1'h0, down_tracks_fwd[14], 1'h0, inputs_i[127], block_out[5], block_out[1], right_tracks_out[0], 1'h0, down_tracks_fwd[15], 1'h0, inputs_i[127], block_out[5], block_out[1] }; |
| assign down_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2472 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3950 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5428 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6906 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8384 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9862 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11340 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12482 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13624 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14766 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15908 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17050 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18192 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19334 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20809 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22284 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23759 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25234 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26709 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28184 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29659 }; |
| assign left_tracks_in = { down_tracks_out[208], 1'h0, left_tracks_fwd[240], 1'h0, inputs_i[128], block_out[110], block_out[106], down_tracks_out[223], 1'h0, left_tracks_fwd[241], 1'h0, inputs_i[128], block_out[110], block_out[106], down_tracks_out[222], 1'h0, left_tracks_fwd[242], 1'h0, inputs_i[129], block_out[110], block_out[106], down_tracks_out[221], 1'h0, left_tracks_fwd[243], 1'h0, inputs_i[129], block_out[110], block_out[106], down_tracks_out[220], 1'h0, left_tracks_fwd[244], 1'h0, inputs_i[130], block_out[110], block_out[106], down_tracks_out[219], 1'h0, left_tracks_fwd[245], 1'h0, inputs_i[130], block_out[110], block_out[106], down_tracks_out[218], 1'h0, left_tracks_fwd[246], 1'h0, inputs_i[131], block_out[110], block_out[106], down_tracks_out[217], 1'h0, left_tracks_fwd[247], 1'h0, inputs_i[131], block_out[110], block_out[106], down_tracks_out[216], 1'h0, left_tracks_fwd[248], 1'h0, inputs_i[132], block_out[110], block_out[106], down_tracks_out[215], 1'h0, left_tracks_fwd[249], 1'h0, inputs_i[132], block_out[110], block_out[106], down_tracks_out[214], 1'h0, left_tracks_fwd[250], 1'h0, inputs_i[133], block_out[110], block_out[106], down_tracks_out[213], 1'h0, left_tracks_fwd[251], 1'h0, inputs_i[133], block_out[110], block_out[106], down_tracks_out[212], 1'h0, left_tracks_fwd[252], 1'h0, inputs_i[134], block_out[110], block_out[106], down_tracks_out[211], 1'h0, left_tracks_fwd[253], 1'h0, inputs_i[134], block_out[110], block_out[106], down_tracks_out[210], 1'h0, left_tracks_fwd[254], 1'h0, inputs_i[135], block_out[110], block_out[106], down_tracks_out[209], 1'h0, left_tracks_fwd[255], 1'h0, inputs_i[135], block_out[110], block_out[106], down_tracks_out[192], up_tracks_out[223], left_tracks_fwd[224], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[207], up_tracks_out[208], left_tracks_fwd[225], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[206], up_tracks_out[209], left_tracks_fwd[226], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[205], up_tracks_out[210], left_tracks_fwd[227], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[204], up_tracks_out[211], left_tracks_fwd[228], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[203], up_tracks_out[212], left_tracks_fwd[229], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[202], up_tracks_out[213], left_tracks_fwd[230], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[201], up_tracks_out[214], left_tracks_fwd[231], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[200], up_tracks_out[215], left_tracks_fwd[232], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[199], up_tracks_out[216], left_tracks_fwd[233], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[198], up_tracks_out[217], left_tracks_fwd[234], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[197], up_tracks_out[218], left_tracks_fwd[235], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[196], up_tracks_out[219], left_tracks_fwd[236], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[195], up_tracks_out[220], left_tracks_fwd[237], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[194], up_tracks_out[221], left_tracks_fwd[238], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[193], up_tracks_out[222], left_tracks_fwd[239], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[176], up_tracks_out[207], left_tracks_fwd[208], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[191], up_tracks_out[192], left_tracks_fwd[209], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[190], up_tracks_out[193], left_tracks_fwd[210], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[189], up_tracks_out[194], left_tracks_fwd[211], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[188], up_tracks_out[195], left_tracks_fwd[212], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[187], up_tracks_out[196], left_tracks_fwd[213], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[186], up_tracks_out[197], left_tracks_fwd[214], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[185], up_tracks_out[198], left_tracks_fwd[215], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[184], up_tracks_out[199], left_tracks_fwd[216], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[183], up_tracks_out[200], left_tracks_fwd[217], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[182], up_tracks_out[201], left_tracks_fwd[218], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[181], up_tracks_out[202], left_tracks_fwd[219], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[180], up_tracks_out[203], left_tracks_fwd[220], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[179], up_tracks_out[204], left_tracks_fwd[221], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[178], up_tracks_out[205], left_tracks_fwd[222], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[177], up_tracks_out[206], left_tracks_fwd[223], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[160], up_tracks_out[191], left_tracks_fwd[192], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[175], up_tracks_out[176], left_tracks_fwd[193], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[174], up_tracks_out[177], left_tracks_fwd[194], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[173], up_tracks_out[178], left_tracks_fwd[195], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[172], up_tracks_out[179], left_tracks_fwd[196], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[171], up_tracks_out[180], left_tracks_fwd[197], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[170], up_tracks_out[181], left_tracks_fwd[198], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[169], up_tracks_out[182], left_tracks_fwd[199], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[168], up_tracks_out[183], left_tracks_fwd[200], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[167], up_tracks_out[184], left_tracks_fwd[201], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[166], up_tracks_out[185], left_tracks_fwd[202], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[165], up_tracks_out[186], left_tracks_fwd[203], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[164], up_tracks_out[187], left_tracks_fwd[204], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[163], up_tracks_out[188], left_tracks_fwd[205], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[162], up_tracks_out[189], left_tracks_fwd[206], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[161], up_tracks_out[190], left_tracks_fwd[207], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[144], up_tracks_out[175], left_tracks_fwd[176], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[159], up_tracks_out[160], left_tracks_fwd[177], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[158], up_tracks_out[161], left_tracks_fwd[178], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[157], up_tracks_out[162], left_tracks_fwd[179], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[156], up_tracks_out[163], left_tracks_fwd[180], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[155], up_tracks_out[164], left_tracks_fwd[181], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[154], up_tracks_out[165], left_tracks_fwd[182], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[153], up_tracks_out[166], left_tracks_fwd[183], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[152], up_tracks_out[167], left_tracks_fwd[184], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[151], up_tracks_out[168], left_tracks_fwd[185], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[150], up_tracks_out[169], left_tracks_fwd[186], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[149], up_tracks_out[170], left_tracks_fwd[187], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[148], up_tracks_out[171], left_tracks_fwd[188], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[147], up_tracks_out[172], left_tracks_fwd[189], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[146], up_tracks_out[173], left_tracks_fwd[190], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[145], up_tracks_out[174], left_tracks_fwd[191], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[128], up_tracks_out[159], left_tracks_fwd[160], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[143], up_tracks_out[144], left_tracks_fwd[161], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[142], up_tracks_out[145], left_tracks_fwd[162], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[141], up_tracks_out[146], left_tracks_fwd[163], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[140], up_tracks_out[147], left_tracks_fwd[164], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[139], up_tracks_out[148], left_tracks_fwd[165], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[138], up_tracks_out[149], left_tracks_fwd[166], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[137], up_tracks_out[150], left_tracks_fwd[167], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[136], up_tracks_out[151], left_tracks_fwd[168], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[135], up_tracks_out[152], left_tracks_fwd[169], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[134], up_tracks_out[153], left_tracks_fwd[170], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[133], up_tracks_out[154], left_tracks_fwd[171], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[132], up_tracks_out[155], left_tracks_fwd[172], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[131], up_tracks_out[156], left_tracks_fwd[173], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[130], up_tracks_out[157], left_tracks_fwd[174], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[129], up_tracks_out[158], left_tracks_fwd[175], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[112], up_tracks_out[143], left_tracks_fwd[144], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[127], up_tracks_out[128], left_tracks_fwd[145], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[126], up_tracks_out[129], left_tracks_fwd[146], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[125], up_tracks_out[130], left_tracks_fwd[147], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[124], up_tracks_out[131], left_tracks_fwd[148], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[123], up_tracks_out[132], left_tracks_fwd[149], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[122], up_tracks_out[133], left_tracks_fwd[150], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[121], up_tracks_out[134], left_tracks_fwd[151], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[120], up_tracks_out[135], left_tracks_fwd[152], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[119], up_tracks_out[136], left_tracks_fwd[153], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[118], up_tracks_out[137], left_tracks_fwd[154], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[117], up_tracks_out[138], left_tracks_fwd[155], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[116], up_tracks_out[139], left_tracks_fwd[156], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[115], up_tracks_out[140], left_tracks_fwd[157], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[114], up_tracks_out[141], left_tracks_fwd[158], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[113], up_tracks_out[142], left_tracks_fwd[159], block_out[68], block_out[64], block_out[62], block_out[58], 1'h0, up_tracks_out[127], left_tracks_fwd[128], block_out[60], block_out[56], 1'h0, inputs_i[56], 1'h0, up_tracks_out[112], left_tracks_fwd[129], block_out[60], block_out[56], 1'h0, inputs_i[56], 1'h0, up_tracks_out[113], left_tracks_fwd[130], block_out[60], block_out[56], 1'h0, inputs_i[57], 1'h0, up_tracks_out[114], left_tracks_fwd[131], block_out[60], block_out[56], 1'h0, inputs_i[57], 1'h0, up_tracks_out[115], left_tracks_fwd[132], block_out[60], block_out[56], 1'h0, inputs_i[58], 1'h0, up_tracks_out[116], left_tracks_fwd[133], block_out[60], block_out[56], 1'h0, inputs_i[58], 1'h0, up_tracks_out[117], left_tracks_fwd[134], block_out[60], block_out[56], 1'h0, inputs_i[59], 1'h0, up_tracks_out[118], left_tracks_fwd[135], block_out[60], block_out[56], 1'h0, inputs_i[59], 1'h0, up_tracks_out[119], left_tracks_fwd[136], block_out[60], block_out[56], 1'h0, inputs_i[60], 1'h0, up_tracks_out[120], left_tracks_fwd[137], block_out[60], block_out[56], 1'h0, inputs_i[60], 1'h0, up_tracks_out[121], left_tracks_fwd[138], block_out[60], block_out[56], 1'h0, inputs_i[61], 1'h0, up_tracks_out[122], left_tracks_fwd[139], block_out[60], block_out[56], 1'h0, inputs_i[61], 1'h0, up_tracks_out[123], left_tracks_fwd[140], block_out[60], block_out[56], 1'h0, inputs_i[62], 1'h0, up_tracks_out[124], left_tracks_fwd[141], block_out[60], block_out[56], 1'h0, inputs_i[62], 1'h0, up_tracks_out[125], left_tracks_fwd[142], block_out[60], block_out[56], 1'h0, inputs_i[63], 1'h0, up_tracks_out[126], left_tracks_fwd[143], block_out[60], block_out[56], 1'h0, inputs_i[63], down_tracks_out[96], 1'h0, left_tracks_fwd[112], 1'h0, inputs_i[136], block_out[54], block_out[50], down_tracks_out[111], 1'h0, left_tracks_fwd[113], 1'h0, inputs_i[136], block_out[54], block_out[50], down_tracks_out[110], 1'h0, left_tracks_fwd[114], 1'h0, inputs_i[137], block_out[54], block_out[50], down_tracks_out[109], 1'h0, left_tracks_fwd[115], 1'h0, inputs_i[137], block_out[54], block_out[50], down_tracks_out[108], 1'h0, left_tracks_fwd[116], 1'h0, inputs_i[138], block_out[54], block_out[50], down_tracks_out[107], 1'h0, left_tracks_fwd[117], 1'h0, inputs_i[138], block_out[54], block_out[50], down_tracks_out[106], 1'h0, left_tracks_fwd[118], 1'h0, inputs_i[139], block_out[54], block_out[50], down_tracks_out[105], 1'h0, left_tracks_fwd[119], 1'h0, inputs_i[139], block_out[54], block_out[50], down_tracks_out[104], 1'h0, left_tracks_fwd[120], 1'h0, inputs_i[140], block_out[54], block_out[50], down_tracks_out[103], 1'h0, left_tracks_fwd[121], 1'h0, inputs_i[140], block_out[54], block_out[50], down_tracks_out[102], 1'h0, left_tracks_fwd[122], 1'h0, inputs_i[141], block_out[54], block_out[50], down_tracks_out[101], 1'h0, left_tracks_fwd[123], 1'h0, inputs_i[141], block_out[54], block_out[50], down_tracks_out[100], 1'h0, left_tracks_fwd[124], 1'h0, inputs_i[142], block_out[54], block_out[50], down_tracks_out[99], 1'h0, left_tracks_fwd[125], 1'h0, inputs_i[142], block_out[54], block_out[50], down_tracks_out[98], 1'h0, left_tracks_fwd[126], 1'h0, inputs_i[143], block_out[54], block_out[50], down_tracks_out[97], 1'h0, left_tracks_fwd[127], 1'h0, inputs_i[143], block_out[54], block_out[50], down_tracks_out[80], up_tracks_out[111], left_tracks_fwd[96], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[95], up_tracks_out[96], left_tracks_fwd[97], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[94], up_tracks_out[97], left_tracks_fwd[98], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[93], up_tracks_out[98], left_tracks_fwd[99], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[92], up_tracks_out[99], left_tracks_fwd[100], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[91], up_tracks_out[100], left_tracks_fwd[101], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[90], up_tracks_out[101], left_tracks_fwd[102], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[89], up_tracks_out[102], left_tracks_fwd[103], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[88], up_tracks_out[103], left_tracks_fwd[104], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[87], up_tracks_out[104], left_tracks_fwd[105], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[86], up_tracks_out[105], left_tracks_fwd[106], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[85], up_tracks_out[106], left_tracks_fwd[107], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[84], up_tracks_out[107], left_tracks_fwd[108], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[83], up_tracks_out[108], left_tracks_fwd[109], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[82], up_tracks_out[109], left_tracks_fwd[110], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[81], up_tracks_out[110], left_tracks_fwd[111], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[64], up_tracks_out[95], left_tracks_fwd[80], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[79], up_tracks_out[80], left_tracks_fwd[81], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[78], up_tracks_out[81], left_tracks_fwd[82], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[77], up_tracks_out[82], left_tracks_fwd[83], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[76], up_tracks_out[83], left_tracks_fwd[84], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[75], up_tracks_out[84], left_tracks_fwd[85], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[74], up_tracks_out[85], left_tracks_fwd[86], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[73], up_tracks_out[86], left_tracks_fwd[87], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[72], up_tracks_out[87], left_tracks_fwd[88], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[71], up_tracks_out[88], left_tracks_fwd[89], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[70], up_tracks_out[89], left_tracks_fwd[90], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[69], up_tracks_out[90], left_tracks_fwd[91], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[68], up_tracks_out[91], left_tracks_fwd[92], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[67], up_tracks_out[92], left_tracks_fwd[93], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[66], up_tracks_out[93], left_tracks_fwd[94], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[65], up_tracks_out[94], left_tracks_fwd[95], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[48], up_tracks_out[79], left_tracks_fwd[64], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[63], up_tracks_out[64], left_tracks_fwd[65], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[62], up_tracks_out[65], left_tracks_fwd[66], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[61], up_tracks_out[66], left_tracks_fwd[67], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[60], up_tracks_out[67], left_tracks_fwd[68], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[59], up_tracks_out[68], left_tracks_fwd[69], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[58], up_tracks_out[69], left_tracks_fwd[70], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[57], up_tracks_out[70], left_tracks_fwd[71], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[56], up_tracks_out[71], left_tracks_fwd[72], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[55], up_tracks_out[72], left_tracks_fwd[73], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[54], up_tracks_out[73], left_tracks_fwd[74], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[53], up_tracks_out[74], left_tracks_fwd[75], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[52], up_tracks_out[75], left_tracks_fwd[76], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[51], up_tracks_out[76], left_tracks_fwd[77], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[50], up_tracks_out[77], left_tracks_fwd[78], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[49], up_tracks_out[78], left_tracks_fwd[79], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[32], up_tracks_out[63], left_tracks_fwd[48], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[47], up_tracks_out[48], left_tracks_fwd[49], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[46], up_tracks_out[49], left_tracks_fwd[50], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[45], up_tracks_out[50], left_tracks_fwd[51], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[44], up_tracks_out[51], left_tracks_fwd[52], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[43], up_tracks_out[52], left_tracks_fwd[53], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[42], up_tracks_out[53], left_tracks_fwd[54], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[41], up_tracks_out[54], left_tracks_fwd[55], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[40], up_tracks_out[55], left_tracks_fwd[56], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[39], up_tracks_out[56], left_tracks_fwd[57], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[38], up_tracks_out[57], left_tracks_fwd[58], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[37], up_tracks_out[58], left_tracks_fwd[59], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[36], up_tracks_out[59], left_tracks_fwd[60], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[35], up_tracks_out[60], left_tracks_fwd[61], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[34], up_tracks_out[61], left_tracks_fwd[62], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[33], up_tracks_out[62], left_tracks_fwd[63], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[16], up_tracks_out[47], left_tracks_fwd[32], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[31], up_tracks_out[32], left_tracks_fwd[33], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[30], up_tracks_out[33], left_tracks_fwd[34], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[29], up_tracks_out[34], left_tracks_fwd[35], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[28], up_tracks_out[35], left_tracks_fwd[36], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[27], up_tracks_out[36], left_tracks_fwd[37], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[26], up_tracks_out[37], left_tracks_fwd[38], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[25], up_tracks_out[38], left_tracks_fwd[39], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[24], up_tracks_out[39], left_tracks_fwd[40], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[23], up_tracks_out[40], left_tracks_fwd[41], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[22], up_tracks_out[41], left_tracks_fwd[42], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[21], up_tracks_out[42], left_tracks_fwd[43], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[20], up_tracks_out[43], left_tracks_fwd[44], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[19], up_tracks_out[44], left_tracks_fwd[45], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[18], up_tracks_out[45], left_tracks_fwd[46], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[17], up_tracks_out[46], left_tracks_fwd[47], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[0], up_tracks_out[31], left_tracks_fwd[16], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[15], up_tracks_out[16], left_tracks_fwd[17], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[14], up_tracks_out[17], left_tracks_fwd[18], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[13], up_tracks_out[18], left_tracks_fwd[19], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[12], up_tracks_out[19], left_tracks_fwd[20], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[11], up_tracks_out[20], left_tracks_fwd[21], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[10], up_tracks_out[21], left_tracks_fwd[22], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[9], up_tracks_out[22], left_tracks_fwd[23], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[8], up_tracks_out[23], left_tracks_fwd[24], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[7], up_tracks_out[24], left_tracks_fwd[25], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[6], up_tracks_out[25], left_tracks_fwd[26], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[5], up_tracks_out[26], left_tracks_fwd[27], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[4], up_tracks_out[27], left_tracks_fwd[28], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[3], up_tracks_out[28], left_tracks_fwd[29], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[2], up_tracks_out[29], left_tracks_fwd[30], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[1], up_tracks_out[30], left_tracks_fwd[31], block_out[12], block_out[8], block_out[6], block_out[2], 1'h0, up_tracks_out[15], left_tracks_fwd[0], block_out[4], block_out[0], 1'h0, inputs_i[64], 1'h0, up_tracks_out[0], left_tracks_fwd[1], block_out[4], block_out[0], 1'h0, inputs_i[64], 1'h0, up_tracks_out[1], left_tracks_fwd[2], block_out[4], block_out[0], 1'h0, inputs_i[65], 1'h0, up_tracks_out[2], left_tracks_fwd[3], block_out[4], block_out[0], 1'h0, inputs_i[65], 1'h0, up_tracks_out[3], left_tracks_fwd[4], block_out[4], block_out[0], 1'h0, inputs_i[66], 1'h0, up_tracks_out[4], left_tracks_fwd[5], block_out[4], block_out[0], 1'h0, inputs_i[66], 1'h0, up_tracks_out[5], left_tracks_fwd[6], block_out[4], block_out[0], 1'h0, inputs_i[67], 1'h0, up_tracks_out[6], left_tracks_fwd[7], block_out[4], block_out[0], 1'h0, inputs_i[67], 1'h0, up_tracks_out[7], left_tracks_fwd[8], block_out[4], block_out[0], 1'h0, inputs_i[68], 1'h0, up_tracks_out[8], left_tracks_fwd[9], block_out[4], block_out[0], 1'h0, inputs_i[68], 1'h0, up_tracks_out[9], left_tracks_fwd[10], block_out[4], block_out[0], 1'h0, inputs_i[69], 1'h0, up_tracks_out[10], left_tracks_fwd[11], block_out[4], block_out[0], 1'h0, inputs_i[69], 1'h0, up_tracks_out[11], left_tracks_fwd[12], block_out[4], block_out[0], 1'h0, inputs_i[70], 1'h0, up_tracks_out[12], left_tracks_fwd[13], block_out[4], block_out[0], 1'h0, inputs_i[70], 1'h0, up_tracks_out[13], left_tracks_fwd[14], block_out[4], block_out[0], 1'h0, inputs_i[71], 1'h0, up_tracks_out[14], left_tracks_fwd[15], block_out[4], block_out[0], 1'h0, inputs_i[71] }; |
| assign left_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31127 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32269 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33411 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34553 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35695 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36837 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37979 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:38001 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40932 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42074 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43216 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44358 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45500 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46642 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47784 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47806 }; |
| assign right_tracks_in = { 1'h0, down_tracks_out[335], right_tracks_fwd[240], 1'h0, inputs_i[128], block_out[110], block_out[106], 1'h0, down_tracks_out[320], right_tracks_fwd[241], 1'h0, inputs_i[128], block_out[110], block_out[106], 1'h0, down_tracks_out[321], right_tracks_fwd[242], 1'h0, inputs_i[129], block_out[110], block_out[106], 1'h0, down_tracks_out[322], right_tracks_fwd[243], 1'h0, inputs_i[129], block_out[110], block_out[106], 1'h0, down_tracks_out[323], right_tracks_fwd[244], 1'h0, inputs_i[130], block_out[110], block_out[106], 1'h0, down_tracks_out[324], right_tracks_fwd[245], 1'h0, inputs_i[130], block_out[110], block_out[106], 1'h0, down_tracks_out[325], right_tracks_fwd[246], 1'h0, inputs_i[131], block_out[110], block_out[106], 1'h0, down_tracks_out[326], right_tracks_fwd[247], 1'h0, inputs_i[131], block_out[110], block_out[106], 1'h0, down_tracks_out[327], right_tracks_fwd[248], 1'h0, inputs_i[132], block_out[110], block_out[106], 1'h0, down_tracks_out[328], right_tracks_fwd[249], 1'h0, inputs_i[132], block_out[110], block_out[106], 1'h0, down_tracks_out[329], right_tracks_fwd[250], 1'h0, inputs_i[133], block_out[110], block_out[106], 1'h0, down_tracks_out[330], right_tracks_fwd[251], 1'h0, inputs_i[133], block_out[110], block_out[106], 1'h0, down_tracks_out[331], right_tracks_fwd[252], 1'h0, inputs_i[134], block_out[110], block_out[106], 1'h0, down_tracks_out[332], right_tracks_fwd[253], 1'h0, inputs_i[134], block_out[110], block_out[106], 1'h0, down_tracks_out[333], right_tracks_fwd[254], 1'h0, inputs_i[135], block_out[110], block_out[106], 1'h0, down_tracks_out[334], right_tracks_fwd[255], 1'h0, inputs_i[135], block_out[110], block_out[106], up_tracks_out[334], down_tracks_out[319], right_tracks_fwd[224], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[333], down_tracks_out[304], right_tracks_fwd[225], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[332], down_tracks_out[305], right_tracks_fwd[226], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[331], down_tracks_out[306], right_tracks_fwd[227], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[330], down_tracks_out[307], right_tracks_fwd[228], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[329], down_tracks_out[308], right_tracks_fwd[229], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[328], down_tracks_out[309], right_tracks_fwd[230], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[327], down_tracks_out[310], right_tracks_fwd[231], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[326], down_tracks_out[311], right_tracks_fwd[232], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[325], down_tracks_out[312], right_tracks_fwd[233], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[324], down_tracks_out[313], right_tracks_fwd[234], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[323], down_tracks_out[314], right_tracks_fwd[235], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[322], down_tracks_out[315], right_tracks_fwd[236], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[321], down_tracks_out[316], right_tracks_fwd[237], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[320], down_tracks_out[317], right_tracks_fwd[238], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[335], down_tracks_out[318], right_tracks_fwd[239], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[318], down_tracks_out[303], right_tracks_fwd[208], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[317], down_tracks_out[288], right_tracks_fwd[209], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[316], down_tracks_out[289], right_tracks_fwd[210], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[315], down_tracks_out[290], right_tracks_fwd[211], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[314], down_tracks_out[291], right_tracks_fwd[212], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[313], down_tracks_out[292], right_tracks_fwd[213], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[312], down_tracks_out[293], right_tracks_fwd[214], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[311], down_tracks_out[294], right_tracks_fwd[215], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[310], down_tracks_out[295], right_tracks_fwd[216], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[309], down_tracks_out[296], right_tracks_fwd[217], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[308], down_tracks_out[297], right_tracks_fwd[218], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[307], down_tracks_out[298], right_tracks_fwd[219], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[306], down_tracks_out[299], right_tracks_fwd[220], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[305], down_tracks_out[300], right_tracks_fwd[221], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[304], down_tracks_out[301], right_tracks_fwd[222], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[319], down_tracks_out[302], right_tracks_fwd[223], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[302], down_tracks_out[287], right_tracks_fwd[192], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[301], down_tracks_out[272], right_tracks_fwd[193], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[300], down_tracks_out[273], right_tracks_fwd[194], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[299], down_tracks_out[274], right_tracks_fwd[195], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[298], down_tracks_out[275], right_tracks_fwd[196], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[297], down_tracks_out[276], right_tracks_fwd[197], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[296], down_tracks_out[277], right_tracks_fwd[198], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[295], down_tracks_out[278], right_tracks_fwd[199], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[294], down_tracks_out[279], right_tracks_fwd[200], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[293], down_tracks_out[280], right_tracks_fwd[201], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[292], down_tracks_out[281], right_tracks_fwd[202], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[291], down_tracks_out[282], right_tracks_fwd[203], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[290], down_tracks_out[283], right_tracks_fwd[204], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[289], down_tracks_out[284], right_tracks_fwd[205], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[288], down_tracks_out[285], right_tracks_fwd[206], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[303], down_tracks_out[286], right_tracks_fwd[207], block_out[92], block_out[88], block_out[86], block_out[82], up_tracks_out[286], down_tracks_out[271], right_tracks_fwd[176], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[285], down_tracks_out[256], right_tracks_fwd[177], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[284], down_tracks_out[257], right_tracks_fwd[178], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[283], down_tracks_out[258], right_tracks_fwd[179], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[282], down_tracks_out[259], right_tracks_fwd[180], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[281], down_tracks_out[260], right_tracks_fwd[181], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[280], down_tracks_out[261], right_tracks_fwd[182], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[279], down_tracks_out[262], right_tracks_fwd[183], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[278], down_tracks_out[263], right_tracks_fwd[184], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[277], down_tracks_out[264], right_tracks_fwd[185], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[276], down_tracks_out[265], right_tracks_fwd[186], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[275], down_tracks_out[266], right_tracks_fwd[187], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[274], down_tracks_out[267], right_tracks_fwd[188], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[273], down_tracks_out[268], right_tracks_fwd[189], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[272], down_tracks_out[269], right_tracks_fwd[190], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[287], down_tracks_out[270], right_tracks_fwd[191], block_out[84], block_out[80], block_out[78], block_out[74], up_tracks_out[270], down_tracks_out[255], right_tracks_fwd[160], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[269], down_tracks_out[240], right_tracks_fwd[161], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[268], down_tracks_out[241], right_tracks_fwd[162], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[267], down_tracks_out[242], right_tracks_fwd[163], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[266], down_tracks_out[243], right_tracks_fwd[164], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[265], down_tracks_out[244], right_tracks_fwd[165], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[264], down_tracks_out[245], right_tracks_fwd[166], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[263], down_tracks_out[246], right_tracks_fwd[167], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[262], down_tracks_out[247], right_tracks_fwd[168], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[261], down_tracks_out[248], right_tracks_fwd[169], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[260], down_tracks_out[249], right_tracks_fwd[170], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[259], down_tracks_out[250], right_tracks_fwd[171], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[258], down_tracks_out[251], right_tracks_fwd[172], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[257], down_tracks_out[252], right_tracks_fwd[173], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[256], down_tracks_out[253], right_tracks_fwd[174], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[271], down_tracks_out[254], right_tracks_fwd[175], block_out[76], block_out[72], block_out[70], block_out[66], up_tracks_out[254], down_tracks_out[239], right_tracks_fwd[144], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[253], down_tracks_out[224], right_tracks_fwd[145], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[252], down_tracks_out[225], right_tracks_fwd[146], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[251], down_tracks_out[226], right_tracks_fwd[147], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[250], down_tracks_out[227], right_tracks_fwd[148], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[249], down_tracks_out[228], right_tracks_fwd[149], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[248], down_tracks_out[229], right_tracks_fwd[150], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[247], down_tracks_out[230], right_tracks_fwd[151], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[246], down_tracks_out[231], right_tracks_fwd[152], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[245], down_tracks_out[232], right_tracks_fwd[153], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[244], down_tracks_out[233], right_tracks_fwd[154], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[243], down_tracks_out[234], right_tracks_fwd[155], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[242], down_tracks_out[235], right_tracks_fwd[156], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[241], down_tracks_out[236], right_tracks_fwd[157], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[240], down_tracks_out[237], right_tracks_fwd[158], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[255], down_tracks_out[238], right_tracks_fwd[159], block_out[68], block_out[64], block_out[62], block_out[58], up_tracks_out[238], 1'h0, right_tracks_fwd[128], block_out[60], block_out[56], 1'h0, inputs_i[56], up_tracks_out[237], 1'h0, right_tracks_fwd[129], block_out[60], block_out[56], 1'h0, inputs_i[56], up_tracks_out[236], 1'h0, right_tracks_fwd[130], block_out[60], block_out[56], 1'h0, inputs_i[57], up_tracks_out[235], 1'h0, right_tracks_fwd[131], block_out[60], block_out[56], 1'h0, inputs_i[57], up_tracks_out[234], 1'h0, right_tracks_fwd[132], block_out[60], block_out[56], 1'h0, inputs_i[58], up_tracks_out[233], 1'h0, right_tracks_fwd[133], block_out[60], block_out[56], 1'h0, inputs_i[58], up_tracks_out[232], 1'h0, right_tracks_fwd[134], block_out[60], block_out[56], 1'h0, inputs_i[59], up_tracks_out[231], 1'h0, right_tracks_fwd[135], block_out[60], block_out[56], 1'h0, inputs_i[59], up_tracks_out[230], 1'h0, right_tracks_fwd[136], block_out[60], block_out[56], 1'h0, inputs_i[60], up_tracks_out[229], 1'h0, right_tracks_fwd[137], block_out[60], block_out[56], 1'h0, inputs_i[60], up_tracks_out[228], 1'h0, right_tracks_fwd[138], block_out[60], block_out[56], 1'h0, inputs_i[61], up_tracks_out[227], 1'h0, right_tracks_fwd[139], block_out[60], block_out[56], 1'h0, inputs_i[61], up_tracks_out[226], 1'h0, right_tracks_fwd[140], block_out[60], block_out[56], 1'h0, inputs_i[62], up_tracks_out[225], 1'h0, right_tracks_fwd[141], block_out[60], block_out[56], 1'h0, inputs_i[62], up_tracks_out[224], 1'h0, right_tracks_fwd[142], block_out[60], block_out[56], 1'h0, inputs_i[63], up_tracks_out[239], 1'h0, right_tracks_fwd[143], block_out[60], block_out[56], 1'h0, inputs_i[63], 1'h0, down_tracks_out[223], right_tracks_fwd[112], 1'h0, inputs_i[136], block_out[54], block_out[50], 1'h0, down_tracks_out[208], right_tracks_fwd[113], 1'h0, inputs_i[136], block_out[54], block_out[50], 1'h0, down_tracks_out[209], right_tracks_fwd[114], 1'h0, inputs_i[137], block_out[54], block_out[50], 1'h0, down_tracks_out[210], right_tracks_fwd[115], 1'h0, inputs_i[137], block_out[54], block_out[50], 1'h0, down_tracks_out[211], right_tracks_fwd[116], 1'h0, inputs_i[138], block_out[54], block_out[50], 1'h0, down_tracks_out[212], right_tracks_fwd[117], 1'h0, inputs_i[138], block_out[54], block_out[50], 1'h0, down_tracks_out[213], right_tracks_fwd[118], 1'h0, inputs_i[139], block_out[54], block_out[50], 1'h0, down_tracks_out[214], right_tracks_fwd[119], 1'h0, inputs_i[139], block_out[54], block_out[50], 1'h0, down_tracks_out[215], right_tracks_fwd[120], 1'h0, inputs_i[140], block_out[54], block_out[50], 1'h0, down_tracks_out[216], right_tracks_fwd[121], 1'h0, inputs_i[140], block_out[54], block_out[50], 1'h0, down_tracks_out[217], right_tracks_fwd[122], 1'h0, inputs_i[141], block_out[54], block_out[50], 1'h0, down_tracks_out[218], right_tracks_fwd[123], 1'h0, inputs_i[141], block_out[54], block_out[50], 1'h0, down_tracks_out[219], right_tracks_fwd[124], 1'h0, inputs_i[142], block_out[54], block_out[50], 1'h0, down_tracks_out[220], right_tracks_fwd[125], 1'h0, inputs_i[142], block_out[54], block_out[50], 1'h0, down_tracks_out[221], right_tracks_fwd[126], 1'h0, inputs_i[143], block_out[54], block_out[50], 1'h0, down_tracks_out[222], right_tracks_fwd[127], 1'h0, inputs_i[143], block_out[54], block_out[50], up_tracks_out[222], down_tracks_out[207], right_tracks_fwd[96], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[221], down_tracks_out[192], right_tracks_fwd[97], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[220], down_tracks_out[193], right_tracks_fwd[98], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[219], down_tracks_out[194], right_tracks_fwd[99], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[218], down_tracks_out[195], right_tracks_fwd[100], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[217], down_tracks_out[196], right_tracks_fwd[101], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[216], down_tracks_out[197], right_tracks_fwd[102], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[215], down_tracks_out[198], right_tracks_fwd[103], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[214], down_tracks_out[199], right_tracks_fwd[104], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[213], down_tracks_out[200], right_tracks_fwd[105], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[212], down_tracks_out[201], right_tracks_fwd[106], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[211], down_tracks_out[202], right_tracks_fwd[107], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[210], down_tracks_out[203], right_tracks_fwd[108], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[209], down_tracks_out[204], right_tracks_fwd[109], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[208], down_tracks_out[205], right_tracks_fwd[110], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[223], down_tracks_out[206], right_tracks_fwd[111], block_out[52], block_out[48], block_out[46], block_out[42], up_tracks_out[206], down_tracks_out[191], right_tracks_fwd[80], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[205], down_tracks_out[176], right_tracks_fwd[81], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[204], down_tracks_out[177], right_tracks_fwd[82], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[203], down_tracks_out[178], right_tracks_fwd[83], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[202], down_tracks_out[179], right_tracks_fwd[84], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[201], down_tracks_out[180], right_tracks_fwd[85], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[200], down_tracks_out[181], right_tracks_fwd[86], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[199], down_tracks_out[182], right_tracks_fwd[87], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[198], down_tracks_out[183], right_tracks_fwd[88], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[197], down_tracks_out[184], right_tracks_fwd[89], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[196], down_tracks_out[185], right_tracks_fwd[90], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[195], down_tracks_out[186], right_tracks_fwd[91], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[194], down_tracks_out[187], right_tracks_fwd[92], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[193], down_tracks_out[188], right_tracks_fwd[93], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[192], down_tracks_out[189], right_tracks_fwd[94], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[207], down_tracks_out[190], right_tracks_fwd[95], block_out[44], block_out[40], block_out[38], block_out[34], up_tracks_out[190], down_tracks_out[175], right_tracks_fwd[64], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[189], down_tracks_out[160], right_tracks_fwd[65], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[188], down_tracks_out[161], right_tracks_fwd[66], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[187], down_tracks_out[162], right_tracks_fwd[67], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[186], down_tracks_out[163], right_tracks_fwd[68], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[185], down_tracks_out[164], right_tracks_fwd[69], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[184], down_tracks_out[165], right_tracks_fwd[70], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[183], down_tracks_out[166], right_tracks_fwd[71], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[182], down_tracks_out[167], right_tracks_fwd[72], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[181], down_tracks_out[168], right_tracks_fwd[73], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[180], down_tracks_out[169], right_tracks_fwd[74], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[179], down_tracks_out[170], right_tracks_fwd[75], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[178], down_tracks_out[171], right_tracks_fwd[76], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[177], down_tracks_out[172], right_tracks_fwd[77], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[176], down_tracks_out[173], right_tracks_fwd[78], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[191], down_tracks_out[174], right_tracks_fwd[79], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[174], down_tracks_out[159], right_tracks_fwd[48], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[173], down_tracks_out[144], right_tracks_fwd[49], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[172], down_tracks_out[145], right_tracks_fwd[50], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[171], down_tracks_out[146], right_tracks_fwd[51], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[170], down_tracks_out[147], right_tracks_fwd[52], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[169], down_tracks_out[148], right_tracks_fwd[53], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[168], down_tracks_out[149], right_tracks_fwd[54], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[167], down_tracks_out[150], right_tracks_fwd[55], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[166], down_tracks_out[151], right_tracks_fwd[56], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[165], down_tracks_out[152], right_tracks_fwd[57], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[164], down_tracks_out[153], right_tracks_fwd[58], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[163], down_tracks_out[154], right_tracks_fwd[59], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[162], down_tracks_out[155], right_tracks_fwd[60], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[161], down_tracks_out[156], right_tracks_fwd[61], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[160], down_tracks_out[157], right_tracks_fwd[62], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[175], down_tracks_out[158], right_tracks_fwd[63], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[158], down_tracks_out[143], right_tracks_fwd[32], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[157], down_tracks_out[128], right_tracks_fwd[33], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[156], down_tracks_out[129], right_tracks_fwd[34], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[155], down_tracks_out[130], right_tracks_fwd[35], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[154], down_tracks_out[131], right_tracks_fwd[36], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[153], down_tracks_out[132], right_tracks_fwd[37], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[152], down_tracks_out[133], right_tracks_fwd[38], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[151], down_tracks_out[134], right_tracks_fwd[39], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[150], down_tracks_out[135], right_tracks_fwd[40], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[149], down_tracks_out[136], right_tracks_fwd[41], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[148], down_tracks_out[137], right_tracks_fwd[42], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[147], down_tracks_out[138], right_tracks_fwd[43], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[146], down_tracks_out[139], right_tracks_fwd[44], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[145], down_tracks_out[140], right_tracks_fwd[45], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[144], down_tracks_out[141], right_tracks_fwd[46], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[159], down_tracks_out[142], right_tracks_fwd[47], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[142], down_tracks_out[127], right_tracks_fwd[16], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[141], down_tracks_out[112], right_tracks_fwd[17], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[140], down_tracks_out[113], right_tracks_fwd[18], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[139], down_tracks_out[114], right_tracks_fwd[19], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[138], down_tracks_out[115], right_tracks_fwd[20], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[137], down_tracks_out[116], right_tracks_fwd[21], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[136], down_tracks_out[117], right_tracks_fwd[22], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[135], down_tracks_out[118], right_tracks_fwd[23], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[134], down_tracks_out[119], right_tracks_fwd[24], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[133], down_tracks_out[120], right_tracks_fwd[25], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[132], down_tracks_out[121], right_tracks_fwd[26], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[131], down_tracks_out[122], right_tracks_fwd[27], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[130], down_tracks_out[123], right_tracks_fwd[28], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[129], down_tracks_out[124], right_tracks_fwd[29], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[128], down_tracks_out[125], right_tracks_fwd[30], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[143], down_tracks_out[126], right_tracks_fwd[31], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[126], 1'h0, right_tracks_fwd[0], block_out[4], block_out[0], 1'h0, inputs_i[64], up_tracks_out[125], 1'h0, right_tracks_fwd[1], block_out[4], block_out[0], 1'h0, inputs_i[64], up_tracks_out[124], 1'h0, right_tracks_fwd[2], block_out[4], block_out[0], 1'h0, inputs_i[65], up_tracks_out[123], 1'h0, right_tracks_fwd[3], block_out[4], block_out[0], 1'h0, inputs_i[65], up_tracks_out[122], 1'h0, right_tracks_fwd[4], block_out[4], block_out[0], 1'h0, inputs_i[66], up_tracks_out[121], 1'h0, right_tracks_fwd[5], block_out[4], block_out[0], 1'h0, inputs_i[66], up_tracks_out[120], 1'h0, right_tracks_fwd[6], block_out[4], block_out[0], 1'h0, inputs_i[67], up_tracks_out[119], 1'h0, right_tracks_fwd[7], block_out[4], block_out[0], 1'h0, inputs_i[67], up_tracks_out[118], 1'h0, right_tracks_fwd[8], block_out[4], block_out[0], 1'h0, inputs_i[68], up_tracks_out[117], 1'h0, right_tracks_fwd[9], block_out[4], block_out[0], 1'h0, inputs_i[68], up_tracks_out[116], 1'h0, right_tracks_fwd[10], block_out[4], block_out[0], 1'h0, inputs_i[69], up_tracks_out[115], 1'h0, right_tracks_fwd[11], block_out[4], block_out[0], 1'h0, inputs_i[69], up_tracks_out[114], 1'h0, right_tracks_fwd[12], block_out[4], block_out[0], 1'h0, inputs_i[70], up_tracks_out[113], 1'h0, right_tracks_fwd[13], block_out[4], block_out[0], 1'h0, inputs_i[70], up_tracks_out[112], 1'h0, right_tracks_fwd[14], block_out[4], block_out[0], 1'h0, inputs_i[71], up_tracks_out[127], 1'h0, right_tracks_fwd[15], block_out[4], block_out[0], 1'h0, inputs_i[71] }; |
| assign right_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31137 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32279 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33421 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34563 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35705 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36847 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37989 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39464 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40942 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42084 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43226 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44368 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45510 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46652 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47794 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49269 }; |
| assign up_tracks_fwd = { 16'h0000, up_tracks_out[335:240], 16'h0000, up_tracks_out[223:128], 16'h0000, up_tracks_out[111:16] }; |
| assign down_tracks_fwd = { down_tracks_out[319:224], 16'h0000, down_tracks_out[207:112], 16'h0000, down_tracks_out[95:0], 16'h0000 }; |
| assign left_tracks_fwd = { left_tracks_out[127:0], 128'h00000000000000000000000000000000 }; |
| assign right_tracks_fwd = { 128'h00000000000000000000000000000000, right_tracks_out[255:128] }; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2460 = _031_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2462 = _032_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2470 = _033_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2472 = _034_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3938 = _037_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3940 = _038_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3948 = _039_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3950 = _040_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5416 = _043_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5418 = _044_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5426 = _045_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5428 = _046_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6894 = _049_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6896 = _050_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6904 = _051_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6906 = _052_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8372 = _055_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8374 = _056_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8382 = _057_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8384 = _058_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9850 = _061_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9852 = _062_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9860 = _063_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9862 = _064_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11328 = _067_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11330 = _068_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11338 = _069_; |
| assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11340 = _070_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12470 = _071_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12472 = _072_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12480 = _073_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12482 = _074_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13612 = _075_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13614 = _076_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13622 = _077_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13624 = _078_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14754 = _079_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14756 = _080_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14764 = _081_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14766 = _082_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15896 = _083_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15898 = _084_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15906 = _085_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15908 = _086_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17038 = _087_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:17040 = _088_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17048 = _089_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17050 = _090_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18180 = _091_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18182 = _092_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18190 = _093_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18192 = _094_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19322 = _095_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19324 = _096_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19332 = _097_; |
| assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19334 = _098_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19344 = _099_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19346 = _100_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20807 = _103_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20809 = _104_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20819 = _105_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20821 = _106_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22282 = _109_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22284 = _110_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22294 = _111_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22296 = _112_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23757 = _115_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23759 = _116_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23769 = _117_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23771 = _118_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25232 = _121_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25234 = _122_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25244 = _123_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25246 = _124_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26707 = _127_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26709 = _128_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26719 = _129_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26721 = _130_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28182 = _133_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28184 = _134_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28194 = _135_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28196 = _136_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29657 = _139_; |
| assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29659 = _140_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31125 = _143_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31127 = _144_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31135 = _145_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31137 = _146_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32267 = _147_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32269 = _148_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32277 = _149_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32279 = _150_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33409 = _151_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33411 = _152_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33419 = _153_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33421 = _154_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34551 = _155_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34553 = _156_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34561 = _157_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34563 = _158_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35693 = _159_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35695 = _160_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35703 = _161_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35705 = _162_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36835 = _163_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36837 = _164_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36845 = _165_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36847 = _166_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37977 = _167_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37979 = _168_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37987 = _169_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37989 = _170_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37999 = _171_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:38001 = _172_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39462 = _175_; |
| assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39464 = _176_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40930 = _179_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40932 = _180_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40940 = _181_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40942 = _182_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42072 = _183_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42074 = _184_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42082 = _185_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42084 = _186_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43214 = _187_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43216 = _188_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43224 = _189_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43226 = _190_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44356 = _191_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44358 = _192_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44366 = _193_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44368 = _194_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45498 = _195_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45500 = _196_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45508 = _197_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45510 = _198_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46640 = _199_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46642 = _200_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46650 = _201_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46652 = _202_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47782 = _203_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47784 = _204_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47792 = _205_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47794 = _206_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47804 = _207_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47806 = _208_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49267 = _211_; |
| assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49269 = _212_; |
| assign config_block_o = { block_cfg_shift_chain[0], block_cfg_shift_chain[8] }; |
| assign config_vrnode_o = { vrnode_cfg_shift_chain[8], vrnode_cfg_shift_chain[17], vrnode_cfg_shift_chain[26], vrnode_cfg_shift_chain[35], vrnode_cfg_shift_chain[44], vrnode_cfg_shift_chain[53], vrnode_cfg_shift_chain[62] }; |
| assign config_hrnode_o = { hrnode_cfg_shift_chain[18], hrnode_cfg_shift_chain[37] }; |
| assign outputs_o = { _178_, _142_, _138_, _132_, _126_, _120_, _114_, _108_, _102_, _210_, _174_, _066_, _060_, _054_, _048_, _042_, _036_, _030_ }; |
| endmodule |
| |
| module fpga_io_mux(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, pins_o); |
| wire _00_; |
| wire _01_; |
| wire _02_; |
| wire _03_; |
| wire _04_; |
| wire _05_; |
| wire _06_; |
| wire _07_; |
| wire _08_; |
| wire _09_; |
| wire _10_; |
| wire _11_; |
| wire _12_; |
| wire _13_; |
| wire _14_; |
| wire _15_; |
| wire [8:0] config_chain; |
| input config_clk_i; |
| wire config_clk_i; |
| input config_ena_i; |
| wire config_ena_i; |
| input config_shift_i; |
| wire config_shift_i; |
| output config_shift_o; |
| wire config_shift_o; |
| output [7:0] pins_o; |
| wire [7:0] pins_o; |
| input [31:0] route_i; |
| wire [31:0] route_i; |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:1.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[8]), |
| .config_shift_o(_00_), |
| .route_i({ route_i[24], route_i[16], route_i[8], route_i[0] }), |
| .route_o(_01_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:2.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[7]), |
| .config_shift_o(_02_), |
| .route_i({ route_i[25], route_i[17], route_i[9], route_i[1] }), |
| .route_o(_03_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:3.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[6]), |
| .config_shift_o(_04_), |
| .route_i({ route_i[26], route_i[18], route_i[10], route_i[2] }), |
| .route_o(_05_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:4.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[5]), |
| .config_shift_o(_06_), |
| .route_i({ route_i[27], route_i[19], route_i[11], route_i[3] }), |
| .route_o(_07_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:5.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[4]), |
| .config_shift_o(_08_), |
| .route_i({ route_i[28], route_i[20], route_i[12], route_i[4] }), |
| .route_o(_09_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:6.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[3]), |
| .config_shift_o(_10_), |
| .route_i({ route_i[29], route_i[21], route_i[13], route_i[5] }), |
| .route_o(_11_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:7.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[2]), |
| .config_shift_o(_12_), |
| .route_i({ route_i[30], route_i[22], route_i[14], route_i[6] }), |
| .route_o(_13_) |
| ); |
| fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:8.io_mux ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_shift_i(config_chain[1]), |
| .config_shift_o(_14_), |
| .route_i({ route_i[31], route_i[23], route_i[15], route_i[7] }), |
| .route_o(_15_) |
| ); |
| assign config_chain = { config_shift_i, _00_, _02_, _04_, _06_, _08_, _10_, _12_, _14_ }; |
| assign config_shift_o = config_chain[0]; |
| assign pins_o = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ }; |
| endmodule |
| |
| module fpga_routing_mux_4_2_18446744073709551615(config_i, route_i, route_o); |
| wire _0_; |
| wire _1_; |
| wire _2_; |
| input [1:0] config_i; |
| wire [1:0] config_i; |
| input [3:0] route_i; |
| wire [3:0] route_i; |
| wire [3:0] route_int; |
| output route_o; |
| wire route_o; |
| assign _0_ = config_i[0] ? route_int[1] : route_int[0]; |
| assign _1_ = config_i[0] ? route_int[3] : route_int[2]; |
| assign _2_ = config_i[1] ? _1_ : _0_; |
| assign route_int = route_i; |
| assign route_o = _2_; |
| endmodule |
| |
| module fpga_routing_mux_7_3_7(config_i, route_i, route_o); |
| wire _00_; |
| wire _01_; |
| wire _02_; |
| wire _03_; |
| wire _04_; |
| wire _05_; |
| wire _06_; |
| input [2:0] config_i; |
| wire [2:0] config_i; |
| input [6:0] route_i; |
| wire [6:0] route_i; |
| wire [7:0] route_int; |
| output route_o; |
| wire route_o; |
| assign _00_ = config_i[0] ? route_int[1] : route_int[0]; |
| assign _01_ = config_i[0] ? route_int[5] : route_int[4]; |
| assign _02_ = config_i[0] ? route_int[3] : route_int[2]; |
| assign _03_ = config_i[0] ? route_int[7] : route_int[6]; |
| assign _04_ = config_i[1] ? _02_ : _00_; |
| assign _05_ = config_i[1] ? _03_ : _01_; |
| assign _06_ = config_i[2] ? _05_ : _04_; |
| assign route_int = { 1'h0, route_i }; |
| assign route_o = _06_; |
| endmodule |
| |
| module fpga_routing_mux_wcfg_4_2_18446744073709551615(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, route_o); |
| wire _0_; |
| wire _1_; |
| wire [1:0] _2_; |
| input config_clk_i; |
| wire config_clk_i; |
| wire [1:0] config_data; |
| input config_ena_i; |
| wire config_ena_i; |
| input config_shift_i; |
| wire config_shift_i; |
| output config_shift_o; |
| wire config_shift_o; |
| input [3:0] route_i; |
| wire [3:0] route_i; |
| output route_o; |
| wire route_o; |
| fpga_cfg_shiftreg_2 config_register ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_o(_2_), |
| .config_shift_i(config_shift_i), |
| .config_shift_o(_1_) |
| ); |
| fpga_routing_mux_4_2_18446744073709551615 mux ( |
| .config_i(config_data), |
| .route_i(route_i), |
| .route_o(_0_) |
| ); |
| assign config_data = _2_; |
| assign config_shift_o = _1_; |
| assign route_o = _0_; |
| endmodule |
| |
| module fpga_routing_node(config_data_i, route_i, route_o); |
| wire _000_; |
| wire _001_; |
| wire _002_; |
| wire _003_; |
| wire _004_; |
| wire _005_; |
| wire _006_; |
| wire _007_; |
| wire _008_; |
| wire _009_; |
| wire _010_; |
| wire _011_; |
| wire _012_; |
| wire _013_; |
| wire _014_; |
| wire _015_; |
| wire _016_; |
| wire _017_; |
| wire _018_; |
| wire _019_; |
| wire _020_; |
| wire _021_; |
| wire _022_; |
| wire _023_; |
| wire _024_; |
| wire _025_; |
| wire _026_; |
| wire _027_; |
| wire _028_; |
| wire _029_; |
| wire _030_; |
| wire _031_; |
| wire _032_; |
| wire _033_; |
| wire _034_; |
| wire _035_; |
| wire _036_; |
| wire _037_; |
| wire _038_; |
| wire _039_; |
| wire _040_; |
| wire _041_; |
| wire _042_; |
| wire _043_; |
| wire _044_; |
| wire _045_; |
| wire _046_; |
| wire _047_; |
| wire _048_; |
| wire _049_; |
| wire _050_; |
| wire _051_; |
| wire _052_; |
| wire _053_; |
| wire _054_; |
| wire _055_; |
| wire _056_; |
| wire _057_; |
| wire _058_; |
| wire _059_; |
| wire _060_; |
| wire _061_; |
| wire _062_; |
| wire _063_; |
| wire _064_; |
| wire _065_; |
| wire _066_; |
| wire _067_; |
| wire _068_; |
| wire _069_; |
| wire _070_; |
| wire _071_; |
| wire _072_; |
| wire _073_; |
| wire _074_; |
| wire _075_; |
| wire _076_; |
| wire _077_; |
| wire _078_; |
| wire _079_; |
| wire _080_; |
| wire _081_; |
| wire _082_; |
| wire _083_; |
| wire _084_; |
| wire _085_; |
| wire _086_; |
| wire _087_; |
| wire _088_; |
| wire _089_; |
| wire _090_; |
| wire _091_; |
| wire _092_; |
| wire _093_; |
| wire _094_; |
| wire _095_; |
| wire _096_; |
| wire _097_; |
| wire _098_; |
| wire _099_; |
| wire _100_; |
| wire _101_; |
| wire _102_; |
| wire _103_; |
| wire _104_; |
| wire _105_; |
| wire _106_; |
| wire _107_; |
| wire _108_; |
| wire _109_; |
| wire _110_; |
| wire _111_; |
| wire _112_; |
| wire _113_; |
| wire _114_; |
| wire _115_; |
| wire _116_; |
| wire _117_; |
| wire _118_; |
| wire _119_; |
| wire _120_; |
| wire _121_; |
| wire _122_; |
| wire _123_; |
| wire _124_; |
| wire _125_; |
| wire _126_; |
| wire _127_; |
| wire _128_; |
| wire _129_; |
| wire _130_; |
| wire _131_; |
| wire _132_; |
| wire _133_; |
| wire _134_; |
| wire _135_; |
| wire _136_; |
| wire _137_; |
| wire _138_; |
| wire _139_; |
| wire _140_; |
| wire _141_; |
| wire _142_; |
| wire _143_; |
| wire _144_; |
| wire _145_; |
| wire _146_; |
| wire _147_; |
| wire _148_; |
| wire _149_; |
| wire _150_; |
| wire _151_; |
| wire _152_; |
| wire _153_; |
| wire _154_; |
| wire _155_; |
| wire _156_; |
| wire _157_; |
| wire _158_; |
| wire _159_; |
| wire _160_; |
| wire _161_; |
| wire _162_; |
| wire _163_; |
| wire _164_; |
| wire _165_; |
| wire _166_; |
| wire _167_; |
| wire _168_; |
| wire _169_; |
| wire _170_; |
| wire _171_; |
| wire _172_; |
| wire _173_; |
| wire _174_; |
| wire _175_; |
| wire [111:0] buffered_in; |
| wire [15:0] buffered_out0; |
| wire [15:0] buffered_out1; |
| input [47:0] config_data_i; |
| wire [47:0] config_data_i; |
| input [111:0] route_i; |
| wire [111:0] route_i; |
| wire [15:0] route_int; |
| output [15:0] route_o; |
| wire [15:0] route_o; |
| fpga_tech_buffer \muxes:1.bufs:1.rnode_in ( |
| .i(route_i[105]), |
| .z(_000_) |
| ); |
| fpga_tech_buffer \muxes:1.bufs:2.rnode_in ( |
| .i(route_i[106]), |
| .z(_001_) |
| ); |
| fpga_tech_buffer \muxes:1.bufs:3.rnode_in ( |
| .i(route_i[107]), |
| .z(_002_) |
| ); |
| fpga_tech_buffer \muxes:1.bufs:4.rnode_in ( |
| .i(route_i[108]), |
| .z(_003_) |
| ); |
| fpga_tech_buffer \muxes:1.bufs:5.rnode_in ( |
| .i(route_i[109]), |
| .z(_004_) |
| ); |
| fpga_tech_buffer \muxes:1.bufs:6.rnode_in ( |
| .i(route_i[110]), |
| .z(_005_) |
| ); |
| fpga_tech_buffer \muxes:1.bufs:7.rnode_in ( |
| .i(route_i[111]), |
| .z(_006_) |
| ); |
| fpga_tech_buffer \muxes:1.loop_breaker ( |
| .i(buffered_out0[0]), |
| .z(_009_) |
| ); |
| fpga_tech_buffer \muxes:1.rnode_tfinish ( |
| .i(route_int[0]), |
| .z(_008_) |
| ); |
| fpga_tech_buffer \muxes:1.rnode_tstart ( |
| .i(buffered_out1[0]), |
| .z(_010_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:1.routing_node_track ( |
| .config_i(config_data_i[2:0]), |
| .route_i(buffered_in[111:105]), |
| .route_o(_007_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:1.rnode_in ( |
| .i(route_i[42]), |
| .z(_099_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:2.rnode_in ( |
| .i(route_i[43]), |
| .z(_100_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:3.rnode_in ( |
| .i(route_i[44]), |
| .z(_101_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:4.rnode_in ( |
| .i(route_i[45]), |
| .z(_102_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:5.rnode_in ( |
| .i(route_i[46]), |
| .z(_103_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:6.rnode_in ( |
| .i(route_i[47]), |
| .z(_104_) |
| ); |
| fpga_tech_buffer \muxes:10.bufs:7.rnode_in ( |
| .i(route_i[48]), |
| .z(_105_) |
| ); |
| fpga_tech_buffer \muxes:10.loop_breaker ( |
| .i(buffered_out0[9]), |
| .z(_108_) |
| ); |
| fpga_tech_buffer \muxes:10.rnode_tfinish ( |
| .i(route_int[9]), |
| .z(_107_) |
| ); |
| fpga_tech_buffer \muxes:10.rnode_tstart ( |
| .i(buffered_out1[9]), |
| .z(_109_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:10.routing_node_track ( |
| .config_i(config_data_i[29:27]), |
| .route_i(buffered_in[48:42]), |
| .route_o(_106_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:1.rnode_in ( |
| .i(route_i[35]), |
| .z(_110_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:2.rnode_in ( |
| .i(route_i[36]), |
| .z(_111_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:3.rnode_in ( |
| .i(route_i[37]), |
| .z(_112_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:4.rnode_in ( |
| .i(route_i[38]), |
| .z(_113_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:5.rnode_in ( |
| .i(route_i[39]), |
| .z(_114_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:6.rnode_in ( |
| .i(route_i[40]), |
| .z(_115_) |
| ); |
| fpga_tech_buffer \muxes:11.bufs:7.rnode_in ( |
| .i(route_i[41]), |
| .z(_116_) |
| ); |
| fpga_tech_buffer \muxes:11.loop_breaker ( |
| .i(buffered_out0[10]), |
| .z(_119_) |
| ); |
| fpga_tech_buffer \muxes:11.rnode_tfinish ( |
| .i(route_int[10]), |
| .z(_118_) |
| ); |
| fpga_tech_buffer \muxes:11.rnode_tstart ( |
| .i(buffered_out1[10]), |
| .z(_120_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:11.routing_node_track ( |
| .config_i(config_data_i[32:30]), |
| .route_i(buffered_in[41:35]), |
| .route_o(_117_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:1.rnode_in ( |
| .i(route_i[28]), |
| .z(_121_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:2.rnode_in ( |
| .i(route_i[29]), |
| .z(_122_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:3.rnode_in ( |
| .i(route_i[30]), |
| .z(_123_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:4.rnode_in ( |
| .i(route_i[31]), |
| .z(_124_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:5.rnode_in ( |
| .i(route_i[32]), |
| .z(_125_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:6.rnode_in ( |
| .i(route_i[33]), |
| .z(_126_) |
| ); |
| fpga_tech_buffer \muxes:12.bufs:7.rnode_in ( |
| .i(route_i[34]), |
| .z(_127_) |
| ); |
| fpga_tech_buffer \muxes:12.loop_breaker ( |
| .i(buffered_out0[11]), |
| .z(_130_) |
| ); |
| fpga_tech_buffer \muxes:12.rnode_tfinish ( |
| .i(route_int[11]), |
| .z(_129_) |
| ); |
| fpga_tech_buffer \muxes:12.rnode_tstart ( |
| .i(buffered_out1[11]), |
| .z(_131_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:12.routing_node_track ( |
| .config_i(config_data_i[35:33]), |
| .route_i(buffered_in[34:28]), |
| .route_o(_128_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:1.rnode_in ( |
| .i(route_i[21]), |
| .z(_132_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:2.rnode_in ( |
| .i(route_i[22]), |
| .z(_133_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:3.rnode_in ( |
| .i(route_i[23]), |
| .z(_134_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:4.rnode_in ( |
| .i(route_i[24]), |
| .z(_135_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:5.rnode_in ( |
| .i(route_i[25]), |
| .z(_136_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:6.rnode_in ( |
| .i(route_i[26]), |
| .z(_137_) |
| ); |
| fpga_tech_buffer \muxes:13.bufs:7.rnode_in ( |
| .i(route_i[27]), |
| .z(_138_) |
| ); |
| fpga_tech_buffer \muxes:13.loop_breaker ( |
| .i(buffered_out0[12]), |
| .z(_141_) |
| ); |
| fpga_tech_buffer \muxes:13.rnode_tfinish ( |
| .i(route_int[12]), |
| .z(_140_) |
| ); |
| fpga_tech_buffer \muxes:13.rnode_tstart ( |
| .i(buffered_out1[12]), |
| .z(_142_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:13.routing_node_track ( |
| .config_i(config_data_i[38:36]), |
| .route_i(buffered_in[27:21]), |
| .route_o(_139_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:1.rnode_in ( |
| .i(route_i[14]), |
| .z(_143_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:2.rnode_in ( |
| .i(route_i[15]), |
| .z(_144_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:3.rnode_in ( |
| .i(route_i[16]), |
| .z(_145_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:4.rnode_in ( |
| .i(route_i[17]), |
| .z(_146_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:5.rnode_in ( |
| .i(route_i[18]), |
| .z(_147_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:6.rnode_in ( |
| .i(route_i[19]), |
| .z(_148_) |
| ); |
| fpga_tech_buffer \muxes:14.bufs:7.rnode_in ( |
| .i(route_i[20]), |
| .z(_149_) |
| ); |
| fpga_tech_buffer \muxes:14.loop_breaker ( |
| .i(buffered_out0[13]), |
| .z(_152_) |
| ); |
| fpga_tech_buffer \muxes:14.rnode_tfinish ( |
| .i(route_int[13]), |
| .z(_151_) |
| ); |
| fpga_tech_buffer \muxes:14.rnode_tstart ( |
| .i(buffered_out1[13]), |
| .z(_153_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:14.routing_node_track ( |
| .config_i(config_data_i[41:39]), |
| .route_i(buffered_in[20:14]), |
| .route_o(_150_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:1.rnode_in ( |
| .i(route_i[7]), |
| .z(_154_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:2.rnode_in ( |
| .i(route_i[8]), |
| .z(_155_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:3.rnode_in ( |
| .i(route_i[9]), |
| .z(_156_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:4.rnode_in ( |
| .i(route_i[10]), |
| .z(_157_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:5.rnode_in ( |
| .i(route_i[11]), |
| .z(_158_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:6.rnode_in ( |
| .i(route_i[12]), |
| .z(_159_) |
| ); |
| fpga_tech_buffer \muxes:15.bufs:7.rnode_in ( |
| .i(route_i[13]), |
| .z(_160_) |
| ); |
| fpga_tech_buffer \muxes:15.loop_breaker ( |
| .i(buffered_out0[14]), |
| .z(_163_) |
| ); |
| fpga_tech_buffer \muxes:15.rnode_tfinish ( |
| .i(route_int[14]), |
| .z(_162_) |
| ); |
| fpga_tech_buffer \muxes:15.rnode_tstart ( |
| .i(buffered_out1[14]), |
| .z(_164_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:15.routing_node_track ( |
| .config_i(config_data_i[44:42]), |
| .route_i(buffered_in[13:7]), |
| .route_o(_161_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:1.rnode_in ( |
| .i(route_i[0]), |
| .z(_165_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:2.rnode_in ( |
| .i(route_i[1]), |
| .z(_166_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:3.rnode_in ( |
| .i(route_i[2]), |
| .z(_167_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:4.rnode_in ( |
| .i(route_i[3]), |
| .z(_168_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:5.rnode_in ( |
| .i(route_i[4]), |
| .z(_169_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:6.rnode_in ( |
| .i(route_i[5]), |
| .z(_170_) |
| ); |
| fpga_tech_buffer \muxes:16.bufs:7.rnode_in ( |
| .i(route_i[6]), |
| .z(_171_) |
| ); |
| fpga_tech_buffer \muxes:16.loop_breaker ( |
| .i(buffered_out0[15]), |
| .z(_174_) |
| ); |
| fpga_tech_buffer \muxes:16.rnode_tfinish ( |
| .i(route_int[15]), |
| .z(_173_) |
| ); |
| fpga_tech_buffer \muxes:16.rnode_tstart ( |
| .i(buffered_out1[15]), |
| .z(_175_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:16.routing_node_track ( |
| .config_i(config_data_i[47:45]), |
| .route_i(buffered_in[6:0]), |
| .route_o(_172_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:1.rnode_in ( |
| .i(route_i[98]), |
| .z(_011_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:2.rnode_in ( |
| .i(route_i[99]), |
| .z(_012_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:3.rnode_in ( |
| .i(route_i[100]), |
| .z(_013_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:4.rnode_in ( |
| .i(route_i[101]), |
| .z(_014_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:5.rnode_in ( |
| .i(route_i[102]), |
| .z(_015_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:6.rnode_in ( |
| .i(route_i[103]), |
| .z(_016_) |
| ); |
| fpga_tech_buffer \muxes:2.bufs:7.rnode_in ( |
| .i(route_i[104]), |
| .z(_017_) |
| ); |
| fpga_tech_buffer \muxes:2.loop_breaker ( |
| .i(buffered_out0[1]), |
| .z(_020_) |
| ); |
| fpga_tech_buffer \muxes:2.rnode_tfinish ( |
| .i(route_int[1]), |
| .z(_019_) |
| ); |
| fpga_tech_buffer \muxes:2.rnode_tstart ( |
| .i(buffered_out1[1]), |
| .z(_021_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:2.routing_node_track ( |
| .config_i(config_data_i[5:3]), |
| .route_i(buffered_in[104:98]), |
| .route_o(_018_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:1.rnode_in ( |
| .i(route_i[91]), |
| .z(_022_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:2.rnode_in ( |
| .i(route_i[92]), |
| .z(_023_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:3.rnode_in ( |
| .i(route_i[93]), |
| .z(_024_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:4.rnode_in ( |
| .i(route_i[94]), |
| .z(_025_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:5.rnode_in ( |
| .i(route_i[95]), |
| .z(_026_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:6.rnode_in ( |
| .i(route_i[96]), |
| .z(_027_) |
| ); |
| fpga_tech_buffer \muxes:3.bufs:7.rnode_in ( |
| .i(route_i[97]), |
| .z(_028_) |
| ); |
| fpga_tech_buffer \muxes:3.loop_breaker ( |
| .i(buffered_out0[2]), |
| .z(_031_) |
| ); |
| fpga_tech_buffer \muxes:3.rnode_tfinish ( |
| .i(route_int[2]), |
| .z(_030_) |
| ); |
| fpga_tech_buffer \muxes:3.rnode_tstart ( |
| .i(buffered_out1[2]), |
| .z(_032_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:3.routing_node_track ( |
| .config_i(config_data_i[8:6]), |
| .route_i(buffered_in[97:91]), |
| .route_o(_029_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:1.rnode_in ( |
| .i(route_i[84]), |
| .z(_033_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:2.rnode_in ( |
| .i(route_i[85]), |
| .z(_034_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:3.rnode_in ( |
| .i(route_i[86]), |
| .z(_035_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:4.rnode_in ( |
| .i(route_i[87]), |
| .z(_036_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:5.rnode_in ( |
| .i(route_i[88]), |
| .z(_037_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:6.rnode_in ( |
| .i(route_i[89]), |
| .z(_038_) |
| ); |
| fpga_tech_buffer \muxes:4.bufs:7.rnode_in ( |
| .i(route_i[90]), |
| .z(_039_) |
| ); |
| fpga_tech_buffer \muxes:4.loop_breaker ( |
| .i(buffered_out0[3]), |
| .z(_042_) |
| ); |
| fpga_tech_buffer \muxes:4.rnode_tfinish ( |
| .i(route_int[3]), |
| .z(_041_) |
| ); |
| fpga_tech_buffer \muxes:4.rnode_tstart ( |
| .i(buffered_out1[3]), |
| .z(_043_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:4.routing_node_track ( |
| .config_i(config_data_i[11:9]), |
| .route_i(buffered_in[90:84]), |
| .route_o(_040_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:1.rnode_in ( |
| .i(route_i[77]), |
| .z(_044_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:2.rnode_in ( |
| .i(route_i[78]), |
| .z(_045_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:3.rnode_in ( |
| .i(route_i[79]), |
| .z(_046_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:4.rnode_in ( |
| .i(route_i[80]), |
| .z(_047_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:5.rnode_in ( |
| .i(route_i[81]), |
| .z(_048_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:6.rnode_in ( |
| .i(route_i[82]), |
| .z(_049_) |
| ); |
| fpga_tech_buffer \muxes:5.bufs:7.rnode_in ( |
| .i(route_i[83]), |
| .z(_050_) |
| ); |
| fpga_tech_buffer \muxes:5.loop_breaker ( |
| .i(buffered_out0[4]), |
| .z(_053_) |
| ); |
| fpga_tech_buffer \muxes:5.rnode_tfinish ( |
| .i(route_int[4]), |
| .z(_052_) |
| ); |
| fpga_tech_buffer \muxes:5.rnode_tstart ( |
| .i(buffered_out1[4]), |
| .z(_054_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:5.routing_node_track ( |
| .config_i(config_data_i[14:12]), |
| .route_i(buffered_in[83:77]), |
| .route_o(_051_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:1.rnode_in ( |
| .i(route_i[70]), |
| .z(_055_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:2.rnode_in ( |
| .i(route_i[71]), |
| .z(_056_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:3.rnode_in ( |
| .i(route_i[72]), |
| .z(_057_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:4.rnode_in ( |
| .i(route_i[73]), |
| .z(_058_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:5.rnode_in ( |
| .i(route_i[74]), |
| .z(_059_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:6.rnode_in ( |
| .i(route_i[75]), |
| .z(_060_) |
| ); |
| fpga_tech_buffer \muxes:6.bufs:7.rnode_in ( |
| .i(route_i[76]), |
| .z(_061_) |
| ); |
| fpga_tech_buffer \muxes:6.loop_breaker ( |
| .i(buffered_out0[5]), |
| .z(_064_) |
| ); |
| fpga_tech_buffer \muxes:6.rnode_tfinish ( |
| .i(route_int[5]), |
| .z(_063_) |
| ); |
| fpga_tech_buffer \muxes:6.rnode_tstart ( |
| .i(buffered_out1[5]), |
| .z(_065_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:6.routing_node_track ( |
| .config_i(config_data_i[17:15]), |
| .route_i(buffered_in[76:70]), |
| .route_o(_062_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:1.rnode_in ( |
| .i(route_i[63]), |
| .z(_066_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:2.rnode_in ( |
| .i(route_i[64]), |
| .z(_067_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:3.rnode_in ( |
| .i(route_i[65]), |
| .z(_068_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:4.rnode_in ( |
| .i(route_i[66]), |
| .z(_069_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:5.rnode_in ( |
| .i(route_i[67]), |
| .z(_070_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:6.rnode_in ( |
| .i(route_i[68]), |
| .z(_071_) |
| ); |
| fpga_tech_buffer \muxes:7.bufs:7.rnode_in ( |
| .i(route_i[69]), |
| .z(_072_) |
| ); |
| fpga_tech_buffer \muxes:7.loop_breaker ( |
| .i(buffered_out0[6]), |
| .z(_075_) |
| ); |
| fpga_tech_buffer \muxes:7.rnode_tfinish ( |
| .i(route_int[6]), |
| .z(_074_) |
| ); |
| fpga_tech_buffer \muxes:7.rnode_tstart ( |
| .i(buffered_out1[6]), |
| .z(_076_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:7.routing_node_track ( |
| .config_i(config_data_i[20:18]), |
| .route_i(buffered_in[69:63]), |
| .route_o(_073_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:1.rnode_in ( |
| .i(route_i[56]), |
| .z(_077_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:2.rnode_in ( |
| .i(route_i[57]), |
| .z(_078_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:3.rnode_in ( |
| .i(route_i[58]), |
| .z(_079_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:4.rnode_in ( |
| .i(route_i[59]), |
| .z(_080_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:5.rnode_in ( |
| .i(route_i[60]), |
| .z(_081_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:6.rnode_in ( |
| .i(route_i[61]), |
| .z(_082_) |
| ); |
| fpga_tech_buffer \muxes:8.bufs:7.rnode_in ( |
| .i(route_i[62]), |
| .z(_083_) |
| ); |
| fpga_tech_buffer \muxes:8.loop_breaker ( |
| .i(buffered_out0[7]), |
| .z(_086_) |
| ); |
| fpga_tech_buffer \muxes:8.rnode_tfinish ( |
| .i(route_int[7]), |
| .z(_085_) |
| ); |
| fpga_tech_buffer \muxes:8.rnode_tstart ( |
| .i(buffered_out1[7]), |
| .z(_087_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:8.routing_node_track ( |
| .config_i(config_data_i[23:21]), |
| .route_i(buffered_in[62:56]), |
| .route_o(_084_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:1.rnode_in ( |
| .i(route_i[49]), |
| .z(_088_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:2.rnode_in ( |
| .i(route_i[50]), |
| .z(_089_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:3.rnode_in ( |
| .i(route_i[51]), |
| .z(_090_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:4.rnode_in ( |
| .i(route_i[52]), |
| .z(_091_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:5.rnode_in ( |
| .i(route_i[53]), |
| .z(_092_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:6.rnode_in ( |
| .i(route_i[54]), |
| .z(_093_) |
| ); |
| fpga_tech_buffer \muxes:9.bufs:7.rnode_in ( |
| .i(route_i[55]), |
| .z(_094_) |
| ); |
| fpga_tech_buffer \muxes:9.loop_breaker ( |
| .i(buffered_out0[8]), |
| .z(_097_) |
| ); |
| fpga_tech_buffer \muxes:9.rnode_tfinish ( |
| .i(route_int[8]), |
| .z(_096_) |
| ); |
| fpga_tech_buffer \muxes:9.rnode_tstart ( |
| .i(buffered_out1[8]), |
| .z(_098_) |
| ); |
| fpga_routing_mux_7_3_7 \muxes:9.routing_node_track ( |
| .config_i(config_data_i[26:24]), |
| .route_i(buffered_in[55:49]), |
| .route_o(_095_) |
| ); |
| assign route_int = { _172_, _161_, _150_, _139_, _128_, _117_, _106_, _095_, _084_, _073_, _062_, _051_, _040_, _029_, _018_, _007_ }; |
| assign buffered_in = { _006_, _005_, _004_, _003_, _002_, _001_, _000_, _017_, _016_, _015_, _014_, _013_, _012_, _011_, _028_, _027_, _026_, _025_, _024_, _023_, _022_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _050_, _049_, _048_, _047_, _046_, _045_, _044_, _061_, _060_, _059_, _058_, _057_, _056_, _055_, _072_, _071_, _070_, _069_, _068_, _067_, _066_, _083_, _082_, _081_, _080_, _079_, _078_, _077_, _094_, _093_, _092_, _091_, _090_, _089_, _088_, _105_, _104_, _103_, _102_, _101_, _100_, _099_, _116_, _115_, _114_, _113_, _112_, _111_, _110_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _149_, _148_, _147_, _146_, _145_, _144_, _143_, _160_, _159_, _158_, _157_, _156_, _155_, _154_, _171_, _170_, _169_, _168_, _167_, _166_, _165_ }; |
| assign buffered_out0 = { _173_, _162_, _151_, _140_, _129_, _118_, _107_, _096_, _085_, _074_, _063_, _052_, _041_, _030_, _019_, _008_ }; |
| assign buffered_out1 = { _174_, _163_, _152_, _141_, _130_, _119_, _108_, _097_, _086_, _075_, _064_, _053_, _042_, _031_, _020_, _009_ }; |
| assign route_o = { _175_, _164_, _153_, _142_, _131_, _120_, _109_, _098_, _087_, _076_, _065_, _054_, _043_, _032_, _021_, _010_ }; |
| endmodule |
| |
| module fpga_routing_node_wcfg(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, route_o); |
| wire [15:0] _0_; |
| wire _1_; |
| wire [47:0] _2_; |
| input config_clk_i; |
| wire config_clk_i; |
| wire [47:0] config_data; |
| wire [47:0] config_data_gated; |
| input config_ena_i; |
| wire config_ena_i; |
| input config_shift_i; |
| wire config_shift_i; |
| output config_shift_o; |
| wire config_shift_o; |
| wire [15:0] \node:49529 ; |
| input [111:0] route_i; |
| wire [111:0] route_i; |
| output [15:0] route_o; |
| wire [15:0] route_o; |
| fpga_cfg_shiftreg_48 config_register ( |
| .config_clk_i(config_clk_i), |
| .config_ena_i(config_ena_i), |
| .config_o(_2_), |
| .config_shift_i(config_shift_i), |
| .config_shift_o(_1_) |
| ); |
| fpga_routing_node node ( |
| .config_data_i(config_data_gated), |
| .route_i(route_i), |
| .route_o(_0_) |
| ); |
| assign config_data = _2_; |
| assign config_data_gated = config_data; |
| assign \node:49529 = _0_; |
| assign config_shift_o = _1_; |
| assign route_o = \node:49529 ; |
| endmodule |
| |
| module wb_arbiter_sync_7(wb_clk_i, wb_rst_i, \wb_i_up.stb_i , \wb_i_up.cyc_i , \wb_i_up.we_i , \wb_i_up.dat_i , \wb_i_up.adr_i , addr_map, wb_i_bottom, \wb_o_up.ack_o , \wb_o_up.dat_o , wb_o_bottom); |
| wire [32:0] _00_; |
| wire [32:0] _01_; |
| wire [32:0] _02_; |
| wire [32:0] _03_; |
| wire _04_; |
| wire _05_; |
| wire _06_; |
| wire _07_; |
| wire _08_; |
| wire _09_; |
| wire [66:0] _10_; |
| wire [66:0] _11_; |
| wire [66:0] _12_; |
| wire [66:0] _13_; |
| wire [66:0] _14_; |
| wire [66:0] _15_; |
| wire [66:0] _16_; |
| wire [32:0] _17_; |
| wire [32:0] _18_; |
| wire [32:0] _19_; |
| wire [32:0] _20_; |
| wire _21_; |
| wire _22_; |
| wire _23_; |
| wire _24_; |
| wire [2:0] _25_; |
| wire _26_; |
| wire [2:0] _27_; |
| wire _28_; |
| wire [2:0] _29_; |
| wire _30_; |
| wire [2:0] _31_; |
| wire _32_; |
| wire [2:0] _33_; |
| wire _34_; |
| wire [2:0] _35_; |
| wire _36_; |
| wire [2:0] _37_; |
| wire [468:0] _38_; |
| wire _39_; |
| wire [2:0] _40_; |
| wire _41_; |
| wire [32:0] _42_; |
| wire [468:0] _43_; |
| wire _44_; |
| wire _45_; |
| wire [32:0] _46_; |
| wire [468:0] _47_; |
| wire _48_; |
| wire [2:0] _49_; |
| wire _50_; |
| wire [2:0] _51_; |
| reg [2:0] _52_ = 3'h0; |
| reg _53_; |
| reg [32:0] _54_; |
| reg [468:0] _55_; |
| wire _56_; |
| wire _57_; |
| wire _58_; |
| wire _59_; |
| wire _60_; |
| wire _61_; |
| wire _62_; |
| wire _63_; |
| wire _64_; |
| wire _65_; |
| wire _66_; |
| wire _67_; |
| wire _68_; |
| wire _69_; |
| wire [66:0] _70_; |
| wire [66:0] _71_; |
| wire [66:0] _72_; |
| wire [66:0] _73_; |
| wire [66:0] _74_; |
| wire [66:0] _75_; |
| wire [66:0] _76_; |
| wire [32:0] _77_; |
| wire [32:0] _78_; |
| wire [32:0] _79_; |
| wire [32:0] _80_; |
| wire _81_; |
| wire _82_; |
| wire _83_; |
| wire _84_; |
| wire _85_; |
| wire _86_; |
| wire _87_; |
| wire _88_; |
| input [223:0] addr_map; |
| wire [223:0] addr_map; |
| wire state; |
| wire [2:0] \sync.pn_buf ; |
| input wb_clk_i; |
| wire wb_clk_i; |
| input [230:0] wb_i_bottom; |
| wire [230:0] wb_i_bottom; |
| input [31:0] \wb_i_up.adr_i ; |
| wire [31:0] \wb_i_up.adr_i ; |
| input \wb_i_up.cyc_i ; |
| wire \wb_i_up.cyc_i ; |
| input [31:0] \wb_i_up.dat_i ; |
| wire [31:0] \wb_i_up.dat_i ; |
| input \wb_i_up.stb_i ; |
| wire \wb_i_up.stb_i ; |
| input \wb_i_up.we_i ; |
| wire \wb_i_up.we_i ; |
| output [468:0] wb_o_bottom; |
| wire [468:0] wb_o_bottom; |
| output \wb_o_up.ack_o ; |
| wire \wb_o_up.ack_o ; |
| output [31:0] \wb_o_up.dat_o ; |
| wire [31:0] \wb_o_up.dat_o ; |
| input wb_rst_i; |
| wire wb_rst_i; |
| assign _00_ = \sync.pn_buf [0] ? wb_i_bottom[65:33] : wb_i_bottom[32:0]; |
| assign _01_ = \sync.pn_buf [0] ? wb_i_bottom[65:33] : wb_i_bottom[32:0]; |
| assign _02_ = \sync.pn_buf [0] ? wb_i_bottom[131:99] : wb_i_bottom[98:66]; |
| assign _03_ = \sync.pn_buf [0] ? wb_i_bottom[131:99] : wb_i_bottom[98:66]; |
| assign _77_ = \sync.pn_buf [1] ? _02_ : _00_; |
| assign _17_ = \sync.pn_buf [1] ? _03_ : _01_; |
| assign _21_ = \wb_i_up.cyc_i & \wb_i_up.stb_i ; |
| assign _22_ = ~ _54_[0]; |
| assign _23_ = _21_ & _22_; |
| assign _24_ = \wb_i_up.adr_i >= addr_map[31:0]; |
| assign _25_ = _24_ ? 3'h0 : \sync.pn_buf ; |
| assign _26_ = \wb_i_up.adr_i >= addr_map[63:32]; |
| assign _27_ = _26_ ? 3'h1 : _25_; |
| assign _28_ = \wb_i_up.adr_i >= addr_map[95:64]; |
| assign _29_ = _28_ ? 3'h2 : _27_; |
| assign _30_ = \wb_i_up.adr_i >= addr_map[127:96]; |
| assign _31_ = _30_ ? 3'h3 : _29_; |
| assign _32_ = \wb_i_up.adr_i >= addr_map[159:128]; |
| assign _33_ = _32_ ? 3'h4 : _31_; |
| assign _34_ = \wb_i_up.adr_i >= addr_map[191:160]; |
| assign _35_ = _34_ ? 3'h5 : _33_; |
| assign _36_ = \wb_i_up.adr_i >= addr_map[223:192]; |
| assign _37_ = _36_ ? 3'h6 : _35_; |
| assign _38_ = _23_ ? { _76_, _75_, _74_, _73_, _72_, _71_, _70_ } : _55_; |
| assign _39_ = _23_ ? 1'h1 : state; |
| assign _40_ = _23_ ? _37_ : \sync.pn_buf ; |
| assign _41_ = state == 1'h0; |
| assign _42_ = _80_[0] ? { _20_[32:1], 1'h1 } : _54_; |
| assign _43_ = _80_[0] ? { _16_, _15_, _14_, _13_, _12_, _11_, _10_ } : _55_; |
| assign _44_ = _80_[0] ? 1'h0 : state; |
| assign _45_ = state == 1'h1; |
| function [32:0] \624 ; |
| input [32:0] a; |
| input [65:0] b; |
| input [1:0] s; |
| (* parallel_case *) |
| casez (s) |
| 2'b?1: |
| \624 = b[32:0]; |
| 2'b1?: |
| \624 = b[65:33]; |
| default: |
| \624 = a; |
| endcase |
| endfunction |
| assign _46_ = \624 (33'hxxxxxxxxx, { _42_, 33'h000000000 }, { _45_, _41_ }); |
| function [468:0] \626 ; |
| input [468:0] a; |
| input [937:0] b; |
| input [1:0] s; |
| (* parallel_case *) |
| casez (s) |
| 2'b?1: |
| \626 = b[468:0]; |
| 2'b1?: |
| \626 = b[937:469]; |
| default: |
| \626 = a; |
| endcase |
| endfunction |
| assign _47_ = \626 (469'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _43_, _38_ }, { _45_, _41_ }); |
| function [0:0] \628 ; |
| input [0:0] a; |
| input [1:0] b; |
| input [1:0] s; |
| (* parallel_case *) |
| casez (s) |
| 2'b?1: |
| \628 = b[0:0]; |
| 2'b1?: |
| \628 = b[1:1]; |
| default: |
| \628 = a; |
| endcase |
| endfunction |
| assign _48_ = \628 (1'hx, { _44_, _39_ }, { _45_, _41_ }); |
| function [2:0] \632 ; |
| input [2:0] a; |
| input [5:0] b; |
| input [1:0] s; |
| (* parallel_case *) |
| casez (s) |
| 2'b?1: |
| \632 = b[2:0]; |
| 2'b1?: |
| \632 = b[5:3]; |
| default: |
| \632 = a; |
| endcase |
| endfunction |
| assign _49_ = \632 (3'hx, { \sync.pn_buf , _40_ }, { _45_, _41_ }); |
| assign _50_ = ~ wb_rst_i; |
| assign _51_ = _50_ ? _49_ : \sync.pn_buf ; |
| always @(posedge wb_clk_i) |
| _52_ <= _51_; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _53_ <= 1'h0; |
| else _53_ <= _48_; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _54_ <= 33'h000000000; |
| else _54_ <= _46_; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _55_ <= 469'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; |
| else _55_ <= _47_; |
| assign _56_ = ~ _37_[2]; |
| assign _57_ = ~ _37_[1]; |
| assign _58_ = _56_ & _57_; |
| assign _59_ = _56_ & _37_[1]; |
| assign _60_ = _37_[2] & _57_; |
| assign _61_ = _37_[2] & _37_[1]; |
| assign _62_ = ~ _37_[0]; |
| assign _63_ = _58_ & _62_; |
| assign _64_ = _58_ & _37_[0]; |
| assign _65_ = _59_ & _62_; |
| assign _66_ = _59_ & _37_[0]; |
| assign _67_ = _60_ & _62_; |
| assign _68_ = _60_ & _37_[0]; |
| assign _69_ = _61_ & _62_; |
| assign _70_ = _63_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[66:0]; |
| assign _71_ = _64_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[133:67]; |
| assign _72_ = _65_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[200:134]; |
| assign _73_ = _66_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[267:201]; |
| assign _74_ = _67_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[334:268]; |
| assign _75_ = _68_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[401:335]; |
| assign _76_ = _69_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _55_[468:402]; |
| assign _78_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132]; |
| assign _79_ = \sync.pn_buf [1] ? wb_i_bottom[230:198] : _78_; |
| assign _80_ = \sync.pn_buf [2] ? _79_ : _77_; |
| assign _81_ = ~ \sync.pn_buf [2]; |
| assign _82_ = ~ \sync.pn_buf [1]; |
| assign _83_ = _81_ & _82_; |
| assign _84_ = _81_ & \sync.pn_buf [1]; |
| assign _85_ = \sync.pn_buf [2] & _82_; |
| assign _86_ = \sync.pn_buf [2] & \sync.pn_buf [1]; |
| assign _87_ = ~ \sync.pn_buf [0]; |
| assign _88_ = _83_ & _87_; |
| assign _04_ = _83_ & \sync.pn_buf [0]; |
| assign _05_ = _84_ & _87_; |
| assign _06_ = _84_ & \sync.pn_buf [0]; |
| assign _07_ = _85_ & _87_; |
| assign _08_ = _85_ & \sync.pn_buf [0]; |
| assign _09_ = _86_ & _87_; |
| assign _10_ = _88_ ? 67'h00000000000000000 : _55_[66:0]; |
| assign _11_ = _04_ ? 67'h00000000000000000 : _55_[133:67]; |
| assign _12_ = _05_ ? 67'h00000000000000000 : _55_[200:134]; |
| assign _13_ = _06_ ? 67'h00000000000000000 : _55_[267:201]; |
| assign _14_ = _07_ ? 67'h00000000000000000 : _55_[334:268]; |
| assign _15_ = _08_ ? 67'h00000000000000000 : _55_[401:335]; |
| assign _16_ = _09_ ? 67'h00000000000000000 : _55_[468:402]; |
| assign _18_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132]; |
| assign _19_ = \sync.pn_buf [1] ? wb_i_bottom[230:198] : _18_; |
| assign _20_ = \sync.pn_buf [2] ? _19_ : _17_; |
| assign state = _53_; |
| assign \sync.pn_buf = _52_; |
| assign \wb_o_up.ack_o = _54_[0]; |
| assign \wb_o_up.dat_o = _54_[32:1]; |
| assign wb_o_bottom = _55_; |
| endmodule |
| |
| module wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o); |
| wire _0_; |
| wire _1_; |
| wire [31:0] _2_; |
| reg [31:0] _3_; |
| reg [32:0] _4_; |
| input [31:0] reg_i; |
| wire [31:0] reg_i; |
| output [31:0] reg_o; |
| wire [31:0] reg_o; |
| wire [31:0] reg_o_buf; |
| input wb_clk_i; |
| wire wb_clk_i; |
| input [31:0] \wb_i.adr_i ; |
| wire [31:0] \wb_i.adr_i ; |
| input \wb_i.cyc_i ; |
| wire \wb_i.cyc_i ; |
| input [31:0] \wb_i.dat_i ; |
| wire [31:0] \wb_i.dat_i ; |
| input \wb_i.stb_i ; |
| wire \wb_i.stb_i ; |
| input \wb_i.we_i ; |
| wire \wb_i.we_i ; |
| output \wb_o.ack_o ; |
| wire \wb_o.ack_o ; |
| output [31:0] \wb_o.dat_o ; |
| wire [31:0] \wb_o.dat_o ; |
| input wb_rst_i; |
| wire wb_rst_i; |
| assign _0_ = \wb_i.cyc_i & \wb_i.stb_i ; |
| assign _1_ = _0_ & \wb_i.we_i ; |
| assign _2_ = _1_ ? \wb_i.dat_i : reg_o_buf; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _3_ <= 32'd0; |
| else _3_ <= _2_; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _4_ <= 33'h000000000; |
| else _4_ <= { reg_i, 1'h1 }; |
| assign reg_o_buf = _3_; |
| assign \wb_o.ack_o = _4_[0]; |
| assign \wb_o.dat_o = _4_[32:1]; |
| assign reg_o = reg_o_buf; |
| endmodule |
| |
| module wb_register32_81b45b9a32734d4367912d54c45d3716474431dc(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o); |
| wire _0_; |
| wire _1_; |
| wire [31:0] _2_; |
| reg [31:0] _3_; |
| reg [32:0] _4_; |
| input [31:0] reg_i; |
| wire [31:0] reg_i; |
| output [31:0] reg_o; |
| wire [31:0] reg_o; |
| wire [31:0] reg_o_buf; |
| input wb_clk_i; |
| wire wb_clk_i; |
| input [31:0] \wb_i.adr_i ; |
| wire [31:0] \wb_i.adr_i ; |
| input \wb_i.cyc_i ; |
| wire \wb_i.cyc_i ; |
| input [31:0] \wb_i.dat_i ; |
| wire [31:0] \wb_i.dat_i ; |
| input \wb_i.stb_i ; |
| wire \wb_i.stb_i ; |
| input \wb_i.we_i ; |
| wire \wb_i.we_i ; |
| output \wb_o.ack_o ; |
| wire \wb_o.ack_o ; |
| output [31:0] \wb_o.dat_o ; |
| wire [31:0] \wb_o.dat_o ; |
| input wb_rst_i; |
| wire wb_rst_i; |
| assign _0_ = \wb_i.cyc_i & \wb_i.stb_i ; |
| assign _1_ = _0_ & \wb_i.we_i ; |
| assign _2_ = _1_ ? \wb_i.dat_i : reg_o_buf; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _3_ <= 32'd14; |
| else _3_ <= _2_; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _4_ <= 33'h000000000; |
| else _4_ <= { reg_o_buf, 1'h1 }; |
| assign reg_o_buf = _3_; |
| assign \wb_o.ack_o = _4_[0]; |
| assign \wb_o.dat_o = _4_[32:1]; |
| assign reg_o = reg_o_buf; |
| endmodule |
| |
| module wb_register32_91a7f356ca6ce41b6122bd41e60c1f2eb8f0f0e3(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o); |
| wire _0_; |
| wire _1_; |
| wire [31:0] _2_; |
| reg [31:0] _3_; |
| reg [32:0] _4_; |
| input [31:0] reg_i; |
| wire [31:0] reg_i; |
| output [31:0] reg_o; |
| wire [31:0] reg_o; |
| wire [31:0] reg_o_buf; |
| input wb_clk_i; |
| wire wb_clk_i; |
| input [31:0] \wb_i.adr_i ; |
| wire [31:0] \wb_i.adr_i ; |
| input \wb_i.cyc_i ; |
| wire \wb_i.cyc_i ; |
| input [31:0] \wb_i.dat_i ; |
| wire [31:0] \wb_i.dat_i ; |
| input \wb_i.stb_i ; |
| wire \wb_i.stb_i ; |
| input \wb_i.we_i ; |
| wire \wb_i.we_i ; |
| output \wb_o.ack_o ; |
| wire \wb_o.ack_o ; |
| output [31:0] \wb_o.dat_o ; |
| wire [31:0] \wb_o.dat_o ; |
| input wb_rst_i; |
| wire wb_rst_i; |
| assign _0_ = \wb_i.cyc_i & \wb_i.stb_i ; |
| assign _1_ = _0_ & \wb_i.we_i ; |
| assign _2_ = _1_ ? \wb_i.dat_i : reg_o_buf; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _3_ <= 32'd0; |
| else _3_ <= _2_; |
| always @(posedge wb_clk_i, posedge wb_rst_i) |
| if (wb_rst_i) _4_ <= 33'h000000000; |
| else _4_ <= { reg_o_buf, 1'h1 }; |
| assign reg_o_buf = _3_; |
| assign \wb_o.ack_o = _4_[0]; |
| assign \wb_o.dat_o = _4_[32:1]; |
| assign reg_o = reg_o_buf; |
| endmodule |