blob: 8f5e281acc01d9935e68f16d835b7571a2c6fe95 [file] [log] [blame]
/* Generated by Yosys 0.22 (git sha1 f109fa3d4, gcc 10.2.1-6 -fPIC -Os) */
module fpga_cfg_shiftreg_2(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o);
reg [1:0] _0_;
input config_clk_i;
wire config_clk_i;
wire [1:0] config_data;
input config_ena_i;
wire config_ena_i;
output [1:0] config_o;
wire [1:0] config_o;
input config_shift_i;
wire config_shift_i;
output config_shift_o;
wire config_shift_o;
always @(posedge config_clk_i)
_0_ <= { config_shift_i, config_data[1] };
assign config_data = _0_;
assign config_shift_o = config_data[0];
assign config_o = config_data;
endmodule
module fpga_cfg_shiftreg_264(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o);
reg [263:0] _0_;
input config_clk_i;
wire config_clk_i;
wire [263:0] config_data;
input config_ena_i;
wire config_ena_i;
output [263:0] config_o;
wire [263:0] config_o;
input config_shift_i;
wire config_shift_i;
output config_shift_o;
wire config_shift_o;
always @(posedge config_clk_i)
_0_ <= { config_shift_i, config_data[263:1] };
assign config_data = _0_;
assign config_shift_o = config_data[0];
assign config_o = config_data;
endmodule
module fpga_logic_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_i, config_shift_o, outputs_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [263:0] _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
wire _38_;
wire _39_;
wire _40_;
wire _41_;
wire [31:0] cell_in;
wire [7:0] cell_out;
input clk_i;
wire clk_i;
input config_clk_i;
wire config_clk_i;
wire [263:0] config_data;
input config_ena_i;
wire config_ena_i;
wire [263:0] config_record;
input config_shift_i;
wire config_shift_i;
output config_shift_o;
wire config_shift_o;
input glb_rstn_i;
wire glb_rstn_i;
input [31:0] inputs_i;
wire [31:0] inputs_i;
output [7:0] outputs_o;
wire [7:0] outputs_o;
fpga_cfg_shiftreg_264 config_register (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_o(_11_),
.config_shift_i(config_shift_i),
.config_shift_o(_10_)
);
fpga_routing_mux_16_4_0 \crossbar:1.crossbar_mux (
.config_i(config_record[127:124]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_20_)
);
fpga_routing_mux_16_4_2 \crossbar:10.crossbar_mux (
.config_i(config_record[91:88]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_29_)
);
fpga_routing_mux_16_4_2 \crossbar:11.crossbar_mux (
.config_i(config_record[87:84]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_30_)
);
fpga_routing_mux_16_4_2 \crossbar:12.crossbar_mux (
.config_i(config_record[83:80]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_31_)
);
fpga_routing_mux_16_4_3 \crossbar:13.crossbar_mux (
.config_i(config_record[79:76]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_32_)
);
fpga_routing_mux_16_4_3 \crossbar:14.crossbar_mux (
.config_i(config_record[75:72]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_33_)
);
fpga_routing_mux_16_4_3 \crossbar:15.crossbar_mux (
.config_i(config_record[71:68]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_34_)
);
fpga_routing_mux_16_4_3 \crossbar:16.crossbar_mux (
.config_i(config_record[67:64]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_35_)
);
fpga_routing_mux_16_4_4 \crossbar:17.crossbar_mux (
.config_i(config_record[63:60]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_36_)
);
fpga_routing_mux_16_4_4 \crossbar:18.crossbar_mux (
.config_i(config_record[59:56]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_37_)
);
fpga_routing_mux_16_4_4 \crossbar:19.crossbar_mux (
.config_i(config_record[55:52]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_38_)
);
fpga_routing_mux_16_4_0 \crossbar:2.crossbar_mux (
.config_i(config_record[123:120]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_21_)
);
fpga_routing_mux_16_4_4 \crossbar:20.crossbar_mux (
.config_i(config_record[51:48]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_39_)
);
fpga_routing_mux_16_4_5 \crossbar:21.crossbar_mux (
.config_i(config_record[47:44]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_40_)
);
fpga_routing_mux_16_4_5 \crossbar:22.crossbar_mux (
.config_i(config_record[43:40]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_41_)
);
fpga_routing_mux_16_4_5 \crossbar:23.crossbar_mux (
.config_i(config_record[39:36]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_00_)
);
fpga_routing_mux_16_4_5 \crossbar:24.crossbar_mux (
.config_i(config_record[35:32]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_01_)
);
fpga_routing_mux_16_4_6 \crossbar:25.crossbar_mux (
.config_i(config_record[31:28]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_02_)
);
fpga_routing_mux_16_4_6 \crossbar:26.crossbar_mux (
.config_i(config_record[27:24]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_03_)
);
fpga_routing_mux_16_4_6 \crossbar:27.crossbar_mux (
.config_i(config_record[23:20]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_04_)
);
fpga_routing_mux_16_4_6 \crossbar:28.crossbar_mux (
.config_i(config_record[19:16]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_05_)
);
fpga_routing_mux_16_4_7 \crossbar:29.crossbar_mux (
.config_i(config_record[15:12]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_06_)
);
fpga_routing_mux_16_4_0 \crossbar:3.crossbar_mux (
.config_i(config_record[119:116]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_22_)
);
fpga_routing_mux_16_4_7 \crossbar:30.crossbar_mux (
.config_i(config_record[11:8]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_07_)
);
fpga_routing_mux_16_4_7 \crossbar:31.crossbar_mux (
.config_i(config_record[7:4]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_08_)
);
fpga_routing_mux_16_4_7 \crossbar:32.crossbar_mux (
.config_i(config_record[3:0]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_09_)
);
fpga_routing_mux_16_4_0 \crossbar:4.crossbar_mux (
.config_i(config_record[115:112]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_23_)
);
fpga_routing_mux_16_4_1 \crossbar:5.crossbar_mux (
.config_i(config_record[111:108]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_24_)
);
fpga_routing_mux_16_4_1 \crossbar:6.crossbar_mux (
.config_i(config_record[107:104]),
.route_i({ inputs_i[15:8], cell_out }),
.route_o(_25_)
);
fpga_routing_mux_16_4_1 \crossbar:7.crossbar_mux (
.config_i(config_record[103:100]),
.route_i({ inputs_i[23:16], cell_out }),
.route_o(_26_)
);
fpga_routing_mux_16_4_1 \crossbar:8.crossbar_mux (
.config_i(config_record[99:96]),
.route_i({ inputs_i[31:24], cell_out }),
.route_o(_27_)
);
fpga_routing_mux_16_4_2 \crossbar:9.crossbar_mux (
.config_i(config_record[95:92]),
.route_i({ inputs_i[7:0], cell_out }),
.route_o(_28_)
);
fpga_logic_cell \logic_cells:1.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[262:247]),
.\config_i.mux_config (config_record[263]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[31:28]),
.logic_o(_12_)
);
fpga_logic_cell \logic_cells:2.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[245:230]),
.\config_i.mux_config (config_record[246]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[27:24]),
.logic_o(_13_)
);
fpga_logic_cell \logic_cells:3.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[228:213]),
.\config_i.mux_config (config_record[229]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[23:20]),
.logic_o(_14_)
);
fpga_logic_cell \logic_cells:4.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[211:196]),
.\config_i.mux_config (config_record[212]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[19:16]),
.logic_o(_15_)
);
fpga_logic_cell \logic_cells:5.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[194:179]),
.\config_i.mux_config (config_record[195]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[15:12]),
.logic_o(_16_)
);
fpga_logic_cell \logic_cells:6.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[177:162]),
.\config_i.mux_config (config_record[178]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[11:8]),
.logic_o(_17_)
);
fpga_logic_cell \logic_cells:7.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[160:145]),
.\config_i.mux_config (config_record[161]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[7:4]),
.logic_o(_18_)
);
fpga_logic_cell \logic_cells:8.cell (
.clk_i(clk_i),
.\config_i.lut_config (config_record[143:128]),
.\config_i.mux_config (config_record[144]),
.glb_rstn_i(glb_rstn_i),
.logic_i(cell_in[3:0]),
.logic_o(_19_)
);
assign cell_in = { _23_, _22_, _21_, _20_, _27_, _26_, _25_, _24_, _31_, _30_, _29_, _28_, _35_, _34_, _33_, _32_, _39_, _38_, _37_, _36_, _01_, _00_, _41_, _40_, _05_, _04_, _03_, _02_, _09_, _08_, _07_, _06_ };
assign cell_out = { _19_, _18_, _17_, _16_, _15_, _14_, _13_, _12_ };
assign config_data = _11_;
assign config_record = { config_data[144:128], config_data[161:145], config_data[178:162], config_data[195:179], config_data[212:196], config_data[229:213], config_data[246:230], config_data[263:247], config_data[3:0], config_data[7:4], config_data[11:8], config_data[15:12], config_data[19:16], config_data[23:20], config_data[27:24], config_data[31:28], config_data[35:32], config_data[39:36], config_data[43:40], config_data[47:44], config_data[51:48], config_data[55:52], config_data[59:56], config_data[63:60], config_data[67:64], config_data[71:68], config_data[75:72], config_data[79:76], config_data[83:80], config_data[87:84], config_data[91:88], config_data[95:92], config_data[99:96], config_data[103:100], config_data[107:104], config_data[111:108], config_data[115:112], config_data[119:116], config_data[123:120], config_data[127:124] };
assign config_shift_o = _10_;
assign outputs_o = cell_out;
endmodule
module fpga_logic_cell(\config_i.lut_config , \config_i.mux_config , clk_i, glb_rstn_i, logic_i, logic_o);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire _4_;
wire _5_;
wire _6_;
wire _7_;
input clk_i;
wire clk_i;
input [15:0] \config_i.lut_config ;
wire [15:0] \config_i.lut_config ;
input \config_i.mux_config ;
wire \config_i.mux_config ;
input glb_rstn_i;
wire glb_rstn_i;
input [3:0] logic_i;
wire [3:0] logic_i;
wire [3:0] logic_in_buf;
output logic_o;
wire logic_o;
wire lut_out;
wire register_out;
assign _6_ = ~ \config_i.mux_config ;
assign _7_ = _6_ ? lut_out : register_out;
fpga_tech_register cell_reg (
.clk_i(clk_i),
.config_i_rst_polarity(1'h0),
.config_i_rst_value(1'h0),
.data_i(lut_out),
.data_o(_5_),
.rstn_i(glb_rstn_i)
);
fpga_tech_buffer \in_bufs:1.cell_tstart (
.i(logic_i[0]),
.z(_0_)
);
fpga_tech_buffer \in_bufs:2.cell_tstart (
.i(logic_i[1]),
.z(_1_)
);
fpga_tech_buffer \in_bufs:3.cell_tstart (
.i(logic_i[2]),
.z(_2_)
);
fpga_tech_buffer \in_bufs:4.cell_tstart (
.i(logic_i[3]),
.z(_3_)
);
fpga_lut_4 lut (
.config_i(\config_i.lut_config ),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_in_buf),
.logic_o(_4_)
);
assign lut_out = _4_;
assign register_out = _5_;
assign logic_in_buf = { _3_, _2_, _1_, _0_ };
assign logic_o = _7_;
endmodule
module fpga_lut_1(glb_rstn_i, config_i, logic_i, logic_o);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire _4_;
wire _5_;
wire _6_;
wire _7_;
wire _8_;
input [1:0] config_i;
wire [1:0] config_i;
input glb_rstn_i;
wire glb_rstn_i;
input logic_i;
wire logic_i;
output logic_o;
wire logic_o;
wire lut_out;
wire sublut0_out;
wire sublut1_out;
assign _0_ = ~ sublut0_out;
assign _1_ = ~ sublut1_out;
assign _2_ = _0_ & _1_;
assign _3_ = sublut0_out & sublut1_out;
assign _4_ = ~ logic_i;
assign _5_ = logic_i ? sublut1_out : 1'h0;
assign _6_ = _4_ ? sublut0_out : _5_;
assign _7_ = _3_ ? 1'h1 : _6_;
assign _8_ = _2_ ? 1'h0 : _7_;
assign lut_out = _8_;
assign sublut0_out = config_i[0];
assign sublut1_out = config_i[1];
assign logic_o = lut_out;
endmodule
module fpga_lut_2(glb_rstn_i, config_i, logic_i, logic_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
input [3:0] config_i;
wire [3:0] config_i;
input glb_rstn_i;
wire glb_rstn_i;
input [1:0] logic_i;
wire [1:0] logic_i;
output logic_o;
wire logic_o;
wire lut_out;
wire sublut0_out;
wire sublut1_out;
assign _02_ = ~ sublut0_out;
assign _03_ = ~ sublut1_out;
assign _04_ = _02_ & _03_;
assign _05_ = sublut0_out & sublut1_out;
assign _06_ = ~ logic_i[1];
assign _07_ = logic_i[1] ? sublut1_out : 1'h0;
assign _08_ = _06_ ? sublut0_out : _07_;
assign _09_ = _05_ ? 1'h1 : _08_;
assign _10_ = _04_ ? 1'h0 : _09_;
fpga_lut_1 \subluts.sublut0 (
.config_i(config_i[1:0]),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_i[0]),
.logic_o(_00_)
);
fpga_lut_1 \subluts.sublut1 (
.config_i(config_i[3:2]),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_i[0]),
.logic_o(_01_)
);
assign lut_out = _10_;
assign sublut0_out = _00_;
assign sublut1_out = _01_;
assign logic_o = lut_out;
endmodule
module fpga_lut_3(glb_rstn_i, config_i, logic_i, logic_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
input [7:0] config_i;
wire [7:0] config_i;
input glb_rstn_i;
wire glb_rstn_i;
input [2:0] logic_i;
wire [2:0] logic_i;
output logic_o;
wire logic_o;
wire lut_out;
wire sublut0_out;
wire sublut1_out;
assign _02_ = ~ sublut0_out;
assign _03_ = ~ sublut1_out;
assign _04_ = _02_ & _03_;
assign _05_ = sublut0_out & sublut1_out;
assign _06_ = ~ logic_i[2];
assign _07_ = logic_i[2] ? sublut1_out : 1'h0;
assign _08_ = _06_ ? sublut0_out : _07_;
assign _09_ = _05_ ? 1'h1 : _08_;
assign _10_ = _04_ ? 1'h0 : _09_;
fpga_lut_2 \subluts.sublut0 (
.config_i(config_i[3:0]),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_i[1:0]),
.logic_o(_00_)
);
fpga_lut_2 \subluts.sublut1 (
.config_i(config_i[7:4]),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_i[1:0]),
.logic_o(_01_)
);
assign lut_out = _10_;
assign sublut0_out = _00_;
assign sublut1_out = _01_;
assign logic_o = lut_out;
endmodule
module fpga_lut_4(glb_rstn_i, config_i, logic_i, logic_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire buffered_out0;
wire buffered_out1;
input [15:0] config_i;
wire [15:0] config_i;
input glb_rstn_i;
wire glb_rstn_i;
input [3:0] logic_i;
wire [3:0] logic_i;
output logic_o;
wire logic_o;
wire lut_out;
wire sublut0_out;
wire sublut1_out;
assign _02_ = ~ sublut0_out;
assign _03_ = ~ sublut1_out;
assign _04_ = _02_ & _03_;
assign _05_ = sublut0_out & sublut1_out;
assign _06_ = ~ logic_i[3];
assign _07_ = logic_i[3] ? sublut1_out : 1'h0;
assign _08_ = _06_ ? sublut0_out : _07_;
assign _09_ = _05_ ? 1'h1 : _08_;
assign _10_ = _04_ ? 1'h0 : _09_;
fpga_tech_buffer \breaker.loop_breaker (
.i(buffered_out0),
.z(_12_)
);
fpga_tech_buffer \breaker.lut_tfinish (
.i(lut_out),
.z(_11_)
);
fpga_tech_buffer \breaker.lut_tstart (
.i(buffered_out1),
.z(_13_)
);
fpga_lut_3 \subluts.sublut0 (
.config_i(config_i[7:0]),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_i[2:0]),
.logic_o(_00_)
);
fpga_lut_3 \subluts.sublut1 (
.config_i(config_i[15:8]),
.glb_rstn_i(glb_rstn_i),
.logic_i(logic_i[2:0]),
.logic_o(_01_)
);
assign lut_out = _10_;
assign sublut0_out = _00_;
assign sublut1_out = _01_;
assign buffered_out0 = _11_;
assign buffered_out1 = _12_;
assign logic_o = _13_;
endmodule
module fpga_routing_mux_16_4_0(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:1], 1'h0 };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_1(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:2], 1'h0, route_i[0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_2(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:3], 1'h0, route_i[1:0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_3(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:4], 1'h0, route_i[2:0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_4(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:5], 1'h0, route_i[3:0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_5(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:6], 1'h0, route_i[4:0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_6(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:7], 1'h0, route_i[5:0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_7(config_i, route_i, route_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
input [3:0] config_i;
wire [3:0] config_i;
input [15:0] route_i;
wire [15:0] route_i;
wire [15:0] route_int;
output route_o;
wire route_o;
assign _00_ = config_i[0] ? route_int[1] : route_int[0];
assign _01_ = config_i[0] ? route_int[5] : route_int[4];
assign _02_ = config_i[0] ? route_int[9] : route_int[8];
assign _03_ = config_i[0] ? route_int[13] : route_int[12];
assign _04_ = config_i[2] ? _11_ : _10_;
assign _05_ = config_i[0] ? route_int[3] : route_int[2];
assign _06_ = config_i[0] ? route_int[7] : route_int[6];
assign _07_ = config_i[0] ? route_int[11] : route_int[10];
assign _08_ = config_i[0] ? route_int[15] : route_int[14];
assign _09_ = config_i[2] ? _13_ : _12_;
assign _10_ = config_i[1] ? _05_ : _00_;
assign _11_ = config_i[1] ? _06_ : _01_;
assign _12_ = config_i[1] ? _07_ : _02_;
assign _13_ = config_i[1] ? _08_ : _03_;
assign _14_ = config_i[3] ? _09_ : _04_;
assign route_int = { route_i[15:8], 1'h0, route_i[6:0] };
assign route_o = _14_;
endmodule
module fpga_routing_mux_4_2_18446744073709551615(config_i, route_i, route_o);
wire _0_;
wire _1_;
wire _2_;
input [1:0] config_i;
wire [1:0] config_i;
input [3:0] route_i;
wire [3:0] route_i;
wire [3:0] route_int;
output route_o;
wire route_o;
assign _0_ = config_i[0] ? route_int[1] : route_int[0];
assign _1_ = config_i[0] ? route_int[3] : route_int[2];
assign _2_ = config_i[1] ? _1_ : _0_;
assign route_int = route_i;
assign route_o = _2_;
endmodule
module fpga_routing_mux_wcfg_4_2_18446744073709551615(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, route_o);
wire _0_;
wire _1_;
wire [1:0] _2_;
input config_clk_i;
wire config_clk_i;
wire [1:0] config_data;
input config_ena_i;
wire config_ena_i;
input config_shift_i;
wire config_shift_i;
output config_shift_o;
wire config_shift_o;
input [3:0] route_i;
wire [3:0] route_i;
output route_o;
wire route_o;
fpga_cfg_shiftreg_2 config_register (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_o(_2_),
.config_shift_i(config_shift_i),
.config_shift_o(_1_)
);
fpga_routing_mux_4_2_18446744073709551615 mux (
.config_i(config_data),
.route_i(route_i),
.route_o(_0_)
);
assign config_data = _2_;
assign config_shift_o = _1_;
assign route_o = _0_;
endmodule
(* top = 1 *)
module fpga_struct_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_up_i, inputs_right_i, inputs_down_i, inputs_left_i, config_shift_o, outputs_o);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
wire _38_;
wire _39_;
wire _40_;
wire _41_;
wire _42_;
wire _43_;
wire _44_;
wire _45_;
wire _46_;
wire _47_;
wire _48_;
wire _49_;
wire _50_;
wire _51_;
wire _52_;
wire _53_;
wire _54_;
wire _55_;
wire _56_;
wire _57_;
wire _58_;
wire _59_;
wire _60_;
wire _61_;
wire [7:0] _62_;
wire _63_;
wire _64_;
wire _65_;
wire [31:0] block_in;
wire [33:0] cfg_shift_chain;
input clk_i;
wire clk_i;
input config_clk_i;
wire config_clk_i;
input config_ena_i;
wire config_ena_i;
input config_shift_i;
wire config_shift_i;
output config_shift_o;
wire config_shift_o;
input glb_rstn_i;
wire glb_rstn_i;
input [31:0] inputs_down_i;
wire [31:0] inputs_down_i;
input [31:0] inputs_left_i;
wire [31:0] inputs_left_i;
input [31:0] inputs_right_i;
wire [31:0] inputs_right_i;
input [31:0] inputs_up_i;
wire [31:0] inputs_up_i;
wire \logic.logic_block:587 ;
wire [7:0] \logic.logic_block:588 ;
output [7:0] outputs_o;
wire [7:0] outputs_o;
fpga_logic_block \logic.logic_block (
.clk_i(clk_i),
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[0]),
.config_shift_o(_61_),
.glb_rstn_i(glb_rstn_i),
.inputs_i(block_in),
.outputs_o(_62_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:1.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[30]),
.config_shift_o(_26_),
.route_i({ inputs_down_i[24], inputs_down_i[16], inputs_down_i[8], inputs_down_i[0] }),
.route_o(_27_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:2.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[26]),
.config_shift_o(_28_),
.route_i({ inputs_down_i[25], inputs_down_i[17], inputs_down_i[9], inputs_down_i[1] }),
.route_o(_29_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:3.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[22]),
.config_shift_o(_30_),
.route_i({ inputs_down_i[26], inputs_down_i[18], inputs_down_i[10], inputs_down_i[2] }),
.route_o(_31_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:4.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[18]),
.config_shift_o(_32_),
.route_i({ inputs_down_i[27], inputs_down_i[19], inputs_down_i[11], inputs_down_i[3] }),
.route_o(_34_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:5.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[14]),
.config_shift_o(_35_),
.route_i({ inputs_down_i[28], inputs_down_i[20], inputs_down_i[12], inputs_down_i[4] }),
.route_o(_36_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:6.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[10]),
.config_shift_o(_37_),
.route_i({ inputs_down_i[29], inputs_down_i[21], inputs_down_i[13], inputs_down_i[5] }),
.route_o(_38_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:7.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[6]),
.config_shift_o(_39_),
.route_i({ inputs_down_i[30], inputs_down_i[22], inputs_down_i[14], inputs_down_i[6] }),
.route_o(_40_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:8.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[2]),
.config_shift_o(_41_),
.route_i({ inputs_down_i[31], inputs_down_i[23], inputs_down_i[15], inputs_down_i[7] }),
.route_o(_42_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:1.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[29]),
.config_shift_o(_43_),
.route_i({ inputs_left_i[24], inputs_left_i[16], inputs_left_i[8], inputs_left_i[0] }),
.route_o(_45_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:2.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[25]),
.config_shift_o(_46_),
.route_i({ inputs_left_i[25], inputs_left_i[17], inputs_left_i[9], inputs_left_i[1] }),
.route_o(_47_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:3.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[21]),
.config_shift_o(_48_),
.route_i({ inputs_left_i[26], inputs_left_i[18], inputs_left_i[10], inputs_left_i[2] }),
.route_o(_49_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:4.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[17]),
.config_shift_o(_50_),
.route_i({ inputs_left_i[27], inputs_left_i[19], inputs_left_i[11], inputs_left_i[3] }),
.route_o(_51_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:5.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[13]),
.config_shift_o(_52_),
.route_i({ inputs_left_i[28], inputs_left_i[20], inputs_left_i[12], inputs_left_i[4] }),
.route_o(_53_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:6.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[9]),
.config_shift_o(_54_),
.route_i({ inputs_left_i[29], inputs_left_i[21], inputs_left_i[13], inputs_left_i[5] }),
.route_o(_56_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:7.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[5]),
.config_shift_o(_57_),
.route_i({ inputs_left_i[30], inputs_left_i[22], inputs_left_i[14], inputs_left_i[6] }),
.route_o(_58_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:8.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[1]),
.config_shift_o(_59_),
.route_i({ inputs_left_i[31], inputs_left_i[23], inputs_left_i[15], inputs_left_i[7] }),
.route_o(_60_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:1.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[31]),
.config_shift_o(_08_),
.route_i({ inputs_right_i[24], inputs_right_i[16], inputs_right_i[8], inputs_right_i[0] }),
.route_o(_09_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:2.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[27]),
.config_shift_o(_10_),
.route_i({ inputs_right_i[25], inputs_right_i[17], inputs_right_i[9], inputs_right_i[1] }),
.route_o(_12_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:3.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[23]),
.config_shift_o(_13_),
.route_i({ inputs_right_i[26], inputs_right_i[18], inputs_right_i[10], inputs_right_i[2] }),
.route_o(_14_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:4.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[19]),
.config_shift_o(_15_),
.route_i({ inputs_right_i[27], inputs_right_i[19], inputs_right_i[11], inputs_right_i[3] }),
.route_o(_16_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:5.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[15]),
.config_shift_o(_17_),
.route_i({ inputs_right_i[28], inputs_right_i[20], inputs_right_i[12], inputs_right_i[4] }),
.route_o(_18_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:6.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[11]),
.config_shift_o(_19_),
.route_i({ inputs_right_i[29], inputs_right_i[21], inputs_right_i[13], inputs_right_i[5] }),
.route_o(_20_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:7.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[7]),
.config_shift_o(_21_),
.route_i({ inputs_right_i[30], inputs_right_i[22], inputs_right_i[14], inputs_right_i[6] }),
.route_o(_23_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:8.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[3]),
.config_shift_o(_24_),
.route_i({ inputs_right_i[31], inputs_right_i[23], inputs_right_i[15], inputs_right_i[7] }),
.route_o(_25_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:1.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[32]),
.config_shift_o(_00_),
.route_i({ inputs_up_i[24], inputs_up_i[16], inputs_up_i[8], inputs_up_i[0] }),
.route_o(_11_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:2.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[28]),
.config_shift_o(_22_),
.route_i({ inputs_up_i[25], inputs_up_i[17], inputs_up_i[9], inputs_up_i[1] }),
.route_o(_33_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:3.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[24]),
.config_shift_o(_44_),
.route_i({ inputs_up_i[26], inputs_up_i[18], inputs_up_i[10], inputs_up_i[2] }),
.route_o(_55_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:4.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[20]),
.config_shift_o(_63_),
.route_i({ inputs_up_i[27], inputs_up_i[19], inputs_up_i[11], inputs_up_i[3] }),
.route_o(_64_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:5.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[16]),
.config_shift_o(_65_),
.route_i({ inputs_up_i[28], inputs_up_i[20], inputs_up_i[12], inputs_up_i[4] }),
.route_o(_01_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:6.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[12]),
.config_shift_o(_02_),
.route_i({ inputs_up_i[29], inputs_up_i[21], inputs_up_i[13], inputs_up_i[5] }),
.route_o(_03_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:7.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[8]),
.config_shift_o(_04_),
.route_i({ inputs_up_i[30], inputs_up_i[22], inputs_up_i[14], inputs_up_i[6] }),
.route_o(_05_)
);
fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:8.block_in_mux (
.config_clk_i(config_clk_i),
.config_ena_i(config_ena_i),
.config_shift_i(cfg_shift_chain[4]),
.config_shift_o(_06_),
.route_i({ inputs_up_i[31], inputs_up_i[23], inputs_up_i[15], inputs_up_i[7] }),
.route_o(_07_)
);
assign cfg_shift_chain = { _00_, _08_, _26_, _43_, _22_, _10_, _28_, _46_, _44_, _13_, _30_, _48_, _63_, _15_, _32_, _50_, _65_, _17_, _35_, _52_, _02_, _19_, _37_, _54_, _04_, _21_, _39_, _57_, _06_, _24_, _41_, _59_, \logic.logic_block:587 , config_shift_i };
assign block_in = { _60_, _42_, _25_, _07_, _58_, _40_, _23_, _05_, _56_, _38_, _20_, _03_, _53_, _36_, _18_, _01_, _51_, _34_, _16_, _64_, _49_, _31_, _14_, _55_, _47_, _29_, _12_, _33_, _45_, _27_, _09_, _11_ };
assign \logic.logic_block:587 = _61_;
assign \logic.logic_block:588 = _62_;
assign config_shift_o = cfg_shift_chain[33];
assign outputs_o = \logic.logic_block:588 ;
endmodule