commit	8ff31d22c6126a4b8042a4d8304e5f821db4706c	[log] [tgz]
author	Guohua <yghlovelyf0616@gmail.com>	Wed Dec 07 03:36:44 2022 +0800
committer	Guohua <yghlovelyf0616@gmail.com>	Wed Dec 07 03:36:44 2022 +0800
tree	b84e6beab5be887e89d71e934eba0d7a0ff89e3e
parent	15e039e404243d3f82a29658955847810abfa663 [diff]

ok

Makefile[diff]
def/sky130_sram_1kbyte_1rw1r_32x256_8.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
def/user_project_wrapper.def.gz[Added - diff]
gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds.gz[Deleted - diff]
gds/user_project_wrapper.gds.gz[diff]
lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef.gz[Deleted - diff]
lef/user_proj_example.lef.gz[Deleted - diff]
lef/user_project_wrapper.lef.gz[diff]
lib/sky130_sram_1kbyte_1rw1r_32x256_8.lib[Deleted - diff]
lib/user_project_wrapper.lib[Deleted - diff]
lib/user_project_wrapper.lib.gz[Added - diff]
mag/sky130_sram_1kbyte_1rw1r_32x256_8.mag.gz[Deleted - diff]
mag/user_proj_example.mag.gz[Deleted - diff]
mag/user_project_wrapper.mag.gz[diff]
maglef/sky130_sram_1kbyte_1rw1r_32x256_8.mag.gz[Deleted - diff]
maglef/user_proj_example.mag.gz[Deleted - diff]
maglef/user_project_wrapper.mag.gz[diff]
openlane/top/greenrio.gds.gz[Added - diff]
openlane/top/greenrio.lef.gz[Added - diff]
openlane/user_proj_example/config.json[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
sdc/sky130_sram_1kbyte_1rw1r_32x256_8.sdc.gz[Deleted - diff]
sdc/user_project_wrapper.sdc.gz[diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf[Deleted - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf[Deleted - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf[Deleted - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf.gz[Added - diff]
sdf/sky130_sram_1kbyte_1rw1r_32x256_8.sdf[Deleted - diff]
sdf/user_project_wrapper.sdf[Deleted - diff]
sdf/user_project_wrapper.sdf.gz[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Deleted - diff]
signoff/user_proj_example/PDK_SOURCES[Deleted - diff]
signoff/user_proj_example/metrics.csv[Deleted - diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/metrics.csv[diff]
spef/multicorner/user_project_wrapper.nom.spef.gz[diff]
spef/sky130_sram_1kbyte_1rw1r_32x256_8.spef.gz[Deleted - diff]
spef/user_project_wrapper.spef.gz[diff]
spi/lvs/sky130_sram_1kbyte_1rw1r_32x256_8.spice.gz[Deleted - diff]
spi/lvs/user_project_wrapper.spice.gz[diff]
verilog/base.sdc[Deleted - diff]
verilog/gl/user_project_wrapper.nl.v[diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/defines.v[diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl_sram_out_cache/bus_arbiter.v[Deleted - diff]
verilog/rtl_sram_out_cache/caravel_defines.v[Deleted - diff]
verilog/rtl_sram_out_cache/data_ram_mux.v[Deleted - diff]
verilog/rtl_sram_out_cache/gpio.v[Deleted - diff]
verilog/rtl_sram_out_cache/greenrio.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/base.sdc[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/sky130_sram_1kbyte_1rw1r_32x256_8.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffe.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffr.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/l1dcache.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/params.vh[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v[Deleted - diff]
verilog/rtl_sram_out_cache/hehe/src/params.vh[Deleted - diff]
verilog/rtl_sram_out_cache/inc/rvj1_defines.v[Deleted - diff]
verilog/rtl_sram_out_cache/instr_ram_mux.v[Deleted - diff]
verilog/rtl_sram_out_cache/latch_map.v[Deleted - diff]
verilog/rtl_sram_out_cache/params.vh[Deleted - diff]
verilog/rtl_sram_out_cache/rvj1_caravel_soc.v[Deleted - diff]
verilog/rtl_sram_out_cache/timer.v[Deleted - diff]
verilog/rtl_sram_out_cache/to.v[Deleted - diff]
verilog/rtl_sram_out_cache/top.v[Deleted - diff]
verilog/rtl_sram_out_cache/user_project_wrapper.v[diff]
verilog/rtl_sram_out_cache/wishbone_mux.v[Deleted - diff]

102 files changed

tree: b84e6beab5be887e89d71e934eba0d7a0ff89e3e

README.md

RIOS Lab GreenRio1.0 RISC-V Processor GF180 Version

:exclamation: Important Note

It's a GF180-based openMPW project. We try to tape out our GreenRio1.0 at 180nm process. For more infomation, you can access:rioschip.