openlane/user_project_wrapper/config.json

{
    "DESIGN_NAME": "user_project_wrapper",
    "DESIGN_IS_CORE": 1,
    "RT_MAX_LAYER": "Metal4",
    "VERILOG_FILES": [
    "dir::../../verilog/rtl_sram_out_cache/caravel/defines.v",
    "dir::../../verilog/rtl_sram_out_cache/user_project_wrapper.v"
    ],
    "VERILOG_FILES_BLACKBOX":[
        "dir::../../verilog/rtl_sram_out_cache/greenrio.v"
        ],
    "EXTRA_LEFS":"dir::../top/greenrio.lef",
    "EXTRA_GDS_FILES":"dir::../top/greenrio.gds",
    "FP_PDN_MACRO_HOOKS":"greenrio vdd vss VDD VSS",
    "RUN_TAP_DECAP_INSERTION":0,
    "RUN_FILL_INSERTION":0,
    "RUN_TAP_DECAP_INSERTION":0,
    "SYNTH_ELABORATE_ONLY":1,
    "PL_RESIZER_DESIGN_OPTIMIZATIONS":0,
    "PL_RESIZER_TIMING_OPTIMIZATIONS":0,
    "PL_RESIZER_BUFFER_INPUT_PORTS":0,
    "PL_RESIZER_BUFFER_OUTPUT_PORTS":0,
    "FP_PDN_CHECK_NODES":0,
    "MACRO_PLACEMENT_CFG":"dir::macro.cfg",
    "CLOCK_PERIOD": 50,
    "CLOCK_PORT": "wb_clk_i",
    "PL_BASIC_PLACEMENT": 1,
    "DIODE_INSERTION_STRATEGY": 0,
    "RUN_CVC": 0,
    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "CLOCK_TREE_SYNTH": 0,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "MAGIC_ZEROIZE_ORIGIN": 0,
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 3000 3000",
    "UNIT": "2.4",
    "FP_IO_VEXTEND": "expr::2 * $UNIT",
    "FP_IO_HEXTEND": "expr::2 * $UNIT",
    "FP_IO_VLENGTH": "ref::$UNIT",
    "FP_IO_HLENGTH": "ref::$UNIT",
    "FP_IO_VTHICKNESS_MULT": 4,
    "FP_IO_HTHICKNESS_MULT": 4,
    "FP_PDN_CORE_RING": 1,
    "FP_PDN_CORE_RING_VWIDTH": 3.1,
    "FP_PDN_CORE_RING_HWIDTH": 3.1,
    "FP_PDN_CORE_RING_VOFFSET": 12.45,
    "FP_PDN_CORE_RING_HOFFSET": 12.45,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "ROUTING_CORES": 48,
    "LVS_CONNECT_BY_LABEL": 1,
    "RUN_KLAYOUT_XOR":0,
    "KLAYOUT_XOR_GDS":0,
    "KLAYOUT_XOR_XML":0,
    "RUN_KLAYOUT":0,
    "RUN_MAGIC_DRC":0,
    "RUN_KLAYOUT_DRC":0,
    "QUIT_ON_LVS_ERROR":0,
    "QUIT_ON_MAGIC_DRC":0,
    "QUIT_ON_NEGATIVE_WNS":0,
    "QUIT_ON_SLEW_VIOLATIONS":0,
    "QUIT_ON_TIMING_VIOLATIONS":0,
    "VDD_PIN":"vdd",
    "GND_PIN":"vss",
    "VDD_NETS": ["vdd"],
    "GND_NETS": ["vss"],
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "CLOCK_PERIOD": 50,
        "FP_PDN_CHECK_NODES": 0,
        "FP_PDN_ENABLE_RAILS": 0,
        "RT_MAX_LAYER": "Metal4",
        "DIE_AREA": "0 0 3000 3000",
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
        "DIODE_INSERTION_STRATEGY": 0,
        "FP_PDN_CHECK_NODES": 0,
        "MAGIC_WRITE_FULL_LEF": 0,
        "PL_RESIZER_DESIGN_OPTIMIZATIONS":0,
        "YOSYS_REWRITE_VERILOG":1,
        "FP_PDN_ENABLE_RAILS": 0
   }
}