commit	7cb1b88314024241002d67955ba1e626bc6673a7	[log] [tgz]
author	Wenting Zhang <zephray@outlook.com>	Thu Nov 24 18:47:53 2022 -0500
committer	Wenting Zhang <zephray@outlook.com>	Thu Nov 24 18:47:53 2022 -0500
tree	7cd490d2230282dd339cb8383853e350ebf32d4a
parent	0bce573edc79af7e94361951e30f86efac4e583f [diff]

Import VerilogBoy RTL

verilog/rtl/alu.v[Added - diff]
verilog/rtl/bootrom.mif[Added - diff]
verilog/rtl/boy.v[Added - diff]
verilog/rtl/brom.v[Added - diff]
verilog/rtl/clk_div.v[Added - diff]
verilog/rtl/common.v[Added - diff]
verilog/rtl/control.v[Added - diff]
verilog/rtl/cpu.v[Added - diff]
verilog/rtl/dma.v[Added - diff]
verilog/rtl/mbc5.v[Added - diff]
verilog/rtl/ppu.v[Added - diff]
verilog/rtl/regfile.v[Added - diff]
verilog/rtl/serial.v[Added - diff]
verilog/rtl/singleport_ram.v[Added - diff]
verilog/rtl/singlereg.v[Added - diff]
verilog/rtl/sound.v[Added - diff]
verilog/rtl/sound_channel_mix.v[Added - diff]
verilog/rtl/sound_length_ctr.v[Added - diff]
verilog/rtl/sound_noise.v[Added - diff]
verilog/rtl/sound_square.v[Added - diff]
verilog/rtl/sound_vol_env.v[Added - diff]
verilog/rtl/sound_wave.v[Added - diff]
verilog/rtl/timer.v[Added - diff]
verilog/sim/Makefile[Added - diff]
verilog/sim/dispsim.cpp[Added - diff]
verilog/sim/dispsim.h[Added - diff]
verilog/sim/main.cpp[Added - diff]
verilog/sim/mbcsim.cpp[Added - diff]
verilog/sim/mbcsim.h[Added - diff]
verilog/sim/memsim.cpp[Added - diff]
verilog/sim/memsim.h[Added - diff]
verilog/sim/mmrprobe.cpp[Added - diff]
verilog/sim/mmrprobe.h[Added - diff]
verilog/sim/rtl.mk[Added - diff]

34 files changed

tree: 7cd490d2230282dd339cb8383853e350ebf32d4a

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.