)]}'
{
  "commit": "7cb1b88314024241002d67955ba1e626bc6673a7",
  "tree": "7cd490d2230282dd339cb8383853e350ebf32d4a",
  "parents": [
    "0bce573edc79af7e94361951e30f86efac4e583f"
  ],
  "author": {
    "name": "Wenting Zhang",
    "email": "zephray@outlook.com",
    "time": "Thu Nov 24 18:47:53 2022 -0500"
  },
  "committer": {
    "name": "Wenting Zhang",
    "email": "zephray@outlook.com",
    "time": "Thu Nov 24 18:47:53 2022 -0500"
  },
  "message": "Import VerilogBoy RTL\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "944e11ff03258a3444a65b61bef75c3b1a746619",
      "new_mode": 33188,
      "new_path": "verilog/rtl/alu.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "77d25b394c370228126f1d04ada160f6f2d3dec8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/bootrom.mif"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "69c2d65e5432fc1d3b2dc5680e1bfcd6d7b6f1bf",
      "new_mode": 33188,
      "new_path": "verilog/rtl/boy.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1b6896bab71aaa0fb35a5deb59130f66147ba469",
      "new_mode": 33188,
      "new_path": "verilog/rtl/brom.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "715bfed9d51e582d836537824f8671b870c6dbb3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/clk_div.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f71c77fe103874a0c5b157f06283c864cb7dea9e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/common.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e272690041e304a6b7099d8a09ed7796e5034b76",
      "new_mode": 33188,
      "new_path": "verilog/rtl/control.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6b5998296d332cd5b78cf9d051c132a1aacb7860",
      "new_mode": 33188,
      "new_path": "verilog/rtl/cpu.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5aaadaae6900884388265234ef5f045f2854019f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/dma.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "97ffd6773f45efbd3aedf0936f5eabad54e92cd4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mbc5.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "bf4e1e8b439691379db49fcd4b5fa980121d0c76",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ppu.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "575070cfcc986b6ce1440ddf44f37a2131b276ac",
      "new_mode": 33188,
      "new_path": "verilog/rtl/regfile.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "30b03fa07e08c07a8459302d1127844ba99ef04d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/serial.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0c8d63026e8c08575b0ec632d904dd30b3d15a48",
      "new_mode": 33188,
      "new_path": "verilog/rtl/singleport_ram.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "783e04c4691d5dbf1cb1a47ee7e56f6e79d4efe1",
      "new_mode": 33188,
      "new_path": "verilog/rtl/singlereg.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2cabe888f59f7b6666dfac89658544fcb8c2d8d8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a9b03ed133290c1afe131d690fafb31756ef6381",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound_channel_mix.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3a1452a754ec6d15b8b977c00a418c545d902a15",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound_length_ctr.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a836bcff8f506edd0701ff9474004e240ba01caa",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound_noise.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8f85838bd1cd4b784c8f10e0a649048e9c94f97a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound_square.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "81cc07fac5f758ad0d00f65ee3add97c77cbe938",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound_vol_env.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "22bd632cb7e0cd1e7e50df0b3ed0e71b7c0a18fc",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sound_wave.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9d72628ed5645a11f87bd399d088dde7a5315197",
      "new_mode": 33188,
      "new_path": "verilog/rtl/timer.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "415ae0a01b2af5405eba1da7e6dea43b2ac1c184",
      "new_mode": 33188,
      "new_path": "verilog/sim/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c796b5ded66dce51668c8fbc810d591053876836",
      "new_mode": 33188,
      "new_path": "verilog/sim/dispsim.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e6ae898072992ec6545f595d6153233148a73a02",
      "new_mode": 33188,
      "new_path": "verilog/sim/dispsim.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c181510c026e5c9679fb1842a81d32345c55506a",
      "new_mode": 33188,
      "new_path": "verilog/sim/main.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "69a836fb73962632c19eeab7b96c93cfdadd8bef",
      "new_mode": 33188,
      "new_path": "verilog/sim/mbcsim.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "87c4f36f0476168dae8c585d6e145defe5926f72",
      "new_mode": 33188,
      "new_path": "verilog/sim/mbcsim.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0cbf3b0c379f2c0c54a89dad060408474dc8d7f5",
      "new_mode": 33188,
      "new_path": "verilog/sim/memsim.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8ce05d2c1ed506d40a957fdb21c4623b8d5f16c3",
      "new_mode": 33188,
      "new_path": "verilog/sim/memsim.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5ff5fc38ae7b925fd4f6116428b1f52001dfbc73",
      "new_mode": 33188,
      "new_path": "verilog/sim/mmrprobe.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ceff7cd02d1d96b272143898e1351fa1f185c4e8",
      "new_mode": 33188,
      "new_path": "verilog/sim/mmrprobe.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "fdc9c72d89a936ee1af738feb167b6f1f4e35a2b",
      "new_mode": 33188,
      "new_path": "verilog/sim/rtl.mk"
    }
  ]
}
