| Matt Venn | 17c02d3 | 2022-11-23 10:39:36 +0100 | [diff] [blame] | 1 | [submodule "verilog/rtl/vga-clock"] |
| 2 | path = verilog/rtl/vga-clock | ||||
| Russell L Friesenhahn | 90e5d11 | 2022-12-05 23:41:16 -0600 | [diff] [blame] | 3 | url = https://github.com/russellfriesenhahn/vga-clock |