| commit | 17c02d3757626e745d84501a5a2e90b11baf7d40 | [log] [tgz] |
|---|---|---|
| author | Matt Venn <matt@mattvenn.net> | Wed Nov 23 10:39:36 2022 +0100 |
| committer | Matt Venn <matt@mattvenn.net> | Wed Nov 23 10:39:36 2022 +0100 |
| tree | 38cb048caffc4a045d25b0147c359100ac423ac1 | |
| parent | 0bce573edc79af7e94361951e30f86efac4e583f [diff] [blame] |
ready for submission
diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..db39e02 --- /dev/null +++ b/.gitmodules
@@ -0,0 +1,3 @@ +[submodule "verilog/rtl/vga-clock"] + path = verilog/rtl/vga-clock + url = https://github.com/mattvenn/vga-clock