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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / f00bbc65df8364716cbcd448313393ded6b68189 / . / sky130 / magic / sky130.tech
blob: 49d7f3a8ce5bd926f011cdc6b9a9d08a1b3a15b8 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18# This file is designed to be used with magic versions
19# 8.3.24 or newer.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]20#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]21tech
22 format 35
23 TECHNAME
24end
25
26version
27 version REVISION
28 description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
29end
30
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]31#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]32# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]33# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]34# Status 8/14/20: Rev 2 (alpha):
35# Started updating with new device/model naming convention
36#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]37
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]38#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]39# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]40#------------------------------------------------------------------------
41# device name magic ID layer description
42#------------------------------------------------------------------------
43# sky130_fd_pr__nfet_01v8 nfet standard nFET
44# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]45# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
46# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]47# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]48# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]49# sky130_fd_pr__pfet_01v8 pfet standard pFET
50# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]51# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]52# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
53# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
54# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
55# sky130_fd_pr__nfet_03v3_nvt --- native nFET
56# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
57# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
58# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
60# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
61# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
62# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]63# sky130_fd_pr__diode_pw2nd_nvt nndiode diode with nndiff
64# sky130_fd_pr__diode_pw2nd_lvt ndiodelvt low Vt n+ diff diode
65# sky130_fd_pr__diode_pd2nw_lvt pdiodelvt low Vt p+ diff diode
66# sky130_fd_pr__diode_pd2nw_hvt pdiodehvt high Vt p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]67# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
68# sky130_fd_pr__npn_11v0 mvpbase thick oxide gated NPN
69# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]70# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
71# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
72# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]73# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]75# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]76# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
77# sky130_fd_pr__res_generic_po npres n+ poly resistor
78# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
79# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
80# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
81# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
82# sky130_fd_pr__cap_var mvvaractor thickox varactor
83# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]84#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]85# (*) Note that ppres may extract into some generic type called
86# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
87# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]88#
89# (**) nFET and pFET in standard cells are the same as devices
90# outside of the standard cell except for the DRC rule for
91# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
92#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]93#-------------------------------------------------------------
94# The following devices are not extracted but are represented
95# only by script-generated subcells in the PDK.
96#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]97# sky130_fd_pr__esd_nfet_01v8 ESD nFET
98# sky130_fd_pr__esd_nfet_g5v0d10v5 ESD thickox nFET
99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
100# sky130_fd_pr__esd_pfet_g5v0d10v5 ESD thickox pFET
101# sky130_fd_pr__special_nfet_pass_flash flash nFET device
102# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
103# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
104# sky130_fd_pr__cap_vpp_* Vpp cap
105# sky130_fd_pr__ind_* inductor
106# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]107#--------------------------------------------------------------
108
109#-----------------------------------------------------
110# Tile planes
111#-----------------------------------------------------
112
113planes
114 dwell,dw
115 well,w
116 active,a
117 locali,li1,li
118 metal1,m1
119 metal2,m2
120 metal3,m3
121#ifdef METAL5
122#ifdef MIM
123 cap1,c1
124#endif (MIM)
125 metal4,m4
126#ifdef MIM
127 cap2,c2
128#endif (MIM)
129 metal5,m5
130#endif (METAL5)
131#ifdef REDISTRIBUTION
132 metali,mi
133#endif
134 block,b
135 comment,c
136end
137
138#-----------------------------------------------------
139# Tile types
140#-----------------------------------------------------
141
142types
143# Deep nwell
144 dwell dnwell,dnw
145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
152 well mvpbase,mvnpn
153 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]154
155# Transistors
156 active nmos,ntransistor,nfet
157 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]158 -active npd,npdfet,sramnfet
159 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]160 active pmos,ptransistor,pfet
161 -active scpmos,scptransistor,scpfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]163 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet,nnfet
167 active varactor,varact,var
168 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]169
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]170 active pmoslvt,pfetlvt
171 active pmosmvt,pfetmvt
172 active pmoshvt,pfethvt
173 active nmoslvt,nfetlvt
174 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]175 -active nsonos,sonos
176
177# Diffusions
178 active ndiff,ndiffusion,ndif
179 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]180 active mvndiff,mvndiffusion,mvndif
181 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182 active ndiffc,ndcontact,ndc
183 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]184 active mvndiffc,mvndcontact,mvndc
185 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]186 active psubdiff,psubstratepdiff,ppdiff,ppd,psd
187 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]188 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
189 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]190 active psubdiffcont,psubstratepcontact,psc
191 active nsubdiffcont,nsubstratencontact,nsc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]192 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
193 active mvnsubdiffcont,mvnsubstratencontact,mvnsc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]194 -active obsactive
195 -active mvobsactive
196
197# Poly
198 active poly,p,polysilicon
199 active polycont,pc,pcontact,polycut,polyc
200 active xpolycontact,xpolyc,xpc
201
202# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]203 active npolyres,npres,mrp1
204 active ppolyres,ppres,xhrpoly
205 active xpolyres,xpres,xres,uhrpoly
206 active ndiffres,rnd,rdn,rndiff
207 active pdiffres,rpd,rdp,rpdiff
208 active mvndiffres,mvrnd,mvrdn,mvrndiff
209 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
210 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]211
212# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]213 active pdiode,pdi
214 active ndiode,ndi
215 active nndiode,nndi
216 active pdiodec,pdic
217 active ndiodec,ndic
218 active nndiodec,nndic
219 active mvpdiode,mvpdi
220 active mvndiode,mvndi
221 active mvpdiodec,mvpdic
222 active mvndiodec,mvndic
223 active pdiodelvt,pdilvt
224 active pdiodehvt,pdihvt
225 active ndiodelvt,ndilvt
226 active pdiodelvtc,pdilvtc
227 active pdiodehvtc,pdihvtc
228 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]229
230# Local Interconnect
231 locali locali,li1,li
232 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]233 locali rlocali,rli1,rli
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]234 locali viali,vial,lic,licon,m1c,v0
235 -locali obsli1,obsli
236 -locali obsli1c,obslic,obslicon
237
238# Metal 1
239 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]240 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 metal1 via1,m2contact,m2cut,m2c,via,v,v1
242 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]243 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]244 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]245
246# Metal 2
247 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]248 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]249 metal2 via2,m3contact,m3cut,m3c,v2
250 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 3
254 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 -metal3 obsm3
257#ifdef METAL5
258 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]259 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]260
261#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 cap1 mimcap,mim,capm
263 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]264#endif
265
266# Metal 4
267 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]269 -metal4 obsm4
270 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]271 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]272
273#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]274 cap2 mimcap2,mim2,capm2
275 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276#endif
277
278# Metal 5
279 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]280 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]281 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]282 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif (METAL5)
284
285#ifdef REDISTRIBUTION
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]286 metal5 mrdlcontact,mrdlc
287 metali metalrdl,mrdl,metrdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metali obsmrdl
289#endif (REDISTRIBUTION)
290
291# Miscellaneous
292 -block glass
293 -block fillblock
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]294 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]296# fixed resistor width identifiers
297 -comment res0p35
298 -comment res0p69
299 -comment res1p41
300 -comment res2p85
301 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]302
303end
304
305#-----------------------------------------------------
306# Magic contact types
307#-----------------------------------------------------
308
309contact
310 pc poly locali
311 ndc ndiff locali
312 pdc pdiff locali
313 nsc nsd locali
314 psc psd locali
315 ndic ndiode locali
316 ndilvtc ndiodelvt locali
317 nndic nndiode locali
318 pdic pdiode locali
319 pdilvtc pdiodelvt locali
320 pdihvtc pdiodehvt locali
321 xpc xpc locali
322
323 mvndc mvndiff locali
324 mvpdc mvpdiff locali
325 mvnsc mvnsd locali
326 mvpsc mvpsd locali
327 mvndic mvndiode locali
328 mvpdic mvpdiode locali
329
330 lic locali metal1
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]331 obslic obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]332
333 via1 metal1 metal2
334 via2 metal2 metal3
335#ifdef METAL5
336 via3 metal3 metal4
337 via4 metal4 metal5
338#endif (METAL5)
339 stackable
340
341#ifdef METAL5
342#ifdef MIM
343 # MiM cap contacts are not stackable!
344 mimcc mimcap metal4
345 mim2cc mimcap2 metal5
346#endif (MIM)
347
348 padl m1 m2 m3 m4 m5 glass
349#else
350 padl m1 m2 m3 glass
351#endif (!METAL5)
352
353#ifdef REDISTRIBUTION
354 mrdlc metal5 mrdl
355#endif (REDISTRIBUTION)
356end
357
358#-----------------------------------------------------
359# Layer aliases
360#-----------------------------------------------------
361
362aliases
363
364 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]365 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]366
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]367 allnfets nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]368 allpfets pfet,ppu,scpfet,mvpfet,pfethvt,pfetlvt,pfetmvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]369 allfets allnfets,allpfets,varactor,mvvaractor,varhvt
370
371 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
372 allnactive allnactivenonfet,allnfets
373 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
374 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar
375
376 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
377 allpactive allpactivenonfet,allpfets
378 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
379 allpactivetap *psd,*mvpsd
380
381 allactivenonfet allnactivenonfet,allpactivenonfet
382 allactive allactivenonfet,allfets
383
384 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
385
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]386 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]387 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388 alldifflv allndifflv,allpdifflv
389 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
390 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
391 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
392
393 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
394 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
395 alldiffmv allndiffmv,allpdiffmv
396 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
397 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
398 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
399 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
400 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
401 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
402
403 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
404 alldiff alldifflv,alldiffmv
405
406 allpolyres mrp1,xhrpoly,uhrpoly,rmp
407 allpolynonfet *poly,allpolyres,xpc
408 allpolynonres *poly,allfets,xpc
409
410 allpoly allpolynonfet,allfets
411 allpolynoncap *poly,xpc,allfets,allpolyres
412
413 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
414 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
415 allndiffcontmv mvndc,mvnsc,mvndic
416 allpdiffcontmv mvpdc,mvpsc,mvpdic
417 allndiffcont allndiffcontlv,allndiffcontmv
418 allpdiffcont allpdiffcontlv,allpdiffcontmv
419 alldiffcontlv allndiffcontlv,allpdiffcontlv
420 alldiffcontmv allndiffcontmv,allpdiffcontmv
421 alldiffcont alldiffcontlv,alldiffcontmv
422
423 allcont alldiffcont,pc
424
425 allres allpolyres,allactiveres
426
427 allli *locali,coreli,rli
428 allm1 *m1,rm1
429 allm2 *m2,rm2
430 allm3 *m3,rm3
431#ifdef METAL5
432 allm4 *m4,rm4
433 allm5 *m5,rm5
434#endif (METAL5)
435
436 allpad padl
437
438 psub pwell
439
440end
441
442#-----------------------------------------------------
443# Layer drawing styles
444#-----------------------------------------------------
445
446styles
447 styletype mos
448 dnwell cwell
449 nwell nwell
450 pwell pwell
451 rpwell pwell ptransistor_stripes
452 ndiff ndiffusion
453 pdiff pdiffusion
454 nsd ndiff_in_nwell
455 psd pdiff_in_pwell
456 nfet ntransistor ntransistor_stripes
457 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]458 npass ntransistor ntransistor_stripes
459 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]460 pfet ptransistor ptransistor_stripes
461 scpfet ptransistor ptransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]462 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]463 var polysilicon ndiff_in_nwell
464 ndc ndiffusion metal1 contact_X'es
465 pdc pdiffusion metal1 contact_X'es
466 nsc ndiff_in_nwell metal1 contact_X'es
467 psc pdiff_in_pwell metal1 contact_X'es
468
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]469 pnp nwell ntransistor_stripes
470 npn pwell ptransistor_stripes
471 mvnpn pwell hvpdiff_mask
472
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]473 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]474 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]475 pfethvt ptransistor ptransistor_stripes implant2
476 nfetlvt ntransistor ntransistor_stripes implant1
477 nsonos ntransistor implant3
478 varhvt polysilicon ndiff_in_nwell implant2
479
480 mvndiff ndiffusion hvndiff_mask
481 mvpdiff pdiffusion hvpdiff_mask
482 mvnsd ndiff_in_nwell hvndiff_mask
483 mvpsd pdiff_in_pwell hvpdiff_mask
484 mvnfet ntransistor ntransistor_stripes hvndiff_mask
485 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
486 mvpfet ptransistor ptransistor_stripes
487 mvvar polysilicon ndiff_in_nwell hvndiff_mask
488 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
489 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
490 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
491 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
492
493 poly polysilicon
494 pc polysilicon metal1 contact_X'es
495 npolyres polysilicon silicide_block nselect2
496 ppolyres polysilicon silicide_block pselect2
497 xpc polysilicon pselect2 metal1 contact_X'es
498 rmp polysilicon poly_resist_stripes
499
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]500 res0p35 implant1
501 res0p69 implant1
502 res1p41 implant1
503 res2p85 implant1
504 res5p73 implant1
505
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]506 pdiode pdiffusion pselect2
507 ndiode ndiffusion nselect2
508 pdiodec pdiffusion pselect2 metal1 contact_X'es
509 ndiodec ndiffusion nselect2 metal1 contact_X'es
510
511 nndiode ndiffusion nselect2 implant3
512 ndiodelvt ndiffusion nselect2 implant1
513 pdiodelvt pdiffusion pselect2 implant1
514 pdiodehvt pdiffusion pselect2 implant2
515 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
516 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
517 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
518
519 mvpdiode pdiffusion pselect2 hvpdiff_mask
520 mvndiode ndiffusion nselect2 hvndiff_mask
521 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
522 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
523 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
524
525 locali metal1
526 coreli metal1
527 rli metal1 poly_resist_stripes
528 lic metal1 metal2 via1arrow
529 obsli metal1
530 obslic metal1 metal2 via1arrow
531
532 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]533 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]534 rm1 metal2 poly_resist_stripes
535 obsm1 metal2
536 m2c metal2 metal3 via2arrow
537 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]538 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]539 rm2 metal3 poly_resist_stripes
540 obsm2 metal3
541 m3c metal3 metal4 via3alt
542 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]543 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]544 rm3 metal4 poly_resist_stripes
545 obsm3 metal4
546#ifdef METAL5
547#ifdef MIM
548 mimcap metal3 mems
549 mimcc metal3 contact_X'es mems
550 mimcap2 metal4 mems
551 mim2cc metal4 contact_X'es mems
552#endif (MIM)
553 via3 metal4 metal5 via4
554 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]555 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]556 rm4 metal5 poly_resist_stripes
557 obsm4 metal5
558 via4 metal5 metal6 via5
559 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]560 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]561 rm5 metal6 poly_resist_stripes
562 obsm5 metal6
563#endif (METAL5)
564#ifdef REDISTRIBUTION
565 mrdlc metal6 metal7 via6
566 metalrdl metal7
567 obsmrdl metal7
568#endif (REDISTRIBUTION)
569
570 glass overglass
571 mrp1 poly_resist poly_resist_stripes
572 xhrpoly poly_resist silicide_block
573 uhrpoly poly_resist
574 ndiffres ndiffusion ndop_stripes
575 pdiffres pdiffusion pdop_stripes
576 mvndiffres ndiffusion hvndiff_mask ndop_stripes
577 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
578 comment comment
579 error_p error_waffle
580 error_s error_waffle
581 error_ps error_waffle
582 fillblock cwell
583
584 obswell cwell
585 obsactive implant4
586
587#ifndef METAL5
588 padl metal4 via4 overglass
589#else
590 padl metal6 via6 overglass
591#endif
592
593 magnet substrate_field_implant
594 rotate via3alt
595 fence via5
596end
597
598#-----------------------------------------------------
599# Special paint/erase rules
600#-----------------------------------------------------
601
602compose
603 compose nfet poly ndiff
604 compose pfet poly pdiff
605 compose var poly nsd
606
607 compose mvnfet poly mvndiff
608 compose mvpfet poly mvpdiff
609 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]610
611 paint obslic locali via1
Tim Edwardsd44d18d2020-09-22 15:29:11 -0400[diff] [blame]612 paint obslic obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]613
614 paint ndc nwell pdc
615 paint nfet nwell pfet
616 paint scnfet nwell scpfet
617 paint ndiff nwell pdiff
618 paint psd nwell nsd
619 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]620 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]621
622 paint pdc pwell ndc
623 paint pfet pwell nfet
624 paint scpfet pwell scnfet
625 paint pdiff pwell ndiff
626 paint nsd pwell psd
627 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]628 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]629
630 paint pdc coreli pdc
631 paint ndc coreli ndc
632 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]633 paint nsc coreli nsc
634 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]635 paint viali coreli viali
636
637 paint coreli pdc pdc
638 paint coreli ndc ndc
639 paint coreli pc pc
640 paint coreli nsc nsc
641 paint coreli psc psc
642 paint coreli viali viali
643
644#ifdef METAL5
645 paint m4 obsm4 m4
646 paint m5 obsm5 m5
647#endif (METAL5)
648end
649
650#-----------------------------------------------------
651# Electrical connectivity
652#-----------------------------------------------------
653
654connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]655 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
656 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]657 *li,coreli *li,coreli
Tim Edwards48db3e12020-09-22 15:41:41 -0400[diff] [blame]658 *m1,m1fill,obslic *m1,m1fill,obslic
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]659 *m2,m2fill *m2,m2fill
660 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]661#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]662 *m4,m4fill *m4,m4fill
663 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]664#ifdef MIM
665 *mimcap *mimcap
666 *mimcap2 *mimcap2
667#endif (MIM)
668#endif (METAL5)
669 allnactivenonfet allnactivenonfet
670 allpactivenonfet allpactivenonfet
671 *poly,xpc,allfets *poly,xpc,allfets
672#ifdef REDISTRIBUTION
673 # RDL connects to m5 (i.e., padl) through glass cut
674 *mrdl *mrdl
675 glass metrdl
676#endif (REDISTRIBUTION)
677end
678
679#-----------------------------------------------------
680# CIF/GDS output layer definitions
681#-----------------------------------------------------
682# NOTE: All values in this section MUST be multiples of 25
683# or else magic will scale below the allowed layout grid size
684
685cifoutput
686
687#----------------------------------------------------------------
688style gdsii
689# NOTE: This section is used for actual GDS output
690#----------------------------------------------------------------
691 scalefactor 10 nanometers
692 options calma-permissive-labels
693 gridlimit 5
694
695#----------------------------------------------------------------
696# Create a temp layer from the cell bounding box for use in
697# generating ID layers. Note that "boundary", unlike "bbox",
698# requires the FIXED_BBOX property (abutment box) in the cell.
699#----------------------------------------------------------------
700 templayer CELLBOUND
701 boundary
702
703#----------------------------------------------------------------
704# BOUND
705#----------------------------------------------------------------
706 layer BOUND CELLBOUND
707 calma 235 4
708
709# Create a boundary outside of an abutment box, so that layers
710# can be made to stretch to the abutment box edges. First strink
711# so that any box that would be so small as to interact with
712# itself will be removed.
713
714 templayer CELLRING CELLBOUND
715 shrink 345
716 grow 545
717 and-not CELLBOUND
718
719#----------------------------------------------------------------
720# DNWELL
721#----------------------------------------------------------------
722
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]723 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]724 calma 64 18
725
726 layer PWRES rpw
727 and dnwell
728 calma 64 13
729
730#----------------------------------------------------------------
731# NWELL
732#----------------------------------------------------------------
733
734 layer NWELL allnwell
735 bloat-all rpw dnwell
736 and-not rpw,pwell
737 calma 64 20
738
739 layer WELLTXT
740 labels allnwell noport
741 calma 64 16
742
743 layer WELLPIN
744 labels allnwell port
745 calma 64 5
746
747#----------------------------------------------------------------
748# SUB (text/port only)
749#----------------------------------------------------------------
750
751 layer SUBTXT
752 labels pwell noport
753 calma 122 16
754
755 layer SUBPIN
756 labels pwell port
757 calma 64 59
758
759#----------------------------------------------------------------
760# DIFF
761#----------------------------------------------------------------
762
763 layer DIFF allnactivenontap,allpactivenontap,allactiveres
764 labels allnactivenontap,allpactivenontap
765 calma 65 20
766
767#----------------------------------------------------------------
768# TAP
769#----------------------------------------------------------------
770
771 layer TAP allnactivetap,allpactivetap
772 labels allnactivetap,allpactivetap
773 calma 65 44
774
775#----------------------------------------------------------------
776# PPLUS, NPLUS (PSDM, NSDM)
777#----------------------------------------------------------------
778
779 templayer basePPLUS pdiffres,mvpdiffres
780 grow 15
781 or xhrpoly,uhrpoly,xpc
782 grow 110
783 bloat-or allpactivetap * 125 allnactivenontap 0
784 bloat-or allpactivenontap * 125 allnactivetap 0
785 bridge 380 380
786
787 templayer extendPPLUS basePPLUS,CELLRING
788 grow 185
789 shrink 185
790 and-not CELLRING
791
792 layer PPLUS basePPLUS,extendPPLUS
793 close 265000
794 calma 94 20
795
796 templayer baseNPLUS ndiffres,mvndiffres
797 grow 125
798 bloat-or allnactivetap * 125 allpactivenontap 0
799 bloat-or allnactivenontap * 125 allpactivetap 0
800 bridge 380 380
801
802 templayer extendNPLUS baseNPLUS,CELLRING
803 grow 185
804 shrink 185
805 and-not CELLRING
806
807 layer NPLUS baseNPLUS,extendNPLUS
808 close 265000
809 calma 93 44
810
811#----------------------------------------------------------------
812# LVTN
813#----------------------------------------------------------------
814
815 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
816 grow 180
817 bridge 380 380
818 grow 185
819 shrink 185
820 close 265000
821 calma 125 44
822
823#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]824# HVTR
825#----------------------------------------------------------------
826
827 layer HVTR pfetmvt
828 grow 180
829 bridge 380 380
830 grow 185
831 shrink 185
832 close 265000
833 calma 18 20
834
835#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]836# HVTP
837#----------------------------------------------------------------
838
839 layer HVTP pfethvt,varhvt,*pdiodehvt
840 grow 180
841 bridge 380 380
842 grow 185
843 shrink 185
844 close 265000
845 calma 78 44
846
847#----------------------------------------------------------------
848# SONOS
849#----------------------------------------------------------------
850
851 layer SONOS nsonos
852 grow 100
853 grow-min 410
854 bridge 500 410
855 grow 250
856 shrink 250
857 calma 80 20
858
859#----------------------------------------------------------------
860# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]861# coreli layer indicates a cell needing COREID. Also, devices
862# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]863#----------------------------------------------------------------
864
865 layer COREID
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]866 bloat-all nsonos,coreli,ppu,npd,npass CELLBOUND
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]867 calma 81 2
868
869#----------------------------------------------------------------
870# STDCELL applies to all cells containing scnfet or scpfet.
871#----------------------------------------------------------------
872
873 layer STDCELL scnfet
874 bloat-all scpfet,scnfet CELLBOUND
875 calma 81 4
876
877#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]878# NPNID and PNPID apply to bipolar transistors
879#----------------------------------------------------------------
880
881 layer NPNID
882 bloat-all npn,mvnpn dnwell
883 calma 82 20
884
885 templayer pnparea pnp
886 grow 400
887
888 layer PNPID
889 bloat-all pnparea *psd
890 or pnparea
891 calma 82 44
892
893#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]894# RPM
895#----------------------------------------------------------------
896
897 layer RPM
898 bloat-all xhrpoly xpc
899 grow 200
900 grow-min 1270
901 grow 420
902 shrink 420
903 calma 86 20
904
905#----------------------------------------------------------------
906# URPM (2kOhms/sq. poly implant)
907#----------------------------------------------------------------
908
909 layer URPM
910 bloat-all uhrpoly xpc
911 grow 200
912 grow-min 1270
913 grow 420
914 shrink 420
915 calma 79 20
916
917#----------------------------------------------------------------
918# LDNTM (Tip implant for SONOS FETs)
919#----------------------------------------------------------------
920
921 layer LDNTM
922 bloat-all nsonos *ndiff
923 grow 185
924 grow 345
925 shrink 345
926 calma 11 44
927
928#----------------------------------------------------------------
929# HVNTM (Tip implant for MV ndiff devices)
930#----------------------------------------------------------------
931
932 templayer hvntm_block *mvpsd
933 grow 185
934
935 layer HVNTM
936 bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
937 bloat-all mvvaractor *mvnsd
938 and-not hvntm_block
939 grow 185
940 grow 345
941 shrink 345
942 calma 125 20
943
944#----------------------------------------------------------------
945# POLY
946#----------------------------------------------------------------
947
948 layer POLY allpoly
949 calma 66 20
950
951 layer POLYTXT
952 labels allpoly noport
953 calma 66 16
954
955 layer POLYPIN
956 labels allpoly port
957 calma 66 5
958
959#----------------------------------------------------------------
960# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
961#----------------------------------------------------------------
962
963 templayer baseTHKOX *mvpsd
964 grow-min 470
965 or alldiffmv,mvvar
966 grow 185
967 bloat-all alldiffmv nwell
968 grow-min 600
969 bridge 700 600
970
971 templayer extendTHKOX baseTHKOX,CELLRING
972 grow 345
973 shrink 345
974 and-not CELLRING
975
976 layer THKOX baseTHKOX,extendTHKOX
977 calma 75 20
978
979#----------------------------------------------------------------
980# CONT (LICON)
981#----------------------------------------------------------------
982
983 layer CONT allcont
984 squares-grid 0 170 170
985 calma 66 44
986
987 # Contact for pres is different than other LICON contacts
988 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
989 templayer xpc_horiz xpc
990 shrink 1007
991 grow 1007
992
993 layer CONT xpc
994 and-not xpc_horiz
995 # Force long edge vertical for contacts narrower than 2um
996 # Minimum space is 350 but 520 satisfies no. of contacts rule
997 slots 80 190 520 80 2000 350
998 calma 66 44
999
1000 layer CONT xpc
1001 and xpc_horiz
1002 # Force long edge vertical for contacts wider than 2um
1003 # Minimum space is 350 but 520 satisfies no. of contacts rule
1004 slots 80 2000 350 80 190 520
1005 calma 66 44
1006
1007#----------------------------------------------------------------
1008# NPC (Nitride poly cut)
1009# surrounds CONT (LICON) on poly only (i.e., pc)
1010#----------------------------------------------------------------
1011
1012 layer NPC pc
1013 squares-grid 0 170 170
1014 grow 100
1015 bridge 270 270
1016 grow 130
1017 shrink 130
1018 calma 95 20
1019
1020 # NPC is also generated on xhrpoly and uhrpoly resistors
1021
1022 layer NPC xpc,xhrpoly,uhrpoly
1023 # xpc surrounds precision_resistor by 0.095um
1024 grow 95
1025 grow 130
1026 shrink 130
1027 calma 95 20
1028
1029#----------------------------------------------------------------
1030# Device markers
1031#----------------------------------------------------------------
1032
1033 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1034 calma 65 13
1035
1036 layer POLYRES mrp1
1037 calma 66 13
1038
1039 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1040 layer POLYSHORT rmp
1041 calma 66 15
1042
1043 # POLYRES extends to edge of contact cut
1044 layer POLYRES xhrpoly,uhrpoly
1045 grow 60
1046 and xpc
1047 or xhrpoly,uhrpoly
1048 calma 66 13
1049
1050 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1051 # To be done: Expand to include anode, cathode, and guard ring
1052 calma 81 23
1053
1054#----------------------------------------------------------------
1055# LI
1056#----------------------------------------------------------------
1057 layer LI allli
1058 calma 67 20
1059
1060 layer LITXT
1061 labels *locali,coreli noport
1062 calma 67 16
1063
1064 layer LIPIN
1065 labels *locali,coreli port
1066 calma 67 5
1067
1068 layer LIRES rli
1069 labels rli
1070 calma 67 13
1071
1072#----------------------------------------------------------------
1073# MCON
1074#----------------------------------------------------------------
1075 layer MCON lic
1076 squares-grid 0 170 190
1077 calma 67 44
1078
1079#----------------------------------------------------------------
1080# MET1
1081#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1082 layer MET1 allm1,m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1083 calma 68 20
1084
1085 layer MET1TXT
1086 labels allm1 noport
1087 calma 68 16
1088
1089 layer MET1PIN
1090 labels allm1 port
1091 calma 68 5
1092
1093 layer MET1RES rm1
1094 labels rm1
1095 calma 68 13
1096
1097#----------------------------------------------------------------
1098# VIA1
1099#----------------------------------------------------------------
1100 layer VIA1 via1
1101 squares-grid 55 150 170
1102 calma 68 44
1103
1104#----------------------------------------------------------------
1105# MET2
1106#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1107 layer MET2 allm2,m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1108 calma 69 20
1109
1110 layer MET2TXT
1111 labels allm2 noport
1112 calma 69 16
1113
1114 layer MET2PIN
1115 labels allm2 port
1116 calma 69 5
1117
1118 layer MET2RES rm2
1119 labels rm2
1120 calma 69 13
1121
1122#----------------------------------------------------------------
1123# VIA2
1124#----------------------------------------------------------------
1125 layer VIA2 via2
1126 squares-grid 40 200 200
1127 calma 69 44
1128
1129#----------------------------------------------------------------
1130# MET3
1131#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1132 layer MET3 allm3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1133 calma 70 20
1134
1135 layer MET3TXT
1136 labels allm3 noport
1137 calma 70 16
1138
1139 layer MET3PIN
1140 labels allm3 port
1141 calma 70 5
1142
1143 layer MET3RES rm3
1144 labels rm3
1145 calma 70 13
1146
1147#ifdef METAL5
1148#----------------------------------------------------------------
1149# VIA3
1150#----------------------------------------------------------------
1151 layer VIA3 via3
1152#ifdef MIM
1153 or mimcc
1154#endif (MIM)
1155 squares-grid 60 200 200
1156 calma 70 44
1157
1158#----------------------------------------------------------------
1159# MET4
1160#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1161 layer MET4 allm4,m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1162 calma 71 20
1163
1164 layer MET4TXT
1165 labels allm4 noport
1166 calma 71 16
1167
1168 layer MET4PIN
1169 labels allm4 port
1170 calma 71 5
1171
1172 layer MET4RES rm4
1173 labels rm4
1174 calma 71 13
1175
1176#----------------------------------------------------------------
1177# VIA4
1178#----------------------------------------------------------------
1179 layer VIA4 via4
1180#ifdef MIM
1181 or mim2cc
1182#endif (MIM)
1183 squares-grid 190 800 800
1184 calma 71 44
1185
1186#----------------------------------------------------------------
1187# MET5
1188#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1189 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1190 calma 72 20
1191
1192 layer MET5TXT
1193 labels allm5 noport
1194 calma 72 16
1195
1196 layer MET5PIN
1197 labels allm5 port
1198 calma 72 5
1199
1200 layer MET5RES rm5
1201 labels rm5
1202 calma 72 13
1203
1204#endif (METAL5)
1205
1206#ifdef REDISTRIBUTION
1207#----------------------------------------------------------------
1208# RDL
1209#----------------------------------------------------------------
1210 layer RDL *metrdl
1211 calma 74 20
1212
1213 layer RDLTXT
1214 labels *metrdl noport
1215 calma 74 16
1216
1217 layer RDLPIN
1218 labels *metrdl port
1219 calma 74 5
1220
1221#endif REDISTRIBUTION
1222
1223#----------------------------------------------------------------
1224# GLASS
1225#----------------------------------------------------------------
1226 layer GLASS glass
1227 calma 76 20
1228
1229#ifdef MIM
1230#----------------------------------------------------------------
1231# CAPM
1232#----------------------------------------------------------------
1233 layer CAPM *mimcap
1234 labels mimcap
1235 calma 89 44
1236
1237 layer CAPM2 *mimcap2
1238 labels mimcap2
1239 calma 97 44
1240#endif (MIM)
1241
1242#----------------------------------------------------------------
1243# Chip top level marker for DRC latchup rules to check 15um
1244# distance to taps (otherwise 6um is used)
1245#----------------------------------------------------------------
1246
1247 layer LOWTAPDENSITY
1248 bbox top
1249 # Clear 200um for pads + 50um for required high tap density
1250 # in critical area.
1251 shrink 250000
1252 calma 81 14
1253
1254#----------------------------------------------------------------
1255# FILLBLOCK
1256#----------------------------------------------------------------
1257 layer FILLOBSM1 fillblock
1258 calma 62 24
1259
1260 layer FILLOBSM2 fillblock
1261 calma 105 52
1262
1263 layer FILLOBSM3 fillblock
1264 calma 107 24
1265
1266 layer FILLOBSM4 fillblock
1267 calma 112 4
1268
1269 render DNWELL cwell -0.1 0.1
1270 render NWELL nwell 0.0 0.2062
1271 render DIFF ndiffusion 0.2062 0.12
1272 render TAP pdiffusion 0.2062 0.12
1273 render POLY polysilicon 0.3262 0.18
1274 render CONT via 0.5062 0.43
1275 render LI metal1 0.9361 0.10
1276 render MCON via 1.0361 0.34
1277 render MET1 metal2 1.3761 0.36
1278 render VIA1 via 1.7361 0.27
1279 render MET2 metal3 2.0061 0.36
1280 render VIA2 via 2.3661 0.42
1281 render MET3 metal4 2.7861 0.845
1282#ifdef METAL5
1283 render VIA3 via 3.6311 0.39
1284 render MET4 metal5 4.0211 0.845
1285 render VIA4 via 4.8661 0.505
1286 render MET5 metal6 5.3711 1.26
1287 render CAPM metal8 2.4661 0.2
1288 render CAPM2 metal9 3.7311 0.2
1289#ifdef REDISTRIBUTION
1290 render RDL metal7 11.8834 4.0
1291#endif (!REDISTRIBUTION)
1292#endif (!METAL5)
1293
1294#----------------------------------------------------------------
1295style drc
1296#----------------------------------------------------------------
1297# NOTE: This style is used for DRC only, not for GDS output
1298#----------------------------------------------------------------
1299 scalefactor 10 nanometers
1300 options calma-permissive-labels
1301
1302 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1303 templayer dnwell_shrink dnwell
1304 shrink 1030
1305
1306 templayer nwell_missing dnwell
1307 grow 400
1308 and-not dnwell_shrink
1309 and-not nwell
1310
1311 # SONOS nFET devices must be in deep nwell
1312 templayer dnwell_missing nsonos
1313 and-not dnwell
1314
1315 # Define MiM cap bottom plate for spacing rule
1316 templayer mim_bottom
1317 bloat-all *mimcap *metal3
1318
1319 # Define MiM2 cap bottom plate for spacing rule
1320 templayer mim2_bottom
1321 bloat-all *mimcap2 *metal4
1322
1323 # Note that metal fill is performed by the foundry and so is not
1324 # an option for a cifoutput style.
1325
1326 # Check latchup rule (15um minimum from tap LICON center to any
1327 # non-tap diffusion. Note that to count as a tap, the diffusion
1328 # must be contacted to LI
1329
1330 templayer ptap_reach psc,mvpsc
1331 and-not dnwell
1332 # grow total is 15um. grow in 0.84um increments to ensure that
1333 # no nwell ring is crossed
1334 grow 840
1335 and-not nwell,dnwell
1336 grow 840
1337 and-not nwell,dnwell
1338 grow 840
1339 and-not nwell,dnwell
1340 grow 840
1341 and-not nwell,dnwell
1342 grow 840
1343 and-not nwell,dnwell
1344 grow 840
1345 and-not nwell,dnwell
1346 grow 840
1347 and-not nwell,dnwell
1348 grow 840
1349 and-not nwell,dnwell
1350 grow 840
1351 and-not nwell,dnwell
1352 grow 840
1353 and-not nwell,dnwell
1354 grow 840
1355 and-not nwell,dnwell
1356 grow 840
1357 and-not nwell,dnwell
1358 grow 840
1359 and-not nwell,dnwell
1360 grow 840
1361 and-not nwell,dnwell
1362 grow 840
1363 and-not nwell,dnwell
1364 grow 840
1365 and-not nwell,dnwell
1366 grow 840
1367 and-not nwell,dnwell
1368 grow 635
1369 and-not nwell,dnwell
1370
1371 templayer ptap_missing *ndiff,*mvndiff
1372 and-not dnwell
1373 and-not ptap_reach
1374
1375 templayer ntap_reach nsc,mvnsc
1376 # grow total is 15um. grow in 1.27um increments to ensure that
1377 # no nwell ring is crossed. There is no difference between
1378 # ntaps in and out of deep nwell.
1379 grow 1270
1380 and nwell
1381 grow 1270
1382 and nwell
1383 grow 1270
1384 and nwell
1385 grow 1270
1386 and nwell
1387 grow 1270
1388 and nwell
1389 grow 1270
1390 and nwell
1391 grow 1270
1392 and nwell
1393 grow 1270
1394 and nwell
1395 grow 1270
1396 and nwell
1397 grow 1270
1398 and nwell
1399 grow 1270
1400 and nwell
1401 grow 945
1402 and nwell
1403
1404 templayer ntap_missing *pdiff,*mvpdiff
1405 and-not dnwell
1406 and-not ntap_reach
1407
1408 templayer dptap_reach psc,mvpsc
1409 and dnwell
1410 grow 840
1411 and-not nwell
1412 and dnwell
1413 grow 840
1414 and-not nwell
1415 and dnwell
1416 grow 840
1417 and-not nwell
1418 and dnwell
1419 grow 840
1420 and-not nwell
1421 and dnwell
1422 grow 840
1423 and-not nwell
1424 and dnwell
1425 grow 840
1426 and-not nwell
1427 and dnwell
1428 grow 840
1429 and-not nwell
1430 and dnwell
1431 grow 840
1432 and-not nwell
1433 and dnwell
1434 grow 840
1435 and-not nwell
1436 and dnwell
1437 grow 840
1438 and-not nwell
1439 and dnwell
1440 grow 840
1441 and-not nwell
1442 and dnwell
1443 grow 840
1444 and-not nwell
1445 and dnwell
1446 grow 840
1447 and-not nwell
1448 and dnwell
1449 grow 840
1450 and-not nwell
1451 and dnwell
1452 grow 840
1453 and-not nwell
1454 and dnwell
1455 grow 840
1456 and-not nwell
1457 and dnwell
1458 grow 840
1459 and-not nwell
1460 and dnwell
1461 grow 635
1462 and-not nwell
1463 and dnwell
1464
1465 templayer dptap_missing *ndiff,*mvndiff
1466 and dnwell
1467 and-not dptap_reach
1468
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1469 templayer m1_small_hole allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1470 close 140000
1471
1472 templayer m1_hole_empty m1_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1473 and-not allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1474
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1475 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1476 close 140000
1477
1478 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1479 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1480
1481#ifdef EXPERIMENTAL
1482#----------------------------------------------------------------
1483style paint
1484#----------------------------------------------------------------
1485# NOTE: This style is used for database manipulations only via
1486# the "cif paint" command.
1487#----------------------------------------------------------------
1488
1489 scalefactor 10 nanometers
1490
1491 templayer m1grow *m1
1492 grow 290
1493
1494 # layer listrap: Use the following set of commands to strap local
1495 # interconnect wires with metal1 (inside the cursor box) to satisfy
1496 # the maximum aspect ratio rule for local interconnect:
1497 #
1498 # tech unlock *
1499 # cif ostyle paint
1500 # cif paint m1strap comment
1501 # cif paint m1strap m1
1502 # cif paint listrap licon
1503 # erase comment
1504
1505 templayer m1strap *li
1506 and-not m1grow
1507 grow 30
1508
1509 templayer listrap comment
1510 slots 30 170 170 60
1511
1512#endif (EXPERIMENTAL)
1513
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1514#----------------------------------------------------------------
1515style wafflefill
1516#----------------------------------------------------------------
1517# Style used by scripts for automatically generating fill layers
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1518#----------------------------------------------------------------
1519 scalefactor 10 nanometers
1520 options calma-permissive-labels
1521 gridlimit 5
1522
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1523#----------------------------------------------------------------
1524# Generate guard-band around nwells to keep FOM from crossing
1525# Spacing from nwell = Diff/Tap 9 = 0.34um
1526# Enclosure by nwell = Diff/Tap 8 = 0.18um
1527#----------------------------------------------------------------
1528 templayer well_shrink nwell
1529 shrink 180
1530 templayer well_guardband nwell
1531 grow 340
1532 and-not well_shrink
1533
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1534#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1535# Interleaved FOM and POLY fill
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1536#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1537 templayer slots_fom_pass1
1538 bbox top
1539 slots 0 4080 1320 0 4080 1320 1360 0
1540 templayer obstruct_fom_pass1 alldiff,allpoly,rpw
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1541 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1542 or well_guardband
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1543 templayer fomfill_pass1 slots_fom_pass1
1544 and-not obstruct_fom_pass1
1545 shrink 2035
1546 grow 2035
1547
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1548#---------------------------------------------------
1549
1550 templayer slots_poly_pass1
1551 bbox top
1552 slots 0 720 360 0 720 360 240 0
1553 templayer obstruct_poly_pass1 alldiff,allpoly,rpw
1554 grow 700
1555 or fomfill_pass1
1556 grow 300
1557 or well_guardband
1558 templayer polyfill_pass1 slots_poly_pass1
1559 and-not obstruct_poly_pass1
1560 shrink 355
1561 grow 355
1562
1563#---------------------------------------------------
1564
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1565 templayer slots_fom_pass2
1566 bbox top
1567 slots 0 2500 1320 0 2500 1320 1360 0
1568 templayer obstruct_fom_pass2 fomfill_pass1
1569 grow 820
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1570 grow 200
1571 or polyfill_pass1
1572 grow 300
1573 or obstruct_fom_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1574 templayer fomfill_pass2 slots_fom_pass2
1575 and-not obstruct_fom_pass2
1576 shrink 1245
1577 grow 1245
1578
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1579#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1580
1581 templayer slots_poly_coarse
1582 bbox top
1583 slots 0 720 360 0 720 360 240 120
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1584 templayer obstruct_poly_coarse polyfill_pass1
1585 grow 60
1586 or fomfill_pass1,fomfill_pass2
1587 grow 300
1588 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1589 templayer polyfill_coarse slots_poly_coarse
1590 and-not obstruct_poly_coarse
1591 shrink 355
1592 grow 355
1593
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1594#---------------------------------------------------
1595
1596 templayer slots_fom_coarse
1597 bbox top
1598 slots 0 1500 1320 0 1500 1320 1360 0
1599 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1600 grow 1020
1601 or polyfill_pass1,polyfill_coarse
1602 grow 300
1603 or obstruct_fom_pass1
1604 templayer fomfill_coarse slots_fom_coarse
1605 and-not obstruct_fom_coarse
1606 shrink 745
1607 grow 745
1608
1609#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1610 templayer slots_poly_medium
1611 bbox top
1612 slots 0 540 360 0 540 360 240 100
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1613 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
1614 grow 1010
1615 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1616 templayer polyfill_medium slots_poly_medium
1617 and-not obstruct_poly_medium
1618 shrink 265
1619 grow 265
1620
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1621#---------------------------------------------------
1622
1623 templayer slots_fom_fine
1624 bbox top
1625 slots 0 500 400 0 500 400 160 0
1626 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1627 grow 1320
1628 or obstruct_fom_pass1
1629 templayer fomfill_fine slots_fom_fine
1630 and-not obstruct_fom_fine
1631 shrink 245
1632 grow 245
1633
1634#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1635 templayer slots_poly_fine
1636 bbox top
1637 slots 0 480 360 0 480 360 240 200
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1638 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1639 grow 650
1640 or polyfill_pass1,polyfill_coarse,polyfill_medium
1641 grow 360
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1642 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1643 templayer polyfill_fine slots_poly_fine
1644 and-not obstruct_poly_fine
1645 shrink 235
1646 grow 235
1647
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1648#---------------------------------------------------
1649 templayer fomfill fomfill_pass1
1650 or fomfill_pass2
1651 or fomfill_coarse
1652 or fomfill_fine
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1653
1654 templayer polyfill polyfill_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1655 or polyfill_coarse
1656 or polyfill_medium
1657 or polyfill_fine
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1658
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1659 layer FOMMASK fomfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1660 calma 23 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1661 layer POLYMASK polyfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1662 calma 28 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1663
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1664#---------------------------------------------------
1665# MET1 fill
1666#---------------------------------------------------
1667 templayer slots_m1_coarse
1668 bbox top
1669 slots 0 2000 200 0 2000 200 700 0
1670 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock
1671 grow 3000
1672 templayer met1fill_coarse slots_m1_coarse
1673 and-not obstruct_m1_coarse
1674 shrink 995
1675 grow 995
1676
1677 templayer slots_m1_medium
1678 bbox top
1679 slots 0 1000 200 0 1000 200 700 0
1680 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock
1681 grow 2800
1682 or met1fill_coarse
1683 grow 200
1684 templayer met1fill_medium slots_m1_medium
1685 and-not obstruct_m1_medium
1686 shrink 495
1687 grow 495
1688
1689 templayer slots_m1_fine
1690 bbox top
1691 slots 0 580 200 0 580 200 700 0
1692 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock
1693 grow 300
1694 or met1fill_coarse,met1fill_medium
1695 grow 200
1696 templayer met1fill_fine slots_m1_fine
1697 and-not obstruct_m1_fine
1698 shrink 285
1699 grow 285
1700
1701 templayer slots_m1_veryfine
1702 bbox top
1703 slots 0 300 200 0 300 200 100 50
1704 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock
1705 grow 100
1706 or met1fill_coarse,met1fill_medium,met1fill_fine
1707 grow 200
1708 templayer met1fill_veryfine slots_m1_veryfine
1709 and-not obstruct_m1_veryfine
1710 shrink 145
1711 grow 145
1712
1713 layer MET1MASK met1fill_coarse
1714 or met1fill_medium
1715 or met1fill_fine
1716 or met1fill_veryfine
1717 calma 36 0
1718
1719#---------------------------------------------------
1720# MET2 fill
1721#---------------------------------------------------
1722 templayer slots_m2_coarse
1723 bbox top
1724 slots 0 2000 200 0 2000 200 700 350
1725 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock
1726 grow 3000
1727 templayer met2fill_coarse slots_m2_coarse
1728 and-not obstruct_m2
1729 shrink 995
1730 grow 995
1731
1732 templayer slots_m2_medium
1733 bbox top
1734 slots 0 1000 200 0 1000 200 700 350
1735 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock
1736 grow 2800
1737 or met2fill_coarse
1738 grow 200
1739 templayer met2fill_medium slots_m2_medium
1740 and-not obstruct_m2_medium
1741 shrink 495
1742 grow 495
1743
1744 templayer slots_m2_fine
1745 bbox top
1746 slots 0 580 200 0 580 200 700 350
1747 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock
1748 grow 300
1749 or met2fill_coarse,met2fill_medium
1750 grow 200
1751 templayer met2fill_fine slots_m2_fine
1752 and-not obstruct_m2_fine
1753 shrink 285
1754 grow 285
1755
1756 templayer slots_m2_veryfine
1757 bbox top
1758 slots 0 300 200 0 300 200 100 100
1759 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock
1760 grow 100
1761 or met2fill_coarse,met2fill_medium,met2fill_fine
1762 grow 200
1763 templayer met2fill_veryfine slots_m2_veryfine
1764 and-not obstruct_m2_veryfine
1765 shrink 145
1766 grow 145
1767
1768 layer MET2MASK met2fill_coarse
1769 or met2fill_medium
1770 or met2fill_fine
1771 or met2fill_veryfine
1772 calma 41 0
1773
1774#---------------------------------------------------
1775# MET3 fill
1776#---------------------------------------------------
1777 templayer slots_m3_coarse
1778 bbox top
1779 slots 0 2000 300 0 2000 300 700 700
1780 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock
1781 grow 3000
1782 templayer met3fill_coarse slots_m3_coarse
1783 and-not obstruct_m3
1784 shrink 995
1785 grow 995
1786
1787 templayer slots_m3_medium
1788 bbox top
1789 slots 0 1000 300 0 1000 300 700 700
1790 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock
1791 grow 2700
1792 or met3fill_coarse
1793 grow 300
1794 templayer met3fill_medium slots_m3_medium
1795 and-not obstruct_m3_medium
1796 shrink 495
1797 grow 495
1798
1799 templayer slots_m3_fine
1800 bbox top
1801 slots 0 580 300 0 580 300 700 700
1802 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock
1803 grow 200
1804 or met3fill_coarse,met3fill_medium
1805 grow 300
1806 templayer met3fill_fine slots_m3_fine
1807 and-not obstruct_m3_fine
1808 shrink 285
1809 grow 285
1810
1811 templayer slots_m3_veryfine
1812 bbox top
1813 slots 0 400 300 0 400 300 150 200
1814 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock
1815 or met3fill_coarse,met3fill_medium,met3fill_fine
1816 grow 300
1817 templayer met3fill_veryfine slots_m3_veryfine
1818 and-not obstruct_m3_veryfine
1819 shrink 195
1820 grow 195
1821
1822 layer MET3MASK met3fill_coarse
1823 or met3fill_medium
1824 or met3fill_fine
1825 or met3fill_veryfine
1826 calma 34 0
1827
1828#ifdef METAL5
1829#---------------------------------------------------
1830# MET4 fill
1831#---------------------------------------------------
1832 templayer slots_m4_coarse
1833 bbox top
1834 slots 0 2000 300 0 2000 300 700 1050
1835 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock
1836 grow 3000
1837 templayer met4fill_coarse slots_m4_coarse
1838 and-not obstruct_m4
1839 shrink 995
1840 grow 995
1841
1842 templayer slots_m4_medium
1843 bbox top
1844 slots 0 1000 300 0 1000 300 700 1050
1845 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock
1846 grow 2700
1847 or met4fill_coarse
1848 grow 300
1849 templayer met4fill_medium slots_m4_medium
1850 and-not obstruct_m4_medium
1851 shrink 495
1852 grow 495
1853
1854 templayer slots_m4_fine
1855 bbox top
1856 slots 0 580 300 0 580 300 700 1050
1857 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock
1858 grow 200
1859 or met4fill_coarse,met4fill_medium
1860 grow 300
1861 templayer met4fill_fine slots_m4_fine
1862 and-not obstruct_m4_fine
1863 shrink 285
1864 grow 285
1865
1866 templayer slots_m4_veryfine
1867 bbox top
1868 slots 0 400 300 0 400 300 150 300
1869 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock
1870 or met4fill_coarse,met4fill_medium,met4fill_fine
1871 grow 300
1872 templayer met4fill_veryfine slots_m4_veryfine
1873 and-not obstruct_m4_veryfine
1874 shrink 195
1875 grow 195
1876
1877 layer MET4MASK met4fill_coarse
1878 or met4fill_medium
1879 or met4fill_fine
1880 or met4fill_veryfine
1881 calma 51 0
1882
1883#---------------------------------------------------
1884# MET5 fill
1885#---------------------------------------------------
1886 templayer slots_m5
1887 bbox top
1888 slots 0 3000 1600 0 3000 1600 1000 100
1889 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
1890 grow 3000
1891 templayer met5fill_gen slots_m5
1892 and-not obstruct_m5
1893 shrink 1495
1894 grow 1495
1895
1896 layer MET5MASK met5fill_gen
1897 calma 59 0
1898#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1899
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1900end
1901
1902#-----------------------------------------------------------------------
1903cifinput
1904#-----------------------------------------------------------------------
1905# NOTE: All values in this section MUST be multiples of 25
1906# or else magic will scale below the allowed layout grid size
1907#-----------------------------------------------------------------------
1908
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]1909style sky130
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1910 scalefactor 10 nanometers
1911 gridlimit 5
1912
1913 options ignore-unknown-layer-labels no-reconnect-labels
1914
1915#ifndef MIM
1916 ignore CAPM
1917 ignore CAPM2
1918#endif (!MIM)
1919#ifndef METAL5
1920 ignore MET4,VIA3
1921 ignore MET5,VIA4
1922#endif
1923 ignore NPC
1924 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1925 ignore CAPID
1926 ignore LDNTM
1927 ignore HVNTM
1928 ignore POLYMOD
1929 ignore LOWTAPDENSITY
1930
1931 layer nwell NWELL,WELLTXT,WELLPIN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1932 and-not PNPID
1933 labels NWELL
1934 labels WELLTXT text
1935 labels WELLPIN port
1936
1937 layer pnp NWELL,WELLTXT,WELLPIN
1938 and PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1939 labels NWELL
1940 labels WELLTXT text
1941 labels WELLPIN port
1942
1943 layer pwell SUBTXT,SUBPIN
1944 labels SUBTXT text
1945 labels SUBPIN port
1946
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]1947 # Always draw pwell under p-tap
1948 layer pwell TAP
1949 and-not NWELL
1950
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1951 layer dnwell DNWELL
1952 labels DNWELL
1953
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1954 layer npn DNWELL
1955 and-not NWELL
1956 and NPNID
1957
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1958 layer rpw PWRES
1959 and DNWELL
1960 labels PWRES
1961
1962 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
1963 and-not POLY
1964 and-not NWELL
1965 and-not PPLUS
1966 and-not DIODE
1967 and-not DIFFRES
1968 and-not THKOX
1969 and NPLUS
1970 copyup ndifcheck
1971 labels DIFF
1972 labels DIFFTXT text
1973 labels DIFFPIN port
1974 labels TAPPIN port
1975
1976 layer ndiff ndiffarea
1977
1978 # Copy ndiff areas up for contact checks
1979 templayer xndifcheck ndifcheck
1980 copyup ndifcheck
1981
1982 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
1983 and-not POLY
1984 and-not NWELL
1985 and-not PPLUS
1986 and-not DIODE
1987 and-not DIFFRES
1988 and THKOX
1989 and NPLUS
1990 copyup ndifcheck
1991 labels DIFF
1992 labels DIFFTXT text
1993 labels DIFFPIN port
1994
1995 layer mvndiff mvndiffarea
1996
1997 # Copy ndiff areas up for contact checks
1998 templayer mvxndifcheck mvndifcheck
1999 copyup mvndifcheck
2000
2001 layer ndiode DIFF
2002 and NPLUS
2003 and DIODE
2004 and-not NWELL
2005 and-not POLY
2006 and-not PPLUS
2007 and-not THKOX
2008 and-not LVTN
2009 labels DIFF
2010
2011 layer ndiodelvt DIFF
2012 and NPLUS
2013 and DIODE
2014 and-not NWELL
2015 and-not POLY
2016 and-not PPLUS
2017 and-not THKOX
2018 and LVTN
2019 labels DIFF
2020
2021 templayer ndiodearea DIODE
2022 and NPLUS
2023 and-not THKOX
2024 and-not NWELL
2025 copyup DIODE,NPLUS
2026
2027 layer ndiffres DIFFRES
2028 and NPLUS
2029 and-not THKOX
2030 labels DIFF
2031
2032 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2033 and-not POLY
2034 and NWELL
2035 and-not NPLUS
2036 and-not DIODE
2037 and-not THKOX
2038 and PPLUS
2039 copyup pdifcheck
2040 labels DIFF
2041 labels DIFFTXT text
2042 labels DIFFPIN port
2043
2044 layer pdiff pdiffarea
2045
2046 layer mvndiode DIFF
2047 and NPLUS
2048 and DIODE
2049 and THKOX
2050 and-not POLY
2051 and-not PPLUS
2052 and-not LVTN
2053 labels DIFF
2054
2055 layer nndiode DIFF
2056 and NPLUS
2057 and DIODE
2058 and THKOX
2059 and-not POLY
2060 and-not PPLUS
2061 and LVTN
2062 labels DIFF
2063
2064 templayer mvndiodearea DIODE
2065 and NPLUS
2066 and THKOX
2067 and-not NWELL
2068 copyup DIODE,NPLUS
2069
2070 layer mvndiffres DIFFRES
2071 and NPLUS
2072 and THKOX
2073 labels DIFF
2074
2075 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2076 and-not POLY
2077 and NWELL
2078 and-not NPLUS
2079 and THKOX
2080 and-not DIODE
2081 and-not DIFFRES
2082 and PPLUS
2083 copyup mvpdifcheck
2084 labels DIFF
2085 labels DIFFTXT text
2086 labels DIFFPIN port
2087
2088 layer mvpdiff mvpdiffarea
2089
2090 # Copy pdiff areas up for contact checks
2091 templayer xpdifcheck pdifcheck
2092 copyup pdifcheck
2093
2094 layer pdiode DIFF
2095 and PPLUS
2096 and-not POLY
2097 and-not NPLUS
2098 and-not THKOX
2099 and-not LVTN
2100 and-not HVTP
2101 and DIODE
2102 labels DIFF
2103
2104 layer pdiodelvt DIFF
2105 and PPLUS
2106 and-not POLY
2107 and-not NPLUS
2108 and-not THKOX
2109 and LVTN
2110 and-not HVTP
2111 and DIODE
2112 labels DIFF
2113
2114 layer pdiodehvt DIFF
2115 and PPLUS
2116 and-not POLY
2117 and-not NPLUS
2118 and-not THKOX
2119 and-not LVTN
2120 and HVTP
2121 and DIODE
2122 labels DIFF
2123
2124 templayer pdiodearea DIODE
2125 and PPLUS
2126 and-not THKOX
2127 copyup DIODE,PPLUS
2128
2129 # Define pfet areas as known pdiff, regardless of the presence of a well.
2130
2131 templayer pfetarea DIFF
2132 and-not NPLUS
2133 and-not THKOX
2134 and POLY
2135
2136 layer pfet pfetarea
2137 and-not LVTN
2138 and-not HVTP
2139 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2140 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2141 labels DIFF
2142
2143 layer scpfet pfetarea
2144 and-not LVTN
2145 and-not HVTP
2146 and STDCELL
2147 labels DIFF
2148
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2149 layer ppu pfetarea
2150 and-not LVTN
2151 and-not HVTP
2152 and COREID
2153 labels DIFF
2154
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2155 layer pfetlvt pfetarea
2156 and LVTN
2157 labels DIFF
2158
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2159 layer pfetmvt pfetarea
2160 and HVTR
2161 labels DIFF
2162
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2163 layer pfethvt pfetarea
2164 and HVTP
2165 labels DIFF
2166
2167 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2168 layer nwell pfetarea
2169 grow 180
2170
2171 # Copy mvpdiff areas up for contact checks
2172 templayer mvxpdifcheck mvpdifcheck
2173 copyup mvpdifcheck
2174
2175 layer mvpdiode DIFF
2176 and PPLUS
2177 and-not POLY
2178 and-not NPLUS
2179 and THKOX
2180 and DIODE
2181 labels DIFF
2182
2183 templayer mvpdiodearea DIODE
2184 and PPLUS
2185 and THKOX
2186 copyup DIODE,PPLUS
2187
2188 # Define pfet areas as known pdiff,
2189 # regardless of the presence of a
2190 # well.
2191
2192 templayer mvpfetarea DIFF
2193 and-not NPLUS
2194 and THKOX
2195 and POLY
2196
2197 layer mvpfet mvpfetarea
2198 labels DIFF
2199
2200 layer pdiff DIFF,DIFFTXT,DIFFPIN
2201 and-not NPLUS
2202 and-not POLY
2203 and-not THKOX
2204 and-not DIODE
2205 and-not DIFFRES
2206 labels DIFF
2207 labels DIFFTXT text
2208 labels DIFFPIN port
2209
2210 layer pdiffres DIFFRES
2211 and PPLUS
2212 and NWELL
2213 and-not THKOX
2214 labels DIFF
2215
2216 layer nfet DIFF
2217 and POLY
2218 and-not PPLUS
2219 and NPLUS
2220 and-not THKOX
2221 and-not LVTN
2222 and-not SONOS
2223 and-not STDCELL
2224 labels DIFF
2225
2226 layer scnfet DIFF
2227 and POLY
2228 and-not PPLUS
2229 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2230 and-not NWELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2231 and-not THKOX
2232 and-not LVTN
2233 and-not SONOS
2234 and STDCELL
2235 labels DIFF
2236
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2237 layer npd DIFF
2238 and POLY
2239 and-not PPLUS
2240 and NPLUS
2241 and-not NWELL
2242 and COREID
2243 labels DIFF
2244
2245 # layer npass DIFF
2246 # and POLY
2247 # and-not PPLUS
2248 # and NPLUS
2249 # and-not NWELL
2250 # and COREID
2251 # labels DIFF
2252
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2253 layer nfetlvt DIFF
2254 and POLY
2255 and-not PPLUS
2256 and NPLUS
2257 and-not THKOX
2258 and LVTN
2259 and-not SONOS
2260 labels DIFF
2261
2262 layer nsonos DIFF
2263 and POLY
2264 and-not PPLUS
2265 and NPLUS
2266 and-not THKOX
2267 and LVTN
2268 and SONOS
2269 labels DIFF
2270
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2271 templayer nsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2272 and NPLUS
2273 and NWELL
2274 and-not POLY
2275 and-not PPLUS
2276 and-not THKOX
2277 copyup nsubcheck
2278
2279 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2280 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2281
2282 layer nsd TAP,TAPPIN
2283 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2284 and-not POLY
2285 and-not THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2286 labels TAP
2287 labels TAPPIN port
2288
2289 templayer nsdexpand nsdarea
2290 grow 500
2291
2292 # Copy nsub areas up for contact checks
2293 templayer xnsubcheck nsubcheck
2294 copyup nsubcheck
2295
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2296 templayer psdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2297 and PPLUS
2298 and-not NWELL
2299 and-not POLY
2300 and-not NPLUS
2301 and-not THKOX
2302 and-not pfetexpand
2303 copyup psubcheck
2304
2305 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2306 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2307
2308 layer psd TAP,TAPPIN
2309 and PPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2310 and-not POLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2311 and-not THKOX
2312 labels TAP
2313 labels TAPPIN port
2314
2315 templayer psdexpand psdarea
2316 grow 500
2317
2318 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
2319 and-not NPLUS
2320 and-not POLY
2321 and THKOX
2322 and mvpfetexpand
2323 labels DIFF
2324 labels DIFFTXT text
2325 labels DIFFPIN port
2326
2327 layer mvpdiffres DIFFRES
2328 and PPLUS
2329 and NWELL
2330 and THKOX
2331 and-not mvrdpioedge
2332 labels DIFF
2333
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2334 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2335 and POLY
2336 and-not PPLUS
2337 and NPLUS
2338 and-not LVTN
2339 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2340 grow 1000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2341
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2342 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2343 and POLY
2344 and-not PPLUS
2345 and NPLUS
2346 and LVTN
2347 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2348 and-not mvnfetarea
2349
2350 layer mvnfet DIFF
2351 and POLY
2352 and-not PPLUS
2353 and NPLUS
2354 and THKOX
2355 and-not mvnnfetarea
2356 labels DIFF
2357
2358 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2359 labels DIFF
2360
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2361 templayer mvnsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2362 and NPLUS
2363 and NWELL
2364 and-not POLY
2365 and-not PPLUS
2366 and THKOX
2367 copyup mvnsubcheck
2368
2369 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2370 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2371
2372 layer mvnsd TAP,TAPPIN
2373 and NPLUS
2374 and THKOX
2375 labels TAP
2376 labels TAPPIN port
2377
2378 templayer mvnsdexpand mvnsdarea
2379 grow 500
2380
2381 # Copy nsub areas up for contact checks
2382 templayer mvxnsubcheck mvnsubcheck
2383 copyup mvnsubcheck
2384
2385 templayer mvpsdarea DIFF
2386 and PPLUS
2387 and-not NWELL
2388 and-not POLY
2389 and-not NPLUS
2390 and THKOX
2391 and-not mvpfetexpand
2392 copyup mvpsubcheck
2393
2394 layer mvpsd mvpsdarea
2395 labels DIFF
2396
2397 layer mvpsd TAP,TAPPIN
2398 and PPLUS
2399 and THKOX
2400 labels TAP
2401 labels TAPPIN port
2402
2403 templayer mvpsdexpand mvpsdarea
2404 grow 500
2405
2406 # Copy psub areas up for contact checks
2407 templayer xpsubcheck psubcheck
2408 copyup psubcheck
2409
2410 templayer mvxpsubcheck mvpsubcheck
2411 copyup mvpsubcheck
2412
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2413 layer psd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2414 and-not PPLUS
2415 and-not NPLUS
2416 and-not POLY
2417 and-not THKOX
2418 and-not pfetexpand
2419 and psdexpand
2420
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2421 layer nsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2422 and-not PPLUS
2423 and-not NPLUS
2424 and-not POLY
2425 and-not THKOX
2426 and nsdexpand
2427
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2428 layer mvpsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2429 and-not PPLUS
2430 and-not NPLUS
2431 and-not POLY
2432 and THKOX
2433 and-not mvpfetexpand
2434 and mvpsdexpand
2435
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2436 layer mvnsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2437 and-not PPLUS
2438 and-not NPLUS
2439 and-not POLY
2440 and THKOX
2441 and mvnsdexpand
2442
2443 templayer hresarea POLY
2444 and RPM
2445 grow 3000
2446
2447 templayer uresarea POLY
2448 and URPM
2449 grow 3000
2450
2451 templayer diffresarea DIFFRES
2452 and-not THKOX
2453 grow 3000
2454
2455 templayer mvdiffresarea DIFFRES
2456 and THKOX
2457 grow 3000
2458
2459 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2460
2461 layer pfet POLY
2462 and DIFF
2463 and diffresarea
2464 and-not NPLUS
2465 and-not STDCELL
2466
2467 layer scpfet POLY
2468 and DIFF
2469 and diffresarea
2470 and-not NPLUS
2471 and STDCELL
2472
2473 templayer xpolyterm RPM,URPM
2474 and POLY
2475 and-not POLYRES
2476 # add back the 0.06um contact surround in the direction of the resistor
2477 grow 60
2478 and POLY
2479
2480 layer xpc xpolyterm
2481
2482 templayer polyarea POLY
2483 and-not POLYRES
2484 and-not POLYSHORT
2485 and-not DIFF
2486 and-not RPM
2487 and-not URPM
2488 copyup polycheck
2489
2490 layer poly polyarea,POLYTXT,POLYPIN
2491 labels POLY
2492 labels POLYTXT text
2493 labels POLYPIN port
2494
2495 # Copy (non-resistor) poly areas up for contact checks
2496 templayer xpolycheck polycheck
2497 copyup polycheck
2498
2499 layer mrp1 POLY
2500 and POLYRES
2501 and-not RPM
2502 and-not URPM
2503 labels POLY
2504
2505 layer rmp POLY
2506 and POLYSHORT
2507 labels POLY
2508
2509 layer xhrpoly POLY
2510 and POLYRES
2511 and RPM
2512 and-not URPM
2513 and PPLUS
2514 and NPC
2515 and-not xpolyterm
2516 labels POLY
2517
2518 layer uhrpoly POLY
2519 and POLYRES
2520 and URPM
2521 and-not RPM
2522 and NPC
2523 and-not xpolyterm
2524 labels POLY
2525
2526 templayer ndcbase CONT
2527 and DIFF
2528 and NPLUS
2529 and-not NWELL
2530 and LI
2531 and-not THKOX
2532
2533 layer ndc ndcbase
2534 grow 85
2535 shrink 85
2536 shrink 85
2537 grow 85
2538 or ndcbase
2539 labels CONT
2540
2541 templayer nscbase CONT
2542 and DIFF,TAP
2543 and NPLUS
2544 and NWELL
2545 and LI
2546 and-not THKOX
2547
2548 layer nsc nscbase
2549 grow 85
2550 shrink 85
2551 shrink 85
2552 grow 85
2553 or nscbase
2554 labels CONT
2555
2556 templayer pdcbase CONT
2557 and DIFF
2558 and PPLUS
2559 and NWELL
2560 and LI
2561 and-not THKOX
2562
2563 layer pdc pdcbase
2564 grow 85
2565 shrink 85
2566 shrink 85
2567 grow 85
2568 or pdcbase
2569 labels CONT
2570
2571 templayer pdcnowell CONT
2572 and DIFF
2573 and PPLUS
2574 and pfetexpand
2575 and LI
2576 and-not THKOX
2577
2578 layer pdc pdcnowell
2579 grow 85
2580 shrink 85
2581 shrink 85
2582 grow 85
2583 or pdcnowell
2584 labels CONT
2585
2586 templayer pscbase CONT
2587 and DIFF,TAP
2588 and PPLUS
2589 and-not NWELL
2590 and-not pfetexpand
2591 and LI
2592 and-not THKOX
2593
2594 layer psc pscbase
2595 grow 85
2596 shrink 85
2597 shrink 85
2598 grow 85
2599 or pscbase
2600 labels CONT
2601
2602 templayer pcbase CONT
2603 and POLY
2604 and-not DIFF
2605 and-not RPM,URPM
2606 and LI
2607
2608 layer pc pcbase
2609 grow 85
2610 shrink 85
2611 shrink 85
2612 grow 85
2613 or pcbase
2614 labels CONT
2615
2616 templayer ndicbase CONT
2617 and DIFF
2618 and NPLUS
2619 and DIODE
2620 and-not POLY
2621 and-not PPLUS
2622 and-not THKOX
2623 and-not LVTN
2624
2625 layer ndic ndicbase
2626 grow 85
2627 shrink 85
2628 shrink 85
2629 grow 85
2630 or ndicbase
2631 labels CONT
2632
2633 templayer ndilvtcbase CONT
2634 and DIFF
2635 and NPLUS
2636 and DIODE
2637 and-not POLY
2638 and-not PPLUS
2639 and-not THKOX
2640 and LVTN
2641
2642 layer ndilvtc ndilvtcbase
2643 grow 85
2644 shrink 85
2645 shrink 85
2646 grow 85
2647 or ndilvtcbase
2648 labels CONT
2649
2650 templayer pdicbase CONT
2651 and DIFF
2652 and PPLUS
2653 and DIODE
2654 and-not POLY
2655 and-not NPLUS
2656 and-not THKOX
2657 and-not LVTN
2658 and-not HVTP
2659
2660 layer pdic pdicbase
2661 grow 85
2662 shrink 85
2663 shrink 85
2664 grow 85
2665 or pdicbase
2666 labels CONT
2667
2668 templayer pdilvtcbase CONT
2669 and DIFF
2670 and PPLUS
2671 and DIODE
2672 and-not POLY
2673 and-not NPLUS
2674 and-not THKOX
2675 and LVTN
2676 and-not HVTP
2677
2678 layer pdilvtc pdilvtcbase
2679 grow 85
2680 shrink 85
2681 shrink 85
2682 grow 85
2683 or pdilvtcbase
2684 labels CONT
2685
2686 templayer pdihvtcbase CONT
2687 and DIFF
2688 and PPLUS
2689 and DIODE
2690 and-not POLY
2691 and-not NPLUS
2692 and-not THKOX
2693 and-not LVTN
2694 and HVTP
2695
2696 layer pdihvtc pdihvtcbase
2697 grow 85
2698 shrink 85
2699 shrink 85
2700 grow 85
2701 or pdihvtcbase
2702 labels CONT
2703
2704 templayer mvndcbase CONT
2705 and DIFF
2706 and NPLUS
2707 and-not NWELL
2708 and LI
2709 and THKOX
2710
2711 layer mvndc mvndcbase
2712 grow 85
2713 shrink 85
2714 shrink 85
2715 grow 85
2716 or mvndcbase
2717 labels CONT
2718
2719 templayer mvnscbase CONT
2720 and DIFF,TAP
2721 and NPLUS
2722 and NWELL
2723 and LI
2724 and THKOX
2725
2726 layer mvnsc mvnscbase
2727 grow 85
2728 shrink 85
2729 shrink 85
2730 grow 85
2731 or mvnscbase
2732 labels CONT
2733
2734 templayer mvpdcbase CONT
2735 and DIFF
2736 and PPLUS
2737 and NWELL
2738 and LI
2739 and THKOX
2740
2741 layer mvpdc mvpdcbase
2742 grow 85
2743 shrink 85
2744 shrink 85
2745 grow 85
2746 or mvpdcbase
2747 labels CONT
2748
2749 templayer mvpdcnowell CONT
2750 and DIFF
2751 and PPLUS
2752 and mvpfetexpand
2753 and MET1
2754 and THKOX
2755
2756 layer mvpdc mvpdcnowell
2757 grow 85
2758 shrink 85
2759 shrink 85
2760 grow 85
2761 or mvpdcnowell
2762 labels CONT
2763
2764 templayer mvpscbase CONT
2765 and DIFF,TAP
2766 and PPLUS
2767 and-not NWELL
2768 and-not mvpfetexpand
2769 and LI
2770 and THKOX
2771
2772 layer mvpsc mvpscbase
2773 grow 85
2774 shrink 85
2775 shrink 85
2776 grow 85
2777 or mvpscbase
2778 labels CONT
2779
2780 templayer mvndicbase CONT
2781 and DIFF
2782 and NPLUS
2783 and DIODE
2784 and-not POLY
2785 and-not PPLUS
2786 and-not LVTN
2787 and THKOX
2788
2789 layer mvndic mvndicbase
2790 grow 85
2791 shrink 85
2792 shrink 85
2793 grow 85
2794 or mvndicbase
2795 labels CONT
2796
2797 templayer nndicbase CONT
2798 and DIFF
2799 and NPLUS
2800 and DIODE
2801 and-not POLY
2802 and-not PPLUS
2803 and LVTN
2804 and THKOX
2805
2806 layer nndic nndicbase
2807 grow 85
2808 shrink 85
2809 shrink 85
2810 grow 85
2811 or nndicbase
2812 labels CONT
2813
2814 templayer mvpdicbase CONT
2815 and DIFF
2816 and PPLUS
2817 and DIODE
2818 and-not POLY
2819 and-not NPLUS
2820 and THKOX
2821
2822 layer mvpdic mvpdicbase
2823 grow 85
2824 shrink 85
2825 shrink 85
2826 grow 85
2827 or mvpdicbase
2828 labels CONT
2829
2830 layer locali LI,LITXT,LIPIN
2831 and-not LIRES,LISHORT
2832 and-not COREID
2833 labels LI
2834 labels LITXT text
2835 labels LIPIN port
2836
2837 layer coreli LI,LITXT,LIPIN
2838 and-not LIRES,LISHORT
2839 and COREID
2840 labels LI
2841 labels LITXT text
2842 labels LIPIN port
2843
2844 layer rli LI
2845 and LIRES,LISHORT
2846 labels LIRES,LISHORT
2847
2848 layer lic MCON
2849 grow 95
2850 shrink 95
2851 shrink 85
2852 grow 85
2853 or MCON
2854 labels MCON
2855
2856 layer m1 MET1,MET1TXT,MET1PIN
2857 and-not MET1RES,MET1SHORT
2858 labels MET1
2859 labels MET1TXT text
2860 labels MET1PIN port
2861
2862 layer rm1 MET1
2863 and MET1RES,MET1SHORT
2864 labels MET1RES,MET1SHORT
2865
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2866 layer m1fill MET1FILL
2867 labels MET1FILL
2868
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2869#ifdef MIM
2870 layer mimcap MET3
2871 and CAPM
2872 labels CAPM
2873
2874 layer mimcc VIA3
2875 and CAPM
2876 grow 60
2877 grow 40
2878 shrink 40
2879 labels CAPM
2880
2881 layer mimcap2 MET4
2882 and CAPM2
2883 labels CAPM2
2884
2885 layer mim2cc VIA4
2886 and CAPM2
2887 grow 190
2888 grow 210
2889 shrink 210
2890 labels CAPM2
2891
2892#endif (MIM)
2893
2894 templayer m2cbase VIA1
2895 grow 55
2896
2897 layer m2c m2cbase
2898 grow 30
2899 shrink 30
2900 shrink 130
2901 grow 130
2902 or m2cbase
2903
2904 layer m2 MET2,MET2TXT,MET2PIN
2905 and-not MET2RES,MET2SHORT
2906 labels MET2
2907 labels MET2TXT text
2908 labels MET2PIN port
2909
2910 layer rm2 MET2
2911 and MET2RES,MET2SHORT
2912 labels MET2RES,MET2SHORT
2913
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2914 layer m2fill MET2FILL
2915 labels MET2FILL
2916
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2917 templayer m3cbase VIA2
2918 grow 40
2919
2920 layer m3c m3cbase
2921 grow 60
2922 shrink 60
2923 shrink 140
2924 grow 140
2925 or m3cbase
2926
2927 layer m3 MET3,MET3TXT,MET3PIN
2928 and-not MET3RES,MET3SHORT
2929#ifdef MIM
2930 and-not CAPM
2931#endif (MIM)
2932 labels MET3
2933 labels MET3TXT text
2934 labels MET3PIN port
2935
2936 layer rm3 MET3
2937 and MET3RES,MET3SHORT
2938 labels MET3RES,MET3SHORT
2939
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2940 layer m3fill MET3FILL
2941 labels MET3FILL
2942
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2943#ifdef (METAL5)
2944
2945 templayer via3base VIA3
2946#ifdef MIM
2947 and-not CAPM
2948#endif (MIM)
2949 grow 60
2950
2951 layer via3 via3base
2952 grow 40
2953 shrink 40
2954 shrink 160
2955 grow 160
2956 or via3base
2957
2958 layer m4 MET4,MET4TXT,MET4PIN
2959 and-not MET4RES,MET4SHORT
2960#ifdef MIM
2961 and-not CAPM2
2962#endif (MIM)
2963 labels MET4
2964 labels MET4TXT text
2965 labels MET4PIN port
2966
2967 layer rm4 MET4
2968 and MET4RES,MET4SHORT
2969 labels MET4RES,MET4SHORT
2970
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2971 layer m4fill MET4FILL
2972 labels MET4FILL
2973
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2974 layer m5 MET5,MET5TXT,MET5PIN
2975 and-not MET5RES,MET5SHORT
2976 labels MET5
2977 labels MET5TXT text
2978 labels MET5PIN port
2979
2980 layer rm5 MET5
2981 and MET5RES,MET5SHORT
2982 labels MET5RES,MET5SHORT
2983
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2984 layer m5fill MET5FILL
2985 labels MET5FILL
2986
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2987 templayer via4base VIA4
2988#ifdef MIM
2989 and-not CAPM2
2990#endif (MIM)
2991 grow 190
2992
2993 layer via4 via4base
2994 grow 210
2995 shrink 210
2996 shrink 590
2997 grow 590
2998 or via4base
2999#endif (METAL5)
3000
3001#ifdef REDISTRIBUTION
3002 layer metrdl RDL,RDLTXT,RDLPIN
3003 labels RDL
3004 labels RDLTXT text
3005 labels RDLPIN port
3006#endif
3007
3008 # Find diffusion not covered in
3009 # NPLUS or PPLUS and pull it into
3010 # the next layer up
3011
3012 templayer gentrans DIFF
3013 and-not PPLUS
3014 and-not NPLUS
3015 and POLY
3016 copyup DIFF,POLY
3017
3018 templayer gendiff DIFF,TAP
3019 and-not PPLUS
3020 and-not NPLUS
3021 and-not POLY
3022 copyup DIFF
3023
3024 # Handle contacts found by copyup
3025
3026 templayer ndiccopy CONT
3027 and LI
3028 and DIODE
3029 and NPLUS
3030 and-not THKOX
3031
3032 layer ndic ndiccopy
3033 grow 85
3034 shrink 85
3035 shrink 85
3036 grow 85
3037 or ndiccopy
3038 labels CONT
3039
3040 templayer mvndiccopy CONT
3041 and LI
3042 and DIODE
3043 and NPLUS
3044 and THKOX
3045
3046 layer mvndic mvndiccopy
3047 grow 85
3048 shrink 85
3049 shrink 85
3050 grow 85
3051 or mvndiccopy
3052 labels CONT
3053
3054 templayer pdiccopy CONT
3055 and LI
3056 and DIODE
3057 and PPLUS
3058 and-not THKOX
3059
3060 layer pdic pdiccopy
3061 grow 85
3062 shrink 85
3063 shrink 85
3064 grow 85
3065 or pdiccopy
3066 labels CONT
3067
3068 templayer mvpdiccopy CONT
3069 and LI
3070 and DIODE
3071 and PPLUS
3072 and THKOX
3073
3074 layer mvpdic mvpdiccopy
3075 grow 85
3076 shrink 85
3077 shrink 85
3078 grow 85
3079 or mvpdiccopy
3080 labels CONT
3081
3082 templayer ndccopy CONT
3083 and ndifcheck
3084
3085 layer ndc ndccopy
3086 grow 85
3087 shrink 85
3088 shrink 85
3089 grow 85
3090 or ndccopy
3091 labels CONT
3092
3093 templayer mvndccopy CONT
3094 and mvndifcheck
3095
3096 layer mvndc mvndccopy
3097 grow 85
3098 shrink 85
3099 shrink 85
3100 grow 85
3101 or mvndccopy
3102 labels CONT
3103
3104 templayer pdccopy CONT
3105 and pdifcheck
3106
3107 layer pdc pdccopy
3108 grow 85
3109 shrink 85
3110 shrink 85
3111 grow 85
3112 or pdccopy
3113 labels CONT
3114
3115 templayer mvpdccopy CONT
3116 and mvpdifcheck
3117
3118 layer mvpdc mvpdccopy
3119 grow 85
3120 shrink 85
3121 shrink 85
3122 grow 85
3123 or mvpdccopy
3124 labels CONT
3125
3126 templayer pccopy CONT
3127 and polycheck
3128
3129 layer pc pccopy
3130 grow 85
3131 shrink 85
3132 shrink 85
3133 grow 85
3134 or pccopy
3135 labels CONT
3136
3137 templayer nsccopy CONT
3138 and nsubcheck
3139
3140 layer nsc nsccopy
3141 grow 85
3142 shrink 85
3143 shrink 85
3144 grow 85
3145 or nsccopy
3146 labels CONT
3147
3148 templayer mvnsccopy CONT
3149 and mvnsubcheck
3150
3151 layer mvnsc mvnsccopy
3152 grow 85
3153 shrink 85
3154 shrink 85
3155 grow 85
3156 or mvnsccopy
3157 labels CONT
3158
3159 templayer psccopy CONT
3160 and psubcheck
3161
3162 layer psc psccopy
3163 grow 85
3164 shrink 85
3165 shrink 85
3166 grow 85
3167 or psccopy
3168 labels CONT
3169
3170 templayer mvpsccopy CONT
3171 and mvpsubcheck
3172
3173 layer mvpsc mvpsccopy
3174 grow 85
3175 shrink 85
3176 shrink 85
3177 grow 85
3178 or mvpsccopy
3179 labels CONT
3180
3181 # Find contacts not covered in
3182 # metal and pull them into the
3183 # next layer up
3184
3185 templayer gencont CONT
3186 and LI
3187 and-not DIFF,TAP
3188 and-not POLY
3189 and-not DIODE
3190 and-not nsubcheck
3191 and-not psubcheck
3192 and-not mvnsubcheck
3193 and-not mvpsubcheck
3194 copyup CONT,LI
3195
3196 templayer barecont CONT
3197 and-not LI
3198 and-not nsubcheck
3199 and-not psubcheck
3200 and-not mvnsubcheck
3201 and-not mvpsubcheck
3202 copyup CONT
3203
3204 layer glass GLASS,PADTXT,PADPIN
3205 labels GLASS
3206 labels PADTXT text
3207 labels PADPIN port
3208
3209 templayer boundary BOUND,STDCELL,PADCELL
3210 boundary
3211
3212 layer comment LVSTEXT
3213 labels LVSTEXT text
3214
3215 layer comment TTEXT
3216 labels TTEXT text
3217
3218 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3219 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3220
3221# MOS Varactor
3222
3223 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3224 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3225 and NPLUS
3226 and NWELL
3227 and-not THKOX
3228 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3229 # NOTE: Else forms a varactor that is not in the vendor netlist.
3230 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3231 labels POLY
3232
3233 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3234 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3235 and NPLUS
3236 and NWELL
3237 and-not THKOX
3238 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3239 labels POLY
3240
3241 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3242 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3243 and NPLUS
3244 and NWELL
3245 and THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3246 labels POLY
3247
3248 calma NWELL 64 20
3249 calma DIFF 65 20
3250 calma DNWELL 64 18
3251 calma PWRES 64 13
3252 calma TAP 65 44
3253 # LVTN
3254 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3255 # HVTR
3256 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3257 # HVTP
3258 calma HVTP 78 44
3259 # SONOS (TUNM)
3260 calma SONOS 80 20
3261 # NPLUS = NSDM
3262 calma NPLUS 93 44
3263 # PPLUS = PSDM
3264 calma PPLUS 94 20
3265 # HVI
3266 calma THKOX 75 20
3267 # NPC
3268 calma NPC 95 20
3269 # P+ POLY MASK
3270 calma RPM 86 20
3271 calma URPM 79 20
3272 calma LDNTM 11 44
3273 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3274 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3275 calma POLYRES 66 13
3276 # Diffusion resistor ID mark
3277 calma DIFFRES 65 13
3278 calma POLY 66 20
3279 calma POLYMOD 66 83
3280 # Diode ID mark
3281 calma DIODE 81 23
3282 # Bipolar NPN mark
3283 calma NPNID 82 20
3284 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3285 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3286 # Capacitor ID
3287 calma CAPID 82 64
3288 # Core area ID mark
3289 calma COREID 81 2
3290 # Standard cell ID mark
3291 calma STDCELL 81 4
3292 # Padframe cell ID mark
3293 calma PADCELL 81 3
3294 # Seal ring ID mark
3295 calma SEALID 81 1
3296 # Low tap density ID mark
3297 calma LOWTAPDENSITY 81 14
3298
3299 # LICON
3300 calma CONT 66 44
3301 calma LI 67 20
3302 calma MCON 67 44
3303
3304 calma MET1 68 20
3305 calma VIA1 68 44
3306 calma MET2 69 20
3307 calma VIA2 69 44
3308 calma MET3 70 20
3309#ifdef METAL5
3310 calma VIA3 70 44
3311 calma MET4 71 20
3312 calma VIA4 71 44
3313 calma MET5 72 20
3314#endif
3315#ifdef REDISTRIBUTION
3316 calma RDL 74 20
3317#endif
3318 calma GLASS 76 20
3319
3320 calma SUBPIN 64 59
3321 calma PADPIN 76 5
3322 calma DIFFPIN 65 6
3323 calma TAPPIN 65 5
3324 calma WELLPIN 64 5
3325 calma LIPIN 67 5
3326 calma POLYPIN 66 5
3327 calma MET1PIN 68 5
3328 calma MET2PIN 69 5
3329 calma MET3PIN 70 5
3330#ifdef METAL5
3331 calma MET4PIN 71 5
3332 calma MET5PIN 72 5
3333#endif
3334#ifdef REDISTRIBUTION
3335 calma RDLPIN 74 5
3336#endif
3337
3338 calma LIRES 67 13
3339 calma MET1RES 68 13
3340 calma MET2RES 69 13
3341 calma MET3RES 70 13
3342#ifdef METAL5
3343 calma MET4RES 71 13
3344 calma MET5RES 72 13
3345#endif
3346
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3347 calma MET1FILL 68 28
3348 calma MET2FILL 69 28
3349 calma MET3FILL 70 28
3350#ifdef METAL5
3351 calma MET4FILL 71 28
3352 calma MET5FILL 72 28
3353#endif
3354
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3355 calma POLYSHORT 66 15
3356 calma LISHORT 67 15
3357 calma MET1SHORT 68 15
3358 calma MET2SHORT 69 15
3359 calma MET3SHORT 70 15
3360#ifdef METAL5
3361 calma MET4SHORT 71 15
3362 calma MET5SHORT 72 15
3363#endif
3364
3365 calma SUBTXT 122 16
3366 calma PADTXT 76 16
3367 calma DIFFTXT 65 16
3368 calma POLYTXT 66 16
3369 calma WELLTXT 64 16
3370 calma LITXT 67 16
3371 calma MET1TXT 68 16
3372 calma MET2TXT 69 16
3373 calma MET3TXT 70 16
3374#ifdef METAL5
3375 calma MET4TXT 71 16
3376 calma MET5TXT 72 16
3377#endif
3378#ifdef REDISTRIBUTION
3379 calma RDLPIN 74 16
3380#endif
3381
3382 calma BOUND 235 4
3383
3384 calma LVSTEXT 83 44
3385
3386#ifdef (MIM)
3387 calma CAPM 89 44
3388 calma CAPM2 97 44
3389#endif (MIM)
3390
3391 calma FILLOBSM1 62 24
3392 calma FILLOBSM2 105 52
3393 calma FILLOBSM3 107 24
3394 calma FILLOBSM4 112 4
3395
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3396#-----------------------------------------------------------------------
3397
3398style vendorimport
3399 scalefactor 10 nanometers
3400 gridlimit 5
3401
3402 options ignore-unknown-layer-labels no-reconnect-labels
3403
3404#ifndef MIM
3405 ignore CAPM
3406 ignore CAPM2
3407#endif (!MIM)
3408#ifndef METAL5
3409 ignore MET4,VIA3
3410 ignore MET5,VIA4
3411#endif
3412 ignore NPC
3413 ignore SEALID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3414 ignore CAPID
3415 ignore LDNTM
3416 ignore HVNTM
3417 ignore POLYMOD
3418 ignore LOWTAPDENSITY
3419
3420 layer nwell NWELL,WELLTXT,WELLPIN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3421 and-not PNPID
3422 labels NWELL
3423 labels WELLTXT port
3424 labels WELLPIN port
3425
3426 layer pnp NWELL,WELLTXT,WELLPIN
3427 and PNPID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3428 labels NWELL
3429 labels WELLTXT port
3430 labels WELLPIN port
3431
3432 layer pwell SUBTXT,SUBPIN
3433 labels SUBTXT port
3434 labels SUBPIN port
3435
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]3436 # Always draw pwell under p-tap
3437 layer pwell TAP
3438 and-not NWELL
3439
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3440 layer dnwell DNWELL
3441 labels DNWELL
3442
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3443 layer npn DNWELL
3444 and-not NWELL
3445 and NPNID
3446
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3447 layer rpw PWRES
3448 and DNWELL
3449 labels PWRES
3450
3451 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
3452 and-not POLY
3453 and-not NWELL
3454 and-not PPLUS
3455 and-not DIODE
3456 and-not DIFFRES
3457 and-not THKOX
3458 and NPLUS
3459 copyup ndifcheck
3460 labels DIFF
3461 labels DIFFTXT port
3462 labels DIFFPIN port
3463 labels TAPPIN port
3464
3465 layer ndiff ndiffarea
3466
3467 # Copy ndiff areas up for contact checks
3468 templayer xndifcheck ndifcheck
3469 copyup ndifcheck
3470
3471 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
3472 and-not POLY
3473 and-not NWELL
3474 and-not PPLUS
3475 and-not DIODE
3476 and-not DIFFRES
3477 and THKOX
3478 and NPLUS
3479 copyup ndifcheck
3480 labels DIFF
3481 labels DIFFTXT port
3482 labels DIFFPIN port
3483
3484 layer mvndiff mvndiffarea
3485
3486 # Copy ndiff areas up for contact checks
3487 templayer mvxndifcheck mvndifcheck
3488 copyup mvndifcheck
3489
3490 layer ndiode DIFF
3491 and NPLUS
3492 and DIODE
3493 and-not NWELL
3494 and-not POLY
3495 and-not PPLUS
3496 and-not THKOX
3497 and-not LVTN
3498 labels DIFF
3499
3500 layer ndiodelvt DIFF
3501 and NPLUS
3502 and DIODE
3503 and-not NWELL
3504 and-not POLY
3505 and-not PPLUS
3506 and-not THKOX
3507 and LVTN
3508 labels DIFF
3509
3510 templayer ndiodearea DIODE
3511 and NPLUS
3512 and-not THKOX
3513 and-not NWELL
3514 copyup DIODE,NPLUS
3515
3516 layer ndiffres DIFFRES
3517 and NPLUS
3518 and-not THKOX
3519 labels DIFF
3520
3521 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
3522 and-not POLY
3523 and NWELL
3524 and-not NPLUS
3525 and-not DIODE
3526 and-not THKOX
3527 and PPLUS
3528 copyup pdifcheck
3529 labels DIFF
3530 labels DIFFTXT port
3531 labels DIFFPIN port
3532
3533 layer pdiff pdiffarea
3534
3535 layer mvndiode DIFF
3536 and NPLUS
3537 and DIODE
3538 and THKOX
3539 and-not POLY
3540 and-not PPLUS
3541 and-not LVTN
3542 labels DIFF
3543
3544 layer nndiode DIFF
3545 and NPLUS
3546 and DIODE
3547 and THKOX
3548 and-not POLY
3549 and-not PPLUS
3550 and LVTN
3551 labels DIFF
3552
3553 templayer mvndiodearea DIODE
3554 and NPLUS
3555 and THKOX
3556 and-not NWELL
3557 copyup DIODE,NPLUS
3558
3559 layer mvndiffres DIFFRES
3560 and NPLUS
3561 and THKOX
3562 labels DIFF
3563
3564 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
3565 and-not POLY
3566 and NWELL
3567 and-not NPLUS
3568 and THKOX
3569 and-not DIODE
3570 and-not DIFFRES
3571 and PPLUS
3572 copyup mvpdifcheck
3573 labels DIFF
3574 labels DIFFTXT port
3575 labels DIFFPIN port
3576
3577 layer mvpdiff mvpdiffarea
3578
3579 # Copy pdiff areas up for contact checks
3580 templayer xpdifcheck pdifcheck
3581 copyup pdifcheck
3582
3583 layer pdiode DIFF
3584 and PPLUS
3585 and-not POLY
3586 and-not NPLUS
3587 and-not THKOX
3588 and-not LVTN
3589 and-not HVTP
3590 and DIODE
3591 labels DIFF
3592
3593 layer pdiodelvt DIFF
3594 and PPLUS
3595 and-not POLY
3596 and-not NPLUS
3597 and-not THKOX
3598 and LVTN
3599 and-not HVTP
3600 and DIODE
3601 labels DIFF
3602
3603 layer pdiodehvt DIFF
3604 and PPLUS
3605 and-not POLY
3606 and-not NPLUS
3607 and-not THKOX
3608 and-not LVTN
3609 and HVTP
3610 and DIODE
3611 labels DIFF
3612
3613 templayer pdiodearea DIODE
3614 and PPLUS
3615 and-not THKOX
3616 copyup DIODE,PPLUS
3617
3618 # Define pfet areas as known pdiff, regardless of the presence of a well.
3619
3620 templayer pfetarea DIFF
3621 and-not NPLUS
3622 and-not THKOX
3623 and POLY
3624
3625 layer pfet pfetarea
3626 and-not LVTN
3627 and-not HVTP
3628 and-not STDCELL
3629 and-not COREID
3630 labels DIFF
3631
3632 layer scpfet pfetarea
3633 and-not LVTN
3634 and-not HVTP
3635 and STDCELL
3636 labels DIFF
3637
3638 layer ppu pfetarea
3639 and-not LVTN
3640 and-not HVTP
3641 and COREID
3642 labels DIFF
3643
3644 layer pfetlvt pfetarea
3645 and LVTN
3646 labels DIFF
3647
3648 layer pfetmvt pfetarea
3649 and HVTR
3650 labels DIFF
3651
3652 layer pfethvt pfetarea
3653 and HVTP
3654 labels DIFF
3655
3656 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
3657 layer nwell pfetarea
3658 grow 180
3659
3660 # Copy mvpdiff areas up for contact checks
3661 templayer mvxpdifcheck mvpdifcheck
3662 copyup mvpdifcheck
3663
3664 layer mvpdiode DIFF
3665 and PPLUS
3666 and-not POLY
3667 and-not NPLUS
3668 and THKOX
3669 and DIODE
3670 labels DIFF
3671
3672 templayer mvpdiodearea DIODE
3673 and PPLUS
3674 and THKOX
3675 copyup DIODE,PPLUS
3676
3677 # Define pfet areas as known pdiff,
3678 # regardless of the presence of a
3679 # well.
3680
3681 templayer mvpfetarea DIFF
3682 and-not NPLUS
3683 and THKOX
3684 and POLY
3685
3686 layer mvpfet mvpfetarea
3687 labels DIFF
3688
3689 layer pdiff DIFF,DIFFTXT,DIFFPIN
3690 and-not NPLUS
3691 and-not POLY
3692 and-not THKOX
3693 and-not DIODE
3694 and-not DIFFRES
3695 labels DIFF
3696 labels DIFFTXT port
3697 labels DIFFPIN port
3698
3699 layer pdiffres DIFFRES
3700 and PPLUS
3701 and NWELL
3702 and-not THKOX
3703 labels DIFF
3704
3705 layer nfet DIFF
3706 and POLY
3707 and-not PPLUS
3708 and NPLUS
3709 and-not THKOX
3710 and-not LVTN
3711 and-not SONOS
3712 and-not STDCELL
3713 labels DIFF
3714
3715 layer scnfet DIFF
3716 and POLY
3717 and-not PPLUS
3718 and NPLUS
3719 and-not NWELL
3720 and-not THKOX
3721 and-not LVTN
3722 and-not SONOS
3723 and STDCELL
3724 labels DIFF
3725
3726 layer npd DIFF
3727 and POLY
3728 and-not PPLUS
3729 and NPLUS
3730 and-not NWELL
3731 and COREID
3732 labels DIFF
3733
3734 # layer npass DIFF
3735 # and POLY
3736 # and-not PPLUS
3737 # and NPLUS
3738 # and-not NWELL
3739 # and COREID
3740 # labels DIFF
3741
3742 layer nfetlvt DIFF
3743 and POLY
3744 and-not PPLUS
3745 and NPLUS
3746 and-not THKOX
3747 and LVTN
3748 and-not SONOS
3749 labels DIFF
3750
3751 layer nsonos DIFF
3752 and POLY
3753 and-not PPLUS
3754 and NPLUS
3755 and-not THKOX
3756 and LVTN
3757 and SONOS
3758 labels DIFF
3759
3760 templayer nsdarea TAP
3761 and NPLUS
3762 and NWELL
3763 and-not POLY
3764 and-not PPLUS
3765 and-not THKOX
3766 copyup nsubcheck
3767
3768 layer nsd nsdarea
3769 labels TAP
3770
3771 layer nsd TAP,TAPPIN
3772 and NPLUS
3773 and-not POLY
3774 and-not THKOX
3775 labels TAP
3776 labels TAPPIN port
3777
3778 templayer nsdexpand nsdarea
3779 grow 500
3780
3781 # Copy nsub areas up for contact checks
3782 templayer xnsubcheck nsubcheck
3783 copyup nsubcheck
3784
3785 templayer psdarea TAP
3786 and PPLUS
3787 and-not NWELL
3788 and-not POLY
3789 and-not NPLUS
3790 and-not THKOX
3791 and-not pfetexpand
3792 copyup psubcheck
3793
3794 layer psd psdarea
3795 labels TAP
3796
3797 layer psd TAP,TAPPIN
3798 and PPLUS
3799 and-not POLY
3800 and-not THKOX
3801 labels TAP
3802 labels TAPPIN port
3803
3804 templayer psdexpand psdarea
3805 grow 500
3806
3807 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
3808 and-not NPLUS
3809 and-not POLY
3810 and THKOX
3811 and mvpfetexpand
3812 labels DIFF
3813 labels DIFFTXT port
3814 labels DIFFPIN port
3815
3816 layer mvpdiffres DIFFRES
3817 and PPLUS
3818 and NWELL
3819 and THKOX
3820 and-not mvrdpioedge
3821 labels DIFF
3822
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3823 templayer mvnfetarea DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3824 and POLY
3825 and-not PPLUS
3826 and NPLUS
3827 and-not LVTN
3828 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3829 grow 1000
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3830
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3831 templayer mvnnfetarea DIFF,TAP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3832 and POLY
3833 and-not PPLUS
3834 and NPLUS
3835 and LVTN
3836 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3837 and-not mvnfetarea
3838
3839 layer mvnfet DIFF
3840 and POLY
3841 and-not PPLUS
3842 and NPLUS
3843 and THKOX
3844 and-not mvnnfetarea
3845 labels DIFF
3846
3847 layer mvnnfet mvnnfetarea
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3848 labels DIFF
3849
3850 templayer mvnsdarea TAP
3851 and NPLUS
3852 and NWELL
3853 and-not POLY
3854 and-not PPLUS
3855 and THKOX
3856 copyup mvnsubcheck
3857
3858 layer mvnsd mvnsdarea
3859 labels TAP
3860
3861 layer mvnsd TAP,TAPPIN
3862 and NPLUS
3863 and THKOX
3864 labels TAP
3865 labels TAPPIN port
3866
3867 templayer mvnsdexpand mvnsdarea
3868 grow 500
3869
3870 # Copy nsub areas up for contact checks
3871 templayer mvxnsubcheck mvnsubcheck
3872 copyup mvnsubcheck
3873
3874 templayer mvpsdarea DIFF
3875 and PPLUS
3876 and-not NWELL
3877 and-not POLY
3878 and-not NPLUS
3879 and THKOX
3880 and-not mvpfetexpand
3881 copyup mvpsubcheck
3882
3883 layer mvpsd mvpsdarea
3884 labels DIFF
3885
3886 layer mvpsd TAP,TAPPIN
3887 and PPLUS
3888 and THKOX
3889 labels TAP
3890 labels TAPPIN port
3891
3892 templayer mvpsdexpand mvpsdarea
3893 grow 500
3894
3895 # Copy psub areas up for contact checks
3896 templayer xpsubcheck psubcheck
3897 copyup psubcheck
3898
3899 templayer mvxpsubcheck mvpsubcheck
3900 copyup mvpsubcheck
3901
3902 layer psd TAP
3903 and-not PPLUS
3904 and-not NPLUS
3905 and-not POLY
3906 and-not THKOX
3907 and-not pfetexpand
3908 and psdexpand
3909
3910 layer nsd TAP
3911 and-not PPLUS
3912 and-not NPLUS
3913 and-not POLY
3914 and-not THKOX
3915 and nsdexpand
3916
3917 layer mvpsd TAP
3918 and-not PPLUS
3919 and-not NPLUS
3920 and-not POLY
3921 and THKOX
3922 and-not mvpfetexpand
3923 and mvpsdexpand
3924
3925 layer mvnsd TAP
3926 and-not PPLUS
3927 and-not NPLUS
3928 and-not POLY
3929 and THKOX
3930 and mvnsdexpand
3931
3932 templayer hresarea POLY
3933 and RPM
3934 grow 3000
3935
3936 templayer uresarea POLY
3937 and URPM
3938 grow 3000
3939
3940 templayer diffresarea DIFFRES
3941 and-not THKOX
3942 grow 3000
3943
3944 templayer mvdiffresarea DIFFRES
3945 and THKOX
3946 grow 3000
3947
3948 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
3949
3950 layer pfet POLY
3951 and DIFF
3952 and diffresarea
3953 and-not NPLUS
3954 and-not STDCELL
3955
3956 layer scpfet POLY
3957 and DIFF
3958 and diffresarea
3959 and-not NPLUS
3960 and STDCELL
3961
3962 templayer xpolyterm RPM,URPM
3963 and POLY
3964 and-not POLYRES
3965 # add back the 0.06um contact surround in the direction of the resistor
3966 grow 60
3967 and POLY
3968
3969 layer xpc xpolyterm
3970
3971 templayer polyarea POLY
3972 and-not POLYRES
3973 and-not POLYSHORT
3974 and-not DIFF
3975 and-not RPM
3976 and-not URPM
3977 copyup polycheck
3978
3979 layer poly polyarea,POLYTXT,POLYPIN
3980 labels POLY
3981 labels POLYTXT port
3982 labels POLYPIN port
3983
3984 # Copy (non-resistor) poly areas up for contact checks
3985 templayer xpolycheck polycheck
3986 copyup polycheck
3987
3988 layer mrp1 POLY
3989 and POLYRES
3990 and-not RPM
3991 and-not URPM
3992 labels POLY
3993
3994 layer rmp POLY
3995 and POLYSHORT
3996 labels POLY
3997
3998 layer xhrpoly POLY
3999 and POLYRES
4000 and RPM
4001 and-not URPM
4002 and PPLUS
4003 and NPC
4004 and-not xpolyterm
4005 labels POLY
4006
4007 layer uhrpoly POLY
4008 and POLYRES
4009 and URPM
4010 and-not RPM
4011 and NPC
4012 and-not xpolyterm
4013 labels POLY
4014
4015 templayer ndcbase CONT
4016 and DIFF
4017 and NPLUS
4018 and-not NWELL
4019 and LI
4020 and-not THKOX
4021
4022 layer ndc ndcbase
4023 grow 85
4024 shrink 85
4025 shrink 85
4026 grow 85
4027 or ndcbase
4028 labels CONT
4029
4030 templayer nscbase CONT
4031 and DIFF,TAP
4032 and NPLUS
4033 and NWELL
4034 and LI
4035 and-not THKOX
4036
4037 layer nsc nscbase
4038 grow 85
4039 shrink 85
4040 shrink 85
4041 grow 85
4042 or nscbase
4043 labels CONT
4044
4045 templayer pdcbase CONT
4046 and DIFF
4047 and PPLUS
4048 and NWELL
4049 and LI
4050 and-not THKOX
4051
4052 layer pdc pdcbase
4053 grow 85
4054 shrink 85
4055 shrink 85
4056 grow 85
4057 or pdcbase
4058 labels CONT
4059
4060 templayer pdcnowell CONT
4061 and DIFF
4062 and PPLUS
4063 and pfetexpand
4064 and LI
4065 and-not THKOX
4066
4067 layer pdc pdcnowell
4068 grow 85
4069 shrink 85
4070 shrink 85
4071 grow 85
4072 or pdcnowell
4073 labels CONT
4074
4075 templayer pscbase CONT
4076 and DIFF,TAP
4077 and PPLUS
4078 and-not NWELL
4079 and-not pfetexpand
4080 and LI
4081 and-not THKOX
4082
4083 layer psc pscbase
4084 grow 85
4085 shrink 85
4086 shrink 85
4087 grow 85
4088 or pscbase
4089 labels CONT
4090
4091 templayer pcbase CONT
4092 and POLY
4093 and-not DIFF
4094 and-not RPM,URPM
4095 and LI
4096
4097 layer pc pcbase
4098 grow 85
4099 shrink 85
4100 shrink 85
4101 grow 85
4102 or pcbase
4103 labels CONT
4104
4105 templayer ndicbase CONT
4106 and DIFF
4107 and NPLUS
4108 and DIODE
4109 and-not POLY
4110 and-not PPLUS
4111 and-not THKOX
4112 and-not LVTN
4113
4114 layer ndic ndicbase
4115 grow 85
4116 shrink 85
4117 shrink 85
4118 grow 85
4119 or ndicbase
4120 labels CONT
4121
4122 templayer ndilvtcbase CONT
4123 and DIFF
4124 and NPLUS
4125 and DIODE
4126 and-not POLY
4127 and-not PPLUS
4128 and-not THKOX
4129 and LVTN
4130
4131 layer ndilvtc ndilvtcbase
4132 grow 85
4133 shrink 85
4134 shrink 85
4135 grow 85
4136 or ndilvtcbase
4137 labels CONT
4138
4139 templayer pdicbase CONT
4140 and DIFF
4141 and PPLUS
4142 and DIODE
4143 and-not POLY
4144 and-not NPLUS
4145 and-not THKOX
4146 and-not LVTN
4147 and-not HVTP
4148
4149 layer pdic pdicbase
4150 grow 85
4151 shrink 85
4152 shrink 85
4153 grow 85
4154 or pdicbase
4155 labels CONT
4156
4157 templayer pdilvtcbase CONT
4158 and DIFF
4159 and PPLUS
4160 and DIODE
4161 and-not POLY
4162 and-not NPLUS
4163 and-not THKOX
4164 and LVTN
4165 and-not HVTP
4166
4167 layer pdilvtc pdilvtcbase
4168 grow 85
4169 shrink 85
4170 shrink 85
4171 grow 85
4172 or pdilvtcbase
4173 labels CONT
4174
4175 templayer pdihvtcbase CONT
4176 and DIFF
4177 and PPLUS
4178 and DIODE
4179 and-not POLY
4180 and-not NPLUS
4181 and-not THKOX
4182 and-not LVTN
4183 and HVTP
4184
4185 layer pdihvtc pdihvtcbase
4186 grow 85
4187 shrink 85
4188 shrink 85
4189 grow 85
4190 or pdihvtcbase
4191 labels CONT
4192
4193 templayer mvndcbase CONT
4194 and DIFF
4195 and NPLUS
4196 and-not NWELL
4197 and LI
4198 and THKOX
4199
4200 layer mvndc mvndcbase
4201 grow 85
4202 shrink 85
4203 shrink 85
4204 grow 85
4205 or mvndcbase
4206 labels CONT
4207
4208 templayer mvnscbase CONT
4209 and DIFF,TAP
4210 and NPLUS
4211 and NWELL
4212 and LI
4213 and THKOX
4214
4215 layer mvnsc mvnscbase
4216 grow 85
4217 shrink 85
4218 shrink 85
4219 grow 85
4220 or mvnscbase
4221 labels CONT
4222
4223 templayer mvpdcbase CONT
4224 and DIFF
4225 and PPLUS
4226 and NWELL
4227 and LI
4228 and THKOX
4229
4230 layer mvpdc mvpdcbase
4231 grow 85
4232 shrink 85
4233 shrink 85
4234 grow 85
4235 or mvpdcbase
4236 labels CONT
4237
4238 templayer mvpdcnowell CONT
4239 and DIFF
4240 and PPLUS
4241 and mvpfetexpand
4242 and MET1
4243 and THKOX
4244
4245 layer mvpdc mvpdcnowell
4246 grow 85
4247 shrink 85
4248 shrink 85
4249 grow 85
4250 or mvpdcnowell
4251 labels CONT
4252
4253 templayer mvpscbase CONT
4254 and DIFF,TAP
4255 and PPLUS
4256 and-not NWELL
4257 and-not mvpfetexpand
4258 and LI
4259 and THKOX
4260
4261 layer mvpsc mvpscbase
4262 grow 85
4263 shrink 85
4264 shrink 85
4265 grow 85
4266 or mvpscbase
4267 labels CONT
4268
4269 templayer mvndicbase CONT
4270 and DIFF
4271 and NPLUS
4272 and DIODE
4273 and-not POLY
4274 and-not PPLUS
4275 and-not LVTN
4276 and THKOX
4277
4278 layer mvndic mvndicbase
4279 grow 85
4280 shrink 85
4281 shrink 85
4282 grow 85
4283 or mvndicbase
4284 labels CONT
4285
4286 templayer nndicbase CONT
4287 and DIFF
4288 and NPLUS
4289 and DIODE
4290 and-not POLY
4291 and-not PPLUS
4292 and LVTN
4293 and THKOX
4294
4295 layer nndic nndicbase
4296 grow 85
4297 shrink 85
4298 shrink 85
4299 grow 85
4300 or nndicbase
4301 labels CONT
4302
4303 templayer mvpdicbase CONT
4304 and DIFF
4305 and PPLUS
4306 and DIODE
4307 and-not POLY
4308 and-not NPLUS
4309 and THKOX
4310
4311 layer mvpdic mvpdicbase
4312 grow 85
4313 shrink 85
4314 shrink 85
4315 grow 85
4316 or mvpdicbase
4317 labels CONT
4318
4319 layer locali LI,LITXT,LIPIN
4320 and-not LIRES,LISHORT
4321 and-not COREID
4322 labels LI
4323 labels LITXT port
4324 labels LIPIN port
4325
4326 layer coreli LI,LITXT,LIPIN
4327 and-not LIRES,LISHORT
4328 and COREID
4329 labels LI
4330 labels LITXT port
4331 labels LIPIN port
4332
4333 layer rli LI
4334 and LIRES,LISHORT
4335 labels LIRES,LISHORT
4336
4337 layer lic MCON
4338 grow 95
4339 shrink 95
4340 shrink 85
4341 grow 85
4342 or MCON
4343 labels MCON
4344
4345 layer m1 MET1,MET1TXT,MET1PIN
4346 and-not MET1RES,MET1SHORT
4347 labels MET1
4348 labels MET1TXT port
4349 labels MET1PIN port
4350
4351 layer rm1 MET1
4352 and MET1RES,MET1SHORT
4353 labels MET1RES,MET1SHORT
4354
4355 layer m1fill MET1FILL
4356 labels MET1FILL
4357
4358#ifdef MIM
4359 layer mimcap MET3
4360 and CAPM
4361 labels CAPM
4362
4363 layer mimcc VIA3
4364 and CAPM
4365 grow 60
4366 grow 40
4367 shrink 40
4368 labels CAPM
4369
4370 layer mimcap2 MET4
4371 and CAPM2
4372 labels CAPM2
4373
4374 layer mim2cc VIA4
4375 and CAPM2
4376 grow 190
4377 grow 210
4378 shrink 210
4379 labels CAPM2
4380
4381#endif (MIM)
4382
4383 templayer m2cbase VIA1
4384 grow 55
4385
4386 layer m2c m2cbase
4387 grow 30
4388 shrink 30
4389 shrink 130
4390 grow 130
4391 or m2cbase
4392
4393 layer m2 MET2,MET2TXT,MET2PIN
4394 and-not MET2RES,MET2SHORT
4395 labels MET2
4396 labels MET2TXT port
4397 labels MET2PIN port
4398
4399 layer rm2 MET2
4400 and MET2RES,MET2SHORT
4401 labels MET2RES,MET2SHORT
4402
4403 layer m2fill MET2FILL
4404 labels MET2FILL
4405
4406 templayer m3cbase VIA2
4407 grow 40
4408
4409 layer m3c m3cbase
4410 grow 60
4411 shrink 60
4412 shrink 140
4413 grow 140
4414 or m3cbase
4415
4416 layer m3 MET3,MET3TXT,MET3PIN
4417 and-not MET3RES,MET3SHORT
4418#ifdef MIM
4419 and-not CAPM
4420#endif (MIM)
4421 labels MET3
4422 labels MET3TXT port
4423 labels MET3PIN port
4424
4425 layer rm3 MET3
4426 and MET3RES,MET3SHORT
4427 labels MET3RES,MET3SHORT
4428
4429 layer m3fill MET3FILL
4430 labels MET3FILL
4431
4432#ifdef (METAL5)
4433
4434 templayer via3base VIA3
4435#ifdef MIM
4436 and-not CAPM
4437#endif (MIM)
4438 grow 60
4439
4440 layer via3 via3base
4441 grow 40
4442 shrink 40
4443 shrink 160
4444 grow 160
4445 or via3base
4446
4447 layer m4 MET4,MET4TXT,MET4PIN
4448 and-not MET4RES,MET4SHORT
4449#ifdef MIM
4450 and-not CAPM2
4451#endif (MIM)
4452 labels MET4
4453 labels MET4TXT port
4454 labels MET4PIN port
4455
4456 layer rm4 MET4
4457 and MET4RES,MET4SHORT
4458 labels MET4RES,MET4SHORT
4459
4460 layer m4fill MET4FILL
4461 labels MET4FILL
4462
4463 layer m5 MET5,MET5TXT,MET5PIN
4464 and-not MET5RES,MET5SHORT
4465 labels MET5
4466 labels MET5TXT port
4467 labels MET5PIN port
4468
4469 layer rm5 MET5
4470 and MET5RES,MET5SHORT
4471 labels MET5RES,MET5SHORT
4472
4473 layer m5fill MET5FILL
4474 labels MET5FILL
4475
4476 templayer via4base VIA4
4477#ifdef MIM
4478 and-not CAPM2
4479#endif (MIM)
4480 grow 190
4481
4482 layer via4 via4base
4483 grow 210
4484 shrink 210
4485 shrink 590
4486 grow 590
4487 or via4base
4488#endif (METAL5)
4489
4490#ifdef REDISTRIBUTION
4491 layer metrdl RDL,RDLTXT,RDLPIN
4492 labels RDL
4493 labels RDLTXT port
4494 labels RDLPIN port
4495#endif
4496
4497 # Find diffusion not covered in
4498 # NPLUS or PPLUS and pull it into
4499 # the next layer up
4500
4501 templayer gentrans DIFF
4502 and-not PPLUS
4503 and-not NPLUS
4504 and POLY
4505 copyup DIFF,POLY
4506
4507 templayer gendiff DIFF,TAP
4508 and-not PPLUS
4509 and-not NPLUS
4510 and-not POLY
4511 copyup DIFF
4512
4513 # Handle contacts found by copyup
4514
4515 templayer ndiccopy CONT
4516 and LI
4517 and DIODE
4518 and NPLUS
4519 and-not THKOX
4520
4521 layer ndic ndiccopy
4522 grow 85
4523 shrink 85
4524 shrink 85
4525 grow 85
4526 or ndiccopy
4527 labels CONT
4528
4529 templayer mvndiccopy CONT
4530 and LI
4531 and DIODE
4532 and NPLUS
4533 and THKOX
4534
4535 layer mvndic mvndiccopy
4536 grow 85
4537 shrink 85
4538 shrink 85
4539 grow 85
4540 or mvndiccopy
4541 labels CONT
4542
4543 templayer pdiccopy CONT
4544 and LI
4545 and DIODE
4546 and PPLUS
4547 and-not THKOX
4548
4549 layer pdic pdiccopy
4550 grow 85
4551 shrink 85
4552 shrink 85
4553 grow 85
4554 or pdiccopy
4555 labels CONT
4556
4557 templayer mvpdiccopy CONT
4558 and LI
4559 and DIODE
4560 and PPLUS
4561 and THKOX
4562
4563 layer mvpdic mvpdiccopy
4564 grow 85
4565 shrink 85
4566 shrink 85
4567 grow 85
4568 or mvpdiccopy
4569 labels CONT
4570
4571 templayer ndccopy CONT
4572 and ndifcheck
4573
4574 layer ndc ndccopy
4575 grow 85
4576 shrink 85
4577 shrink 85
4578 grow 85
4579 or ndccopy
4580 labels CONT
4581
4582 templayer mvndccopy CONT
4583 and mvndifcheck
4584
4585 layer mvndc mvndccopy
4586 grow 85
4587 shrink 85
4588 shrink 85
4589 grow 85
4590 or mvndccopy
4591 labels CONT
4592
4593 templayer pdccopy CONT
4594 and pdifcheck
4595
4596 layer pdc pdccopy
4597 grow 85
4598 shrink 85
4599 shrink 85
4600 grow 85
4601 or pdccopy
4602 labels CONT
4603
4604 templayer mvpdccopy CONT
4605 and mvpdifcheck
4606
4607 layer mvpdc mvpdccopy
4608 grow 85
4609 shrink 85
4610 shrink 85
4611 grow 85
4612 or mvpdccopy
4613 labels CONT
4614
4615 templayer pccopy CONT
4616 and polycheck
4617
4618 layer pc pccopy
4619 grow 85
4620 shrink 85
4621 shrink 85
4622 grow 85
4623 or pccopy
4624 labels CONT
4625
4626 templayer nsccopy CONT
4627 and nsubcheck
4628
4629 layer nsc nsccopy
4630 grow 85
4631 shrink 85
4632 shrink 85
4633 grow 85
4634 or nsccopy
4635 labels CONT
4636
4637 templayer mvnsccopy CONT
4638 and mvnsubcheck
4639
4640 layer mvnsc mvnsccopy
4641 grow 85
4642 shrink 85
4643 shrink 85
4644 grow 85
4645 or mvnsccopy
4646 labels CONT
4647
4648 templayer psccopy CONT
4649 and psubcheck
4650
4651 layer psc psccopy
4652 grow 85
4653 shrink 85
4654 shrink 85
4655 grow 85
4656 or psccopy
4657 labels CONT
4658
4659 templayer mvpsccopy CONT
4660 and mvpsubcheck
4661
4662 layer mvpsc mvpsccopy
4663 grow 85
4664 shrink 85
4665 shrink 85
4666 grow 85
4667 or mvpsccopy
4668 labels CONT
4669
4670 # Find contacts not covered in
4671 # metal and pull them into the
4672 # next layer up
4673
4674 templayer gencont CONT
4675 and LI
4676 and-not DIFF,TAP
4677 and-not POLY
4678 and-not DIODE
4679 and-not nsubcheck
4680 and-not psubcheck
4681 and-not mvnsubcheck
4682 and-not mvpsubcheck
4683 copyup CONT,LI
4684
4685 templayer barecont CONT
4686 and-not LI
4687 and-not nsubcheck
4688 and-not psubcheck
4689 and-not mvnsubcheck
4690 and-not mvpsubcheck
4691 copyup CONT
4692
4693 layer glass GLASS,PADTXT,PADPIN
4694 labels GLASS
4695 labels PADTXT port
4696 labels PADPIN port
4697
4698 templayer boundary BOUND,STDCELL,PADCELL
4699 boundary
4700
4701 layer comment LVSTEXT
4702 labels LVSTEXT text
4703
4704 layer comment TTEXT
4705 labels TTEXT text
4706
4707 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4708 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4709
4710# MOS Varactor
4711
4712 layer var POLY
4713 and TAP
4714 and NPLUS
4715 and NWELL
4716 and-not THKOX
4717 and-not HVTP
4718 # NOTE: Else forms a varactor that is not in the vendor netlist.
4719 and-not COREID
4720 labels POLY
4721
4722 layer varhvt POLY
4723 and TAP
4724 and NPLUS
4725 and NWELL
4726 and-not THKOX
4727 and HVTP
4728 labels POLY
4729
4730 layer mvvar POLY
4731 and TAP
4732 and NPLUS
4733 and NWELL
4734 and THKOX
4735 labels POLY
4736
4737 calma NWELL 64 20
4738 calma DIFF 65 20
4739 calma DNWELL 64 18
4740 calma PWRES 64 13
4741 calma TAP 65 44
4742 # LVTN
4743 calma LVTN 125 44
4744 # HVTR
4745 calma HVTR 18 20
4746 # HVTP
4747 calma HVTP 78 44
4748 # SONOS (TUNM)
4749 calma SONOS 80 20
4750 # NPLUS = NSDM
4751 calma NPLUS 93 44
4752 # PPLUS = PSDM
4753 calma PPLUS 94 20
4754 # HVI
4755 calma THKOX 75 20
4756 # NPC
4757 calma NPC 95 20
4758 # P+ POLY MASK
4759 calma RPM 86 20
4760 calma URPM 79 20
4761 calma LDNTM 11 44
4762 calma HVNTM 125 20
Tim Edwards3360b9e2020-09-16 11:45:19 -0400[diff] [blame]4763 # Poly resistor ID mark
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4764 calma POLYRES 66 13
4765 # Diffusion resistor ID mark
4766 calma DIFFRES 65 13
4767 calma POLY 66 20
4768 calma POLYMOD 66 83
4769 # Diode ID mark
4770 calma DIODE 81 23
4771 # Bipolar NPN mark
4772 calma NPNID 82 20
4773 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]4774 calma PNPID 82 44
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4775 # Capacitor ID
4776 calma CAPID 82 64
4777 # Core area ID mark
4778 calma COREID 81 2
4779 # Standard cell ID mark
4780 calma STDCELL 81 4
4781 # Padframe cell ID mark
4782 calma PADCELL 81 3
4783 # Seal ring ID mark
4784 calma SEALID 81 1
4785 # Low tap density ID mark
4786 calma LOWTAPDENSITY 81 14
4787
4788 # LICON
4789 calma CONT 66 44
4790 calma LI 67 20
4791 calma MCON 67 44
4792
4793 calma MET1 68 20
4794 calma VIA1 68 44
4795 calma MET2 69 20
4796 calma VIA2 69 44
4797 calma MET3 70 20
4798#ifdef METAL5
4799 calma VIA3 70 44
4800 calma MET4 71 20
4801 calma VIA4 71 44
4802 calma MET5 72 20
4803#endif
4804#ifdef REDISTRIBUTION
4805 calma RDL 74 20
4806#endif
4807 calma GLASS 76 20
4808
4809 calma SUBPIN 64 59
4810 calma PADPIN 76 5
4811 calma DIFFPIN 65 6
4812 calma TAPPIN 65 5
4813 calma WELLPIN 64 5
4814 calma LIPIN 67 5
4815 calma POLYPIN 66 5
4816 calma MET1PIN 68 5
4817 calma MET2PIN 69 5
4818 calma MET3PIN 70 5
4819#ifdef METAL5
4820 calma MET4PIN 71 5
4821 calma MET5PIN 72 5
4822#endif
4823#ifdef REDISTRIBUTION
4824 calma RDLPIN 74 5
4825#endif
4826
4827 calma LIRES 67 13
4828 calma MET1RES 68 13
4829 calma MET2RES 69 13
4830 calma MET3RES 70 13
4831#ifdef METAL5
4832 calma MET4RES 71 13
4833 calma MET5RES 72 13
4834#endif
4835
4836 calma MET1FILL 68 28
4837 calma MET2FILL 69 28
4838 calma MET3FILL 70 28
4839#ifdef METAL5
4840 calma MET4FILL 71 28
4841 calma MET5FILL 72 28
4842#endif
4843
4844 calma POLYSHORT 66 15
4845 calma LISHORT 67 15
4846 calma MET1SHORT 68 15
4847 calma MET2SHORT 69 15
4848 calma MET3SHORT 70 15
4849#ifdef METAL5
4850 calma MET4SHORT 71 15
4851 calma MET5SHORT 72 15
4852#endif
4853
4854 calma SUBTXT 122 16
4855 calma PADTXT 76 16
4856 calma DIFFTXT 65 16
4857 calma POLYTXT 66 16
4858 calma WELLTXT 64 16
4859 calma LITXT 67 16
4860 calma MET1TXT 68 16
4861 calma MET2TXT 69 16
4862 calma MET3TXT 70 16
4863#ifdef METAL5
4864 calma MET4TXT 71 16
4865 calma MET5TXT 72 16
4866#endif
4867#ifdef REDISTRIBUTION
4868 calma RDLPIN 74 16
4869#endif
4870
4871 calma BOUND 235 4
4872
4873 calma LVSTEXT 83 44
4874
4875#ifdef (MIM)
4876 calma CAPM 89 44
4877 calma CAPM2 97 44
4878#endif (MIM)
4879
4880 calma FILLOBSM1 62 24
4881 calma FILLOBSM2 105 52
4882 calma FILLOBSM3 107 24
4883 calma FILLOBSM4 112 4
4884
4885end
4886
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4887#-----------------------------------------------------
4888# Digital flow maze router cost parameters
4889#-----------------------------------------------------
4890
4891mzrouter
4892end
4893
4894#-----------------------------------------------------
4895# Vendor DRC rules
4896#-----------------------------------------------------
4897
4898drc
4899
4900 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4901 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4902 cifstyle drc
4903
4904 variants (fast),(full)
4905
4906#-----------------------------
4907# DNWELL
4908#-----------------------------
4909
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4910 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4911 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4912 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4913 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4914 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4915 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4916 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4917 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4918
4919#-----------------------------
4920# NWELL
4921#-----------------------------
4922
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4923 width allnwell 840 "N-well width < %d (nwell.1)"
4924 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4925
4926#-----------------------------
4927# DIFF
4928#-----------------------------
4929
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4930 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,ppu,*psd,*pdiode,pdiffres \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4931 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4932 width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4933 "MV Diffusion width < %d (diff/tap.14)"
4934 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4935 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4936 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4937 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4938 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4939 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4940 spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4941 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4942 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4943 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4944 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4945 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4946 spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4947 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4948 spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4949 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4950 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4951 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4952 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4953 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4954 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4955 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4956 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4957 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4958 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4959 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4960 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4961 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4962 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4963 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4964 surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4965 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4966 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4967 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4968 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4969 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4970
4971 # Butting junction rules
4972 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
4973 "N-Diffusion to P-tap spacing < %d across butted junction"
4974 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
4975 "N-Diffusion to P-tap spacing < %d across butted junction"
4976 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
4977 "P-Diffusion to N-tap spacing < %d across butted junction"
4978 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
4979 "P-Diffusion to N-tap spacing < %d across butted junction"
4980
4981 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
4982 "MV N-Diffusion to MV P-tap spacing < %d across butted junction"
4983 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
4984 "MV N-Diffusion to MV P-tap spacing < %d across butted junction"
4985 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
4986 "MV P-Diffusion to MV N-tap spacing < %d across butted junction"
4987 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
4988 "MV P-Diffusion to MV N-tap spacing < %d across butted junction"
4989
4990 variants (full)
4991
4992 # Latchup rules
4993 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4994 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4995 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4996 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4997 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4998 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4999
5000 variants *
5001
5002#-----------------------------
5003# POLY
5004#-----------------------------
5005
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5006 width allpoly 150 "poly.width < %d (poly.1a)"
5007 spacing allpoly allpoly 210 touching_ok "poly.spacing < %d (poly.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5008 spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5009 "poly.spacing to Diffusion < %d (poly.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5010 spacing npres *nsd 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5011 "poly.resistor spacing to N-tap < %d (poly.9)"
5012 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nmos < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5013 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5014 "N-Diffusion overhang of nmos < %d (poly.7)"
5015 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
5016 overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (poly.7)"
5017 overhang *poly allfets 130 "poly.overhang of transistor < %d (poly.8)"
5018 rect_only allfets "No bends in transistors (poly.11)"
5019 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5020 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5021 "poly.contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5022 spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5023 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5024
5025#--------------------------------------------------------------------
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5026# NPC (Nitride poly.Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5027#--------------------------------------------------------------------
5028
5029# Layer NPC is defined automatically around poly contacts (grow 0.1um)
5030
5031#--------------------------------------------------------------------
5032# CONT (LICON, contact between poly/diff and LI)
5033#--------------------------------------------------------------------
5034
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5035 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
5036 width nsc/li 170 "N-tap contact width < %d (licon.1)"
5037 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
5038 width psc/li 170 "P-tap contact width < %d (licon.1)"
5039 width ndic/li 170 "N-diode contact width < %d (licon.1)"
5040 width pdic/li 170 "P-diode contact width < %d (licon.1)"
5041 width pc/li 170 "poly.contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5042
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5043 width xpc/li 350 "poly.resistor contact width < %d (licon.1b + 2 * li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5044
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5045 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
5046 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
5047 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
5048 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
5049 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
5050 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5051
5052 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5053 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5054 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5055 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5056 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5057 "Diffusion contact spacing < %d (licon.2)"
5058 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5059
5060 spacing pc alldiff 190 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5061 "poly.contact spacing to diffusion < %d (licon.14)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5062 spacing pc allpfets 235 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5063 "poly.contact spacing to pFET < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5064
5065 spacing ndc,pdc nfet,pfet 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5066 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5067 spacing ndc,pdc scnfet,npd,npass,scpfet,ppu 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5068 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5069 spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5070 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5071 spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()"
5072 spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()"
5073 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5074 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5075 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5076 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5077
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5078 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5079 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5080 surround pdc/a *pdiff,pfet,scpfet,ppu,pfethvt,pfetmvt,pfetlvt 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5081 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5082 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5083 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5084 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5085 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5086
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5087 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5088 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5089 surround pdc/a *pdiff,pfet,scpfet,ppu,pfethvt,pfetmvt,pfetlvt 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5090 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5091 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5092 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5093 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5094 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5095
5096 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5097 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5098 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5099 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5100
5101 surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5102 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5103 surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5104 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5105 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5106 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5107 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5108 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5109
5110 surround mvndc/a *mvndiff,mvnfet 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5111 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5112 surround mvpdc/a *mvpdiff,mvpfet 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5113 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5114 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5115 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5116 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5117 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5118
5119 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5120 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5121 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5122 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5123
5124 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5125 "poly.overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5126 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5127 "poly.overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5128
5129 exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a
5130 exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a
5131
5132#-------------------------------------------------------------
5133# LI - Local interconnect layer
5134#-------------------------------------------------------------
5135
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5136 width *li,rli 170 "Local interconnect width < %d (li.1)"
5137 width coreli 140 "Core local interconnect width < %d (li.c1)"
5138 spacing allli allli,*obsli 170 touching_ok "Local interconnect spacing < %d (li.3)"
5139 spacing coreli allli,*obsli 140 touching_ok "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5140
5141 surround pc/li *li 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5142 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5143
5144 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
5145 *li,rli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5146 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5147
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5148 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5149
5150#-------------------------------------------------------------
5151# MCON - Contact between local interconnect and metal1
5152#-------------------------------------------------------------
5153
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5154 width lic/m1 170 "mcon.width < %d (mcon.1)"
5155 spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5156
5157 exact_overlap lic/m1
5158
5159#-------------------------------------------------------------
5160# METAL1 -
5161#-------------------------------------------------------------
5162
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5163 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
5164 spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (met1.2)"
5165 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5166
5167 surround lic/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5168 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5169 surround lic/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5170 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5171
5172variants (fast),(full)
5173 widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5174 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5175 widespacing *obsm1 3000 allm1 280 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5176 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5177
5178variants (full)
5179 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5180 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5181variants *
5182
5183#--------------------------------------------------
5184# VIA1
5185#--------------------------------------------------
5186
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5187 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
5188 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5189 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5190 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5191 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5192 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5193
5194 exact_overlap v1/m2
5195
5196#--------------------------------------------------
5197# METAL2 -
5198#--------------------------------------------------
5199
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5200 width allm2 140 "Metal2 width < %d (met2.1)"
5201 spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (met2.2)"
5202 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5203
5204variants (fast),(full)
5205 widespacing allm2 3000 allm2,obsm2 280 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5206 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5207 widespacing obsm2 3000 allm2 280 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5208 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5209
5210variants (full)
5211 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5212 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5213variants *
5214
5215#--------------------------------------------------
5216# VIA2
5217#--------------------------------------------------
5218
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5219 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5220
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5221 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5222
5223 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5224 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
5225 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5226
5227 exact_overlap v2/m2
5228
5229#--------------------------------------------------
5230# METAL3 -
5231#--------------------------------------------------
5232
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5233 width allm3 300 "Metal3 width < %d (met3.1)"
5234 spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (met3.2)"
5235 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5236
5237variants (fast),(full)
5238 widespacing allm3 3000 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5239 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5240 widespacing obsm3 3000 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5241 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5242variants *
5243
5244
5245#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5246#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5247#--------------------------------------------------
5248# VIA3 - Requires METAL5 Module
5249#--------------------------------------------------
5250
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5251 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
5252 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5253 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5254 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5255 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5256 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5257
5258 exact_overlap v3/m3
5259
5260#-----------------------------
5261# METAL4 - METAL4 Module
5262#-----------------------------
5263
5264variants *
5265
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5266 width allm4 300 "Metal4 width < %d (met4.1)"
5267 spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (met4.2)"
5268 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5269
5270variants (fast),(full)
5271 widespacing allm4 3000 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5272 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5273 widespacing obsm4 3000 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5274 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5275variants *
5276
5277#--------------------------------------------------
5278# VIA4 - Requires METAL5 Module
5279#--------------------------------------------------
5280
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5281 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
5282 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5283 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5284 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5285
5286 exact_overlap v4/m4
5287
5288#-----------------------------
5289# METAL5 - METAL5 Module
5290#-----------------------------
5291
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5292 width allm5 1600 "Metal5 width < %d (met5.1)"
5293 spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (met5.2)"
5294 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5295
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5296#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5297#endif (METAL5)
5298
5299#ifdef REDISTRIBUTION
5300
5301variants (full)
5302
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5303 width metrdl 10000 "RDL width < %d (rdl.1)"
5304 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
5305 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
5306 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5307
5308variants *
5309
5310#endif (REDISTRIBUTION)
5311
5312#--------------------------------------------------
5313# NMOS, PMOS
5314#--------------------------------------------------
5315
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5316 extend allfets *poly 420 "Transistor width < %d (diff/tap.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5317 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5318 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5319
5320 spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5321 "N-tap spacing to field poly < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5322 spacing *psd,*mvpsd allpolynonfet 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5323 "P-tap spacing to field poly < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5324
5325 # Full edge rule required to describe FET to butted tap distance
5326 edge4way *psd *ndiff 300 *ndiff *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5327 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5328 edge4way *nsd *pdiff 300 *pdiff *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5329 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5330 edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5331 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5332 edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5333 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5334
5335 # No LV FETs in HV diff
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5336 spacing pfet,scpfet,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5337 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5338
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5339 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5340 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5341
5342 # No HV FETs in LV diff
5343 spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5344 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5345
5346 spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5347 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5348
5349 # Minimum length of MV FETs. Note that this is larger than the minimum
5350 # width (0.29um), so an edge rule is required
5351
5352 edge4way mvndiff mvnfet 500 mvnfet 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5353 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5354
5355 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5356 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5357
5358 edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5359 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5360
5361#--------------------------------------------------
5362# mrp1 (N+ poly resistor)
5363#--------------------------------------------------
5364
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5365 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5366
5367#--------------------------------------------------
5368# xhrpoly (P+ poly resistor)
5369#--------------------------------------------------
5370
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5371 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5372 # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27.
5373
5374#--------------------------------------------------
5375# uhrpoly (P+ poly resistor, 2kOhm/sq)
5376#--------------------------------------------------
5377
5378 width uhrpoly 350 "uhrpoly resistor width < %d"
5379 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5380 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5381
5382#------------------------------------
5383# MOS Varactor device rules
5384#------------------------------------
5385
5386 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5387 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5388
5389 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5390 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5391
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5392 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
5393 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5394
5395#ifdef MIM
5396#-----------------------------------------------------------
5397# MiM CAP (CAPM) -
5398#-----------------------------------------------------------
5399
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5400 width *mimcap 2000 "MiM cap width < %d (capm.1)"
5401 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5402 spacing *mimcap via2/m3 1270 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5403 "MiM cap spacing to via2 < %d (capm.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5404 surround *mimcc *mimcap 200 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5405 "MiM cap must surround MiM cap contact by %d (capm.4)"
5406 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5407
5408 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5409 "Metal3 must surround MiM cap by %d (capm.3)"
5410 spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (capm.8)"
5411 spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (capm.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5412 # (resolve scaling issue!)
5413 # cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5414 # "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5415
5416 # MiM cap contact rules (VIA3)
5417
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5418 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5419 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5420 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5421 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5422 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5423
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5424 width *mimcap2 2000 "MiM cap width < %d (cap2m.1)"
5425 spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (cap2m.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5426 spacing *mimcap2 via3/m4 1270 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5427 "MiM cap spacing to via3 < %d (cap2m.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5428 surround *mim2cc *mimcap2 200 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5429 "MiM cap must surround MiM cap contact by %d (cap2m.4)"
5430 rect_only *mimcap2 "MiM cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5431
5432 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5433 "Metal4 must surround MiM cap by %d (cap2m.3)"
5434 spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (cap2m.8)"
5435 spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (cap2m.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5436 # (resolve scaling issue!)
5437 # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5438 # "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5439
5440 # MiM cap contact rules (VIA4)
5441
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5442 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5443 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5444 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5445 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5446 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5447 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5448
5449#endif (MIM)
5450
5451#----------------------------
5452# End DRC style
5453#----------------------------
5454
5455end
5456
5457#----------------------------
5458# LEF format definitions
5459#----------------------------
5460
5461lef
5462
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]5463 masterslice pwell pwell PWELL substrate
5464 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]5465
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5466 routing li li1 LI1 LI li
5467
5468 routing m1 met1 MET1 m1
5469 routing m2 met2 MET2 m2
5470 routing m3 met3 MET3 m3
5471#ifdef METAL5
5472 routing m4 met4 MET4 m4
5473 routing m5 met5 MET5 m5
5474#endif (METAL5)
5475#ifdef REDISTRIBUTION
5476 routing mrdl met6 MET6 m6 MRDL METRDL
5477#endif
5478
5479 cut lic mcon MCON Mcon
5480 cut m2c via via1 VIA VIA1 cont2 via12
5481 cut m3c via2 VIA2 cont3 via23
5482#ifdef METAL5
5483 cut via3 via3 VIA3 cont4 via34
5484 cut via4 via4 VIA4 cont5 via45
5485#endif (METAL5)
5486
5487 obs obsli li1
5488 obs obsm1 met1
5489 obs obsm2 met2
5490 obs obsm3 met3
5491
5492#ifdef METAL5
5493 obs obsm4 met4
5494 obs obsm5 met5
5495#endif (METAL5)
5496#ifdef REDISTRIBUTION
5497 obs obsmrdl met6
5498#endif
5499
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]5500 # NOTE: obslic only used with li1, not obsli.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5501 obs obslic mcon
5502
5503end
5504
5505#-----------------------------------------------------
5506# Device and Parasitic extraction
5507#-----------------------------------------------------
5508
5509
5510extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5511 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5512 cscale 1
5513 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
5514 # dimensions must be in units of microns in the extract file.
5515 # Use extract style "ngspice(si)" to override this and produce
5516 # a file with SI units for length/area.
5517
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5518 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5519 lambda 1E6
5520 variants (si)
5521 lambda 1.0
5522 variants *
5523
5524 units microns
5525 step 7
5526 sidehalo 2
5527
5528 # NOTE: MiM cap layers have been purposely put out of order,
5529 # may want to reconsider.
5530
5531 planeorder dwell 0
5532 planeorder well 1
5533 planeorder active 2
5534 planeorder locali 3
5535 planeorder metal1 4
5536 planeorder metal2 5
5537 planeorder metal3 6
5538#ifdef METAL5
5539 planeorder metal4 7
5540 planeorder metal5 8
5541#ifdef REDISTRIBUTION
5542 planeorder metali 9
5543 planeorder block 10
5544 planeorder comment 11
5545 planeorder cap1 12
5546 planeorder cap2 13
5547#else (!REDISTRIBUTION)
5548 planeorder block 9
5549 planeorder comment 10
5550 planeorder cap1 11
5551 planeorder cap2 12
5552#endif (!REDISTRIBUTION)
5553#else (!METAL5)
5554#ifdef REDISTRIBUTION
5555 planeorder metali 7
5556 planeorder block 8
5557 planeorder comment 9
5558 planeorder cap1 10
5559 planeorder cap2 11
5560#else (!REDISTRIBUTION)
5561 planeorder block 7
5562 planeorder comment 8
5563 planeorder cap1 9
5564 planeorder cap2 10
5565#endif (!REDISTRIBUTION)
5566#endif (!METAL5)
5567
5568 height dnwell -0.1 0.1
5569 height nwell,pwell 0.0 0.2062
5570 height alldiff 0.2062 0.12
5571 height allpoly 0.3262 0.18
5572 height alldiffcont 0.3262 0.61
5573 height pc 0.5062 0.43
5574 height allli 0.9361 0.10
5575 height lic 1.0361 0.34
5576 height allm1 1.3761 0.36
5577 height v1 1.7361 0.27
5578 height allm2 2.0061 0.36
5579 height v2 2.3661 0.42
5580 height allm3 2.7861 0.845
5581#ifdef METAL5
5582 height v3 3.6311 0.39
5583 height allm4 4.0211 0.845
5584 height v4 4.8661 0.505
5585 height allm5 5.3711 1.26
5586 height mimcap 2.4661 0.2
5587 height mimcap2 3.7311 0.2
5588 height mimcc 2.6661 0.12
5589 height mim2cc 3.9311 0.09
5590#ifdef REDISTRIBUTION
5591 height mrdlc 6.6311 5.2523
5592 height mrdl 11.8834 4.0
5593#endif (!REDISTRIBUTION)
5594#endif (!METAL5)
5595
5596 # Antenna check parameters
5597 # Note that checks w/diode diffusion are not modeled
5598 model partial
5599 antenna poly sidewall 50 none
5600 antenna allcont surface 3 none
5601 antenna li sidewall 75 0 450
5602 antenna lic surface 3 0 18
5603 antenna m1,m2,m3 sidewall 400 2600 400
5604 antenna v1 surface 3 0 18
5605 antenna v2 surface 6 0 36
5606#ifdef METAL5
5607 antenna m4,m5 sidewall 400 2600 400
5608 antenna v3,v4 surface 6 0 36
5609#endif (METAL5)
5610
5611 tiedown alldiffnonfet
5612
5613 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
5614
5615# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
5616
5617# Resistances are in milliohms per square
5618# Optional 3rd argument is the corner adjustment fraction
5619# Device values come from trtc.cor (typical corner)
5620 resist (dnwell)/dwell 2200000
5621 resist (pwell)/well 3050000
5622 resist (nwell)/well 1700000
5623 resist (rpw)/well 3050000 0.5
5624 resist (*ndiff,nsd)/active 120000
5625 resist (*pdiff,*psd)/active 197000
5626 resist (*mvndiff,mvnsd)/active 114000
5627 resist (*mvpdiff,*mvpsd)/active 191000
5628
5629 resist ndiffres/active 120000 0.5
5630 resist pdiffres/active 197000 0.5
5631 resist mvndiffres/active 114000 0.5
5632 resist mvpdiffres/active 191000 0.5
5633 resist mrp1/active 48200 0.5
5634 resist xhrpoly/active 319800 0.5
5635 resist uhrpoly/active 2000000 0.5
5636
5637 resist (allpolynonres)/active 48200
5638 resist rmp/active 48200
5639
5640 resist (allli)/locali 12200
5641 resist (allm1)/metal1 125
5642 resist (allm2)/metal2 125
5643 resist (allm3)/metal3 47
5644#ifdef METAL5
5645 resist (allm4)/metal4 47
5646 resist (allm5)/metal5 29
5647#endif (METAL5)
5648#ifdef REDISTRIBUTION
5649 resist mrdl/metali 5
5650#endif (REDISTRIBUTION)
5651
5652 contact ndc,nsc 15000
5653 contact pdc,psc 15000
5654 contact mvndc,mvnsc 15000
5655 contact mvpdc,mvpsc 15000
5656 contact pc 15000
5657 contact lic 152000
5658 contact m2c 4500
5659 contact m3c 3410
5660#ifdef METAL5
5661#ifdef MIM
5662 contact mimcc 4500
5663 contact mim2cc 3410
5664#endif (MIM)
5665 contact via3 3410
5666 contact via4 380
5667#endif (METAL5)
5668#ifdef REDISTRIBUTION
5669 contact mrdlc 6
5670#endif (REDISTRIBUTION)
5671
5672#-------------------------------------------------------------------------
5673# Parasitic capacitance values: Use document (...)
5674#-------------------------------------------------------------------------
5675# This uses the new "default" definitions that determine the intervening
5676# planes from the planeorder stack, take care of the reflexive sideoverlap
5677# definitions, and generally clean up the section and make it more readable.
5678#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5679# Also uses "units microns" statement. All values are taken from the
5680# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5681# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5682#-------------------------------------------------------------------------
5683# Remember that device capacitances to substrate are taken care of by the
5684# models. Thus, active and poly definitions ignore all "fet" types.
5685# fet types are excluded when computing parasitic capacitance to
5686# active from layers above them because poly is a shield; fet types are
5687# included for parasitics from layers above to poly. Resistor types
5688# should be removed from all parasitic capacitance calculations, or else
5689# they just create floating caps. Technically, the capacitance probably
5690# should be split between the two terminals. Unsure of the correct model.
5691#-------------------------------------------------------------------------
5692
5693#n-well
5694# NOTE: This value not found in PEX files
5695defaultareacap nwell well 120
5696
5697#n-active
5698# Rely on device models to capture *ndiff area cap
5699# Do not extract parasitics from resistors
5700# defaultareacap allnactivenonfet active 790
5701# defaultperimeter allnactivenonfet active 280
5702
5703#p-active
5704# Rely on device models to capture *pdiff area cap
5705# Do not extract parasitics from resistors
5706# defaultareacap allpactivenonfet active 810
5707# defaultperimeter allpactivenonfet active 300
5708
5709#poly
5710# Do not extract parasitics from resistors
5711# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5712# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5713# defaultperimeter allpolynonfet active 57
5714
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5715 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5716 defaultareacap *poly active nwell,obswell,pwell well 106
5717 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5718
5719#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5720 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5721 defaultareacap allli locali nwell,obswell,pwell well 37
5722 defaultperimeter allli locali nwell,obswell,pwell well 55
5723 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5724
5725#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5726 defaultoverlap allli locali allactivenonfet active 37
5727 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5728
5729#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5730 defaultoverlap allli locali allpolynonres active 94
5731 defaultsideoverlap allli locali allpolynonres active 52
5732 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5733
5734#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5735 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5736 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5737 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5738 defaultoverlap allm1 metal1 nwell well 26
5739
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5740#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5741 defaultoverlap allm1 metal1 allactivenonfet active 26
5742 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5743
5744#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5745 defaultoverlap allm1 metal1 allpolynonres active 45
5746 defaultsideoverlap allm1 metal1 allpolynonres active 47
5747 defaultsideoverlap *poly active allm1 metal1 17
5748
5749#metal1->locali
5750 defaultoverlap allm1 metal1 allli locali 114
5751 defaultsideoverlap allm1 metal1 allli locali 59
5752 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5753
5754#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5755 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5756 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
5757 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
5758 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5759
5760#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5761 defaultoverlap allm2 metal2 allactivenonfet active 17
5762 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5763
5764#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5765 defaultoverlap allm2 metal2 allpolynonres active 24
5766 defaultsideoverlap allm2 metal2 allpolynonres active 41
5767 defaultsideoverlap *poly active allm2 metal2 11
5768
5769#metal2->locali
5770 defaultoverlap allm2 metal2 allli locali 38
5771 defaultsideoverlap allm2 metal2 allli locali 46
5772 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5773
5774#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5775 defaultoverlap allm2 metal2 allm1 metal1 134
5776 defaultsideoverlap allm2 metal2 allm1 metal1 67
5777 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5778
5779#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5780 defaultsidewall allm3 metal3 63
5781 defaultoverlap allm3 metal3 nwell well 12
5782 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5783 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5784
5785#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5786 defaultoverlap allm3 metal3 allactive active 12
5787 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5788
5789#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5790 defaultoverlap allm3 metal3 allpolynonres active 16
5791 defaultsideoverlap allm3 metal3 allpolynonres active 44
5792 defaultsideoverlap *poly active allm3 metal3 9
5793
5794#metal3->locali
5795 defaultoverlap allm3 metal3 allli locali 21
5796 defaultsideoverlap allm3 metal3 allli locali 47
5797 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5798
5799#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5800 defaultoverlap allm3 metal3 allm1 metal1 35
5801 defaultsideoverlap allm3 metal3 allm1 metal1 55
5802 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5803
5804#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5805 defaultoverlap allm3 metal3 allm2 metal2 86
5806 defaultsideoverlap allm3 metal3 allm2 metal2 70
5807 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5808
5809#ifdef METAL5
5810#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5811 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5812# defaultareacap alltopm metal4 well 6
5813 areacap allm4/m4 8
5814 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5815 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5816
5817#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5818 defaultoverlap allm4 metal4 allactivenonfet active 8
5819 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5820
5821#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5822 defaultoverlap allm4 metal4 allpolynonres active 10
5823 defaultsideoverlap allm4 metal4 allpolynonres active 38
5824 defaultsideoverlap *poly active allm4 metal4 6
5825
5826#metal4->locali
5827 defaultoverlap allm4 metal4 allli locali 12
5828 defaultsideoverlap allm4 metal4 allli locali 40
5829 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5830
5831#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5832 defaultoverlap allm4 metal4 allm1 metal1 15
5833 defaultsideoverlap allm4 metal4 allm1 metal1 43
5834 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5835
5836#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5837 defaultoverlap allm4 metal4 allm2 metal2 20
5838 defaultsideoverlap allm4 metal4 allm2 metal2 46
5839 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5840
5841#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5842 defaultoverlap allm4 metal4 allm3 metal3 84
5843 defaultsideoverlap allm4 metal4 allm3 metal3 71
5844 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5845
5846#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5847 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5848# defaultareacap allm5 metal5 well 6
5849 areacap allm5/m5 6
5850 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5851 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5852
5853#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5854 defaultoverlap allm5 metal5 allactivenonfet active 6
5855 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5856
5857#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5858 defaultoverlap allm5 metal5 allpolynonres active 7
5859 defaultsideoverlap allm5 metal5 allpolynonres active 40
5860 defaultsideoverlap *poly active allm5 metal5 6
5861
5862#metal5->locali
5863 defaultoverlap allm5 metal5 allli locali 8
5864 defaultsideoverlap allm5 metal5 allli locali 41
5865 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5866
5867#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5868 defaultoverlap allm5 metal5 allm1 metal1 9
5869 defaultsideoverlap allm5 metal5 allm1 metal1 43
5870 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5871
5872#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5873 defaultoverlap allm5 metal5 allm2 metal2 11
5874 defaultsideoverlap allm5 metal5 allm2 metal2 46
5875 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5876
5877#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5878 defaultoverlap allm5 metal5 allm3 metal3 20
5879 defaultsideoverlap allm5 metal5 allm3 metal3 54
5880 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5881
5882#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5883 defaultoverlap allm5 metal5 allm4 metal4 68
5884 defaultsideoverlap allm5 metal5 allm4 metal4 83
5885 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5886#endif (METAL5)
5887
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5888#ifdef REDISTRIBUTION
5889#endif (REDISTRIBUTION)
5890
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5891# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5892
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5893variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5894
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5895 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
5896 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5897 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5898 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5899 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
5900 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5901 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
5902 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5903 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt \
5904 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5905
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5906 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5907 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5908 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5909 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5910 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
5911 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
5912
5913 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5914 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
5915 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5916 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
5917 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
5918 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5919 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5920 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5921 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5922 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5923 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5924 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5925 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5926 *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5927
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5928 # Extended drain devices (must appear before the regular devices)
5929 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5930 dnwell pwell,space/w error l=l w=w
5931 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5932 dnwell pwell,space/w error l=l w=w
5933 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5934 pwell,space/w nwell error l=l w=w
5935
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5936 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
5937 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
5938 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
5939 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
5940 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
5941 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5942
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]5943 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
5944 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5945
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5946 device resistor sky130_fd_pr__res_generic_l1 rli1 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5947 *li,coreli space/w,pwell,nwell error l=l w=w
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5948 device resistor sky130_fd_pr__res_generic_m1 rmetal1 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5949 *metal1 space/w,pwell,nwell error l=l w=w
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5950 device resistor sky130_fd_pr__res_generic_m2 rmetal2 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5951 *metal2 space/w,pwell,nwell error l=l w=w
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5952 device resistor sky130_fd_pr__res_generic_m3 rmetal3 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5953 *metal3 space/w,pwell,nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5954#ifdef METAL5
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5955 device resistor sky130_fd_pr__res_generic_m4 rm4 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5956 *m4 space/w,pwell,nwell error l=l w=w
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5957 device resistor sky130_fd_pr__res_generic_m5 rm5 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5958 *m5 space/w,pwell,nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5959#endif (METAL5)
5960
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5961 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5962 xpc pwell,space/w error +res0p35 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5963 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5964 xpc pwell,space/w error +res0p69 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5965 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5966 xpc pwell,space/w error +res1p41 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5967 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5968 xpc pwell,space/w error +res2p85 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5969 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5970 xpc pwell,space/w error +res5p73 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5971 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5972 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5973 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5974 xpc pwell,space/w error +res0p35 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5975 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5976 xpc pwell,space/w error +res0p69 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5977 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5978 xpc pwell,space/w error +res1p41 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5979 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5980 xpc pwell,space/w error +res2p85 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5981 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5982 xpc pwell,space/w error +res5p73 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5983 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5984 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5985
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5986 device rsubcircuit sky130_fd_pr_res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5987 *ndiff pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5988 device rsubcircuit sky130_fd_pr_res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5989 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5990 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5991 pwell dnwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5992
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]5993 device resistor sky130_fd_pr__res_generic_po mrp1 \
5994 *poly pwell,space/w error
5995 device resistor sky130_fd_pr__res_generic_nd__hv mvndiffres \
5996 *mvndiff pwell,space/w error
5997 device resistor sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5998 *mvpdiff nwell error
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5999
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6000 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6001 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6002 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6003 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6004 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6005 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6006 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6007 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6008
6009 # These are parasitic devices
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6010 device msubcircuit sky130_fd_pr__diode_pw2nd_lvt *ndiodelvt \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6011 pwell,space/w a=area
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6012 device subcircuit sky130_fd_pr__diode_pd2nw_lvt *pdiodelvt \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6013 nwell a=area
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6014 device subcircuit sky130_fd_pr_diode_pd2nw_hvt *pdiodehvt \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6015 nwell a=area
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6016 device msubcircuit sky130_fd_pr__diode_pw2nd_nvt *nndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6017 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6018
6019#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]6020 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
6021 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6022#endif (MIM)
6023
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6024 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6025
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6026 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
6027 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
6028 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
6029 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
6030 device mosfet sky130_fd_pr__pfet_01v8_hvt pfethvt pdiff,pdiffres,pdc nwell
6031 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
6032 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
6033 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6034 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6035 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
6036 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
6037 pwell,space/w
6038
6039 # Extended drain devices (must appear before the regular devices)
6040 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
6041 dnwell pwell,space/w error
6042 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
6043 dnwell pwell,space/w error
6044 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
6045 pwell,space/w nwell error
6046
6047 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
6048 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
6049 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6050
6051 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6052 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
6053 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
6054 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6055
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6056 device resistor sky130_fd_pr__res_generic_po rmp *poly
6057 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
6058 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
6059 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
6060 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6061#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6062 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
6063 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6064#endif (METAL5)
6065
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6066 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
6067 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
6068 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
6069 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
6070 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
6071 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
6072 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
6073 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
6074 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
6075 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
6076 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
6077 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
6078 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
6079 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
6080 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6081 device resistor mrdn_hv mvndiffres *mvndiff
6082 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6083 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6084
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6085 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
6086 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
6087 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
6088 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6089
6090 # These are parasitic devices
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6091 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
6092 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
6093 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
6094 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6095
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]6096 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
6097 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6098
6099#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6100 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
6101 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6102#endif (MIM)
6103
6104end
6105
6106#-----------------------------------------------------
6107# Wiring tool definitions
6108#-----------------------------------------------------
6109
6110wiring
6111 # All wiring values are in nanometers
6112 scalefactor 10
6113
6114 contact lic 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6115 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6116 contact v2 280 m2 0 45 m3 25 0
6117#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]6118 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6119 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6120#endif (METAL5)
6121
6122 contact pc 170 poly 50 80 li 0 80
6123 contact pdc 170 pdiff 40 60 li 0 80
6124 contact ndc 170 ndiff 40 60 li 0 80
6125 contact psc 170 psd 40 60 li 0 80
6126 contact nsc 170 nsd 40 60 li 0 80
6127
6128end
6129
6130#-----------------------------------------------------
6131# Plain old router. . .
6132#-----------------------------------------------------
6133
6134router
6135end
6136
6137#------------------------------------------------------------
6138# Plowing (restored in magic 8.2, need to fill this section)
6139#------------------------------------------------------------
6140
6141plowing
6142end
6143
6144#-----------------------------------------------------------------
6145# No special plot layers defined (use default PNM color choices)
6146#-----------------------------------------------------------------
6147
6148plot
6149 style pnm
6150 default
6151 draw fillblock no_color_at_all
6152 draw nwell cwell
6153end
6154