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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / b184e85de7629b8c87087a46b79eb45e7f7cd383 / . / sky130 / magic / sky130.tech
blob: e027773c820750978eac6771db8ba4d0d121af02 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18# This file is designed to be used with magic versions
19# 8.3.24 or newer.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]20#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]21tech
22 format 35
23 TECHNAME
24end
25
26version
27 version REVISION
28 description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
29end
30
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]31#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]32# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]33# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]34# Status 8/14/20: Rev 2 (alpha):
35# Started updating with new device/model naming convention
36#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]37
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]38#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]39# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]40#------------------------------------------------------------------------
41# device name magic ID layer description
42#------------------------------------------------------------------------
43# sky130_fd_pr__nfet_01v8 nfet standard nFET
44# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]45# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
46# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]47# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]48# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]49# sky130_fd_pr__pfet_01v8 pfet standard pFET
50# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]51# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]52# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
53# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
54# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
55# sky130_fd_pr__nfet_03v3_nvt --- native nFET
56# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
57# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
58# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]60# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
61# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]62# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
63# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]64# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
65# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]66# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]67# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]68# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]69# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]70# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
71# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
72# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]73# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]75# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]76# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
77# sky130_fd_pr__res_generic_po npres n+ poly resistor
78# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
79# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
80# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
81# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
82# sky130_fd_pr__cap_var mvvaractor thickox varactor
83# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]84#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]85# (*) Note that ppres may extract into some generic type called
86# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
87# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]88#
89# (**) nFET and pFET in standard cells are the same as devices
90# outside of the standard cell except for the DRC rule for
91# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
92#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]93#-------------------------------------------------------------
94# The following devices are not extracted but are represented
95# only by script-generated subcells in the PDK.
96#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]97# sky130_fd_pr__esd_nfet_01v8 ESD nFET
98# sky130_fd_pr__esd_nfet_g5v0d10v5 ESD thickox nFET
99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
100# sky130_fd_pr__esd_pfet_g5v0d10v5 ESD thickox pFET
101# sky130_fd_pr__special_nfet_pass_flash flash nFET device
102# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
103# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
104# sky130_fd_pr__cap_vpp_* Vpp cap
105# sky130_fd_pr__ind_* inductor
106# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]107#--------------------------------------------------------------
108
109#-----------------------------------------------------
110# Tile planes
111#-----------------------------------------------------
112
113planes
114 dwell,dw
115 well,w
116 active,a
117 locali,li1,li
118 metal1,m1
119 metal2,m2
120 metal3,m3
121#ifdef METAL5
122#ifdef MIM
123 cap1,c1
124#endif (MIM)
125 metal4,m4
126#ifdef MIM
127 cap2,c2
128#endif (MIM)
129 metal5,m5
130#endif (METAL5)
131#ifdef REDISTRIBUTION
132 metali,mi
133#endif
134 block,b
135 comment,c
136end
137
138#-----------------------------------------------------
139# Tile types
140#-----------------------------------------------------
141
142types
143# Deep nwell
144 dwell dnwell,dnw
145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]152 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]153
154# Transistors
155 active nmos,ntransistor,nfet
156 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]157 -active npd,npdfet,sramnfet
158 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]159 active pmos,ptransistor,pfet
160 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]161 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]163 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet,nnfet
167 active varactor,varact,var
168 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]169
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]170 active pmoslvt,pfetlvt
171 active pmosmvt,pfetmvt
172 active pmoshvt,pfethvt
173 active nmoslvt,nfetlvt
174 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]175 -active nsonos,sonos
176
177# Diffusions
178 active ndiff,ndiffusion,ndif
179 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]180 active mvndiff,mvndiffusion,mvndif
181 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182 active ndiffc,ndcontact,ndc
183 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]184 active mvndiffc,mvndcontact,mvndc
185 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]186 active psubdiff,psubstratepdiff,ppdiff,ppd,psd
187 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]188 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
189 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]190 active psubdiffcont,psubstratepcontact,psc
191 active nsubdiffcont,nsubstratencontact,nsc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]192 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
193 active mvnsubdiffcont,mvnsubstratencontact,mvnsc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]194 -active obsactive
195 -active mvobsactive
196
197# Poly
198 active poly,p,polysilicon
199 active polycont,pc,pcontact,polycut,polyc
200 active xpolycontact,xpolyc,xpc
201
202# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]203 active npolyres,npres,mrp1
204 active ppolyres,ppres,xhrpoly
205 active xpolyres,xpres,xres,uhrpoly
206 active ndiffres,rnd,rdn,rndiff
207 active pdiffres,rpd,rdp,rpdiff
208 active mvndiffres,mvrnd,mvrdn,mvrndiff
209 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
210 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]211
212# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]213 active pdiode,pdi
214 active ndiode,ndi
215 active nndiode,nndi
216 active pdiodec,pdic
217 active ndiodec,ndic
218 active nndiodec,nndic
219 active mvpdiode,mvpdi
220 active mvndiode,mvndi
221 active mvpdiodec,mvpdic
222 active mvndiodec,mvndic
223 active pdiodelvt,pdilvt
224 active pdiodehvt,pdihvt
225 active ndiodelvt,ndilvt
226 active pdiodelvtc,pdilvtc
227 active pdiodehvtc,pdihvtc
228 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]229
230# Local Interconnect
231 locali locali,li1,li
232 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]233 locali rlocali,rli1,rli
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]234 locali viali,vial,mcon,lic,licon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]235 -locali obsli1,obsli
236 -locali obsli1c,obslic,obslicon
237
238# Metal 1
239 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]240 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 metal1 via1,m2contact,m2cut,m2c,via,v,v1
242 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]243 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]244 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]245
246# Metal 2
247 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]248 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]249 metal2 via2,m3contact,m3cut,m3c,v2
250 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 3
254 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 -metal3 obsm3
257#ifdef METAL5
258 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]259 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]260
261#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 cap1 mimcap,mim,capm
263 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]264#endif
265
266# Metal 4
267 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]269 -metal4 obsm4
270 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]271 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]272
273#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]274 cap2 mimcap2,mim2,capm2
275 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276#endif
277
278# Metal 5
279 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]280 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]281 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]282 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif (METAL5)
284
285#ifdef REDISTRIBUTION
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]286 metal5 mrdlcontact,mrdlc
287 metali metalrdl,mrdl,metrdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metali obsmrdl
289#endif (REDISTRIBUTION)
290
291# Miscellaneous
292 -block glass
293 -block fillblock
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]294 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]296# fixed resistor width identifiers
297 -comment res0p35
298 -comment res0p69
299 -comment res1p41
300 -comment res2p85
301 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]302
303end
304
305#-----------------------------------------------------
306# Magic contact types
307#-----------------------------------------------------
308
309contact
310 pc poly locali
311 ndc ndiff locali
312 pdc pdiff locali
313 nsc nsd locali
314 psc psd locali
315 ndic ndiode locali
316 ndilvtc ndiodelvt locali
317 nndic nndiode locali
318 pdic pdiode locali
319 pdilvtc pdiodelvt locali
320 pdihvtc pdiodehvt locali
321 xpc xpc locali
322
323 mvndc mvndiff locali
324 mvpdc mvpdiff locali
325 mvnsc mvnsd locali
326 mvpsc mvpsd locali
327 mvndic mvndiode locali
328 mvpdic mvpdiode locali
329
330 lic locali metal1
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]331 obslic obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]332
333 via1 metal1 metal2
334 via2 metal2 metal3
335#ifdef METAL5
336 via3 metal3 metal4
337 via4 metal4 metal5
338#endif (METAL5)
339 stackable
340
341#ifdef METAL5
342#ifdef MIM
343 # MiM cap contacts are not stackable!
344 mimcc mimcap metal4
345 mim2cc mimcap2 metal5
346#endif (MIM)
347
348 padl m1 m2 m3 m4 m5 glass
349#else
350 padl m1 m2 m3 glass
351#endif (!METAL5)
352
353#ifdef REDISTRIBUTION
354 mrdlc metal5 mrdl
355#endif (REDISTRIBUTION)
356end
357
358#-----------------------------------------------------
359# Layer aliases
360#-----------------------------------------------------
361
362aliases
363
364 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]365 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]366
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]367 allnfets nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]368 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetlvt,pfetmvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]369 allfets allnfets,allpfets,varactor,mvvaractor,varhvt
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]370 allfetsstd nfet,mvnfet,mvnnfet,nfetlvt,pfet,mvpfet,pfethvt,pfetlvt,pfetmvt
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]371 allfetsspecial npass,npd,scnfet,nsonos,ppu,scpfet,scpfethvt
372 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetmvt,varactor,mvvaractor,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]373
374 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
375 allnactive allnactivenonfet,allnfets
376 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
377 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar
378
379 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
380 allpactive allpactivenonfet,allpfets
381 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
382 allpactivetap *psd,*mvpsd
383
384 allactivenonfet allnactivenonfet,allpactivenonfet
385 allactive allactivenonfet,allfets
386
387 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
388
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]389 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]390 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]391 alldifflv allndifflv,allpdifflv
392 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
393 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
394 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
395
396 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
397 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
398 alldiffmv allndiffmv,allpdiffmv
399 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
400 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
401 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
402 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
403 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
404 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
405
406 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
407 alldiff alldifflv,alldiffmv
408
409 allpolyres mrp1,xhrpoly,uhrpoly,rmp
410 allpolynonfet *poly,allpolyres,xpc
411 allpolynonres *poly,allfets,xpc
412
413 allpoly allpolynonfet,allfets
414 allpolynoncap *poly,xpc,allfets,allpolyres
415
416 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
417 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
418 allndiffcontmv mvndc,mvnsc,mvndic
419 allpdiffcontmv mvpdc,mvpsc,mvpdic
420 allndiffcont allndiffcontlv,allndiffcontmv
421 allpdiffcont allpdiffcontlv,allpdiffcontmv
422 alldiffcontlv allndiffcontlv,allpdiffcontlv
423 alldiffcontmv allndiffcontmv,allpdiffcontmv
424 alldiffcont alldiffcontlv,alldiffcontmv
425
426 allcont alldiffcont,pc
427
428 allres allpolyres,allactiveres
429
430 allli *locali,coreli,rli
431 allm1 *m1,rm1
432 allm2 *m2,rm2
433 allm3 *m3,rm3
434#ifdef METAL5
435 allm4 *m4,rm4
436 allm5 *m5,rm5
437#endif (METAL5)
438
439 allpad padl
440
441 psub pwell
442
443end
444
445#-----------------------------------------------------
446# Layer drawing styles
447#-----------------------------------------------------
448
449styles
450 styletype mos
451 dnwell cwell
452 nwell nwell
453 pwell pwell
454 rpwell pwell ptransistor_stripes
455 ndiff ndiffusion
456 pdiff pdiffusion
457 nsd ndiff_in_nwell
458 psd pdiff_in_pwell
459 nfet ntransistor ntransistor_stripes
460 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]461 npass ntransistor ntransistor_stripes
462 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]463 pfet ptransistor ptransistor_stripes
464 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]465 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]466 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]467 var polysilicon ndiff_in_nwell
468 ndc ndiffusion metal1 contact_X'es
469 pdc pdiffusion metal1 contact_X'es
470 nsc ndiff_in_nwell metal1 contact_X'es
471 psc pdiff_in_pwell metal1 contact_X'es
472
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]473 pnp nwell ntransistor_stripes
474 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]475
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]476 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]477 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]478 pfethvt ptransistor ptransistor_stripes implant2
479 nfetlvt ntransistor ntransistor_stripes implant1
480 nsonos ntransistor implant3
481 varhvt polysilicon ndiff_in_nwell implant2
482
483 mvndiff ndiffusion hvndiff_mask
484 mvpdiff pdiffusion hvpdiff_mask
485 mvnsd ndiff_in_nwell hvndiff_mask
486 mvpsd pdiff_in_pwell hvpdiff_mask
487 mvnfet ntransistor ntransistor_stripes hvndiff_mask
488 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
489 mvpfet ptransistor ptransistor_stripes
490 mvvar polysilicon ndiff_in_nwell hvndiff_mask
491 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
492 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
493 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
494 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
495
496 poly polysilicon
497 pc polysilicon metal1 contact_X'es
498 npolyres polysilicon silicide_block nselect2
499 ppolyres polysilicon silicide_block pselect2
500 xpc polysilicon pselect2 metal1 contact_X'es
501 rmp polysilicon poly_resist_stripes
502
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]503 res0p35 implant1
504 res0p69 implant1
505 res1p41 implant1
506 res2p85 implant1
507 res5p73 implant1
508
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]509 pdiode pdiffusion pselect2
510 ndiode ndiffusion nselect2
511 pdiodec pdiffusion pselect2 metal1 contact_X'es
512 ndiodec ndiffusion nselect2 metal1 contact_X'es
513
514 nndiode ndiffusion nselect2 implant3
515 ndiodelvt ndiffusion nselect2 implant1
516 pdiodelvt pdiffusion pselect2 implant1
517 pdiodehvt pdiffusion pselect2 implant2
518 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
519 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
520 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
521
522 mvpdiode pdiffusion pselect2 hvpdiff_mask
523 mvndiode ndiffusion nselect2 hvndiff_mask
524 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
525 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
526 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
527
528 locali metal1
529 coreli metal1
530 rli metal1 poly_resist_stripes
531 lic metal1 metal2 via1arrow
532 obsli metal1
533 obslic metal1 metal2 via1arrow
534
535 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]536 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]537 rm1 metal2 poly_resist_stripes
538 obsm1 metal2
539 m2c metal2 metal3 via2arrow
540 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]541 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]542 rm2 metal3 poly_resist_stripes
543 obsm2 metal3
544 m3c metal3 metal4 via3alt
545 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]546 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]547 rm3 metal4 poly_resist_stripes
548 obsm3 metal4
549#ifdef METAL5
550#ifdef MIM
551 mimcap metal3 mems
552 mimcc metal3 contact_X'es mems
553 mimcap2 metal4 mems
554 mim2cc metal4 contact_X'es mems
555#endif (MIM)
556 via3 metal4 metal5 via4
557 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]558 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]559 rm4 metal5 poly_resist_stripes
560 obsm4 metal5
561 via4 metal5 metal6 via5
562 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]563 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]564 rm5 metal6 poly_resist_stripes
565 obsm5 metal6
566#endif (METAL5)
567#ifdef REDISTRIBUTION
568 mrdlc metal6 metal7 via6
569 metalrdl metal7
570 obsmrdl metal7
571#endif (REDISTRIBUTION)
572
573 glass overglass
574 mrp1 poly_resist poly_resist_stripes
575 xhrpoly poly_resist silicide_block
576 uhrpoly poly_resist
577 ndiffres ndiffusion ndop_stripes
578 pdiffres pdiffusion pdop_stripes
579 mvndiffres ndiffusion hvndiff_mask ndop_stripes
580 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
581 comment comment
582 error_p error_waffle
583 error_s error_waffle
584 error_ps error_waffle
585 fillblock cwell
586
587 obswell cwell
588 obsactive implant4
589
590#ifndef METAL5
591 padl metal4 via4 overglass
592#else
593 padl metal6 via6 overglass
594#endif
595
596 magnet substrate_field_implant
597 rotate via3alt
598 fence via5
599end
600
601#-----------------------------------------------------
602# Special paint/erase rules
603#-----------------------------------------------------
604
605compose
606 compose nfet poly ndiff
607 compose pfet poly pdiff
608 compose var poly nsd
609
610 compose mvnfet poly mvndiff
611 compose mvpfet poly mvpdiff
612 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]613
614 paint obslic locali via1
Tim Edwardsd44d18d2020-09-22 15:29:11 -0400[diff] [blame]615 paint obslic obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]616
617 paint ndc nwell pdc
618 paint nfet nwell pfet
619 paint scnfet nwell scpfet
620 paint ndiff nwell pdiff
621 paint psd nwell nsd
622 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]623 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]624
625 paint pdc pwell ndc
626 paint pfet pwell nfet
627 paint scpfet pwell scnfet
628 paint pdiff pwell ndiff
629 paint nsd pwell psd
630 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]631 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]632
633 paint pdc coreli pdc
634 paint ndc coreli ndc
635 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]636 paint nsc coreli nsc
637 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]638 paint viali coreli viali
639
640 paint coreli pdc pdc
641 paint coreli ndc ndc
642 paint coreli pc pc
643 paint coreli nsc nsc
644 paint coreli psc psc
645 paint coreli viali viali
646
647#ifdef METAL5
648 paint m4 obsm4 m4
649 paint m5 obsm5 m5
650#endif (METAL5)
651end
652
653#-----------------------------------------------------
654# Electrical connectivity
655#-----------------------------------------------------
656
657connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]658 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
659 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]660 *li,coreli *li,coreli
Tim Edwards48db3e12020-09-22 15:41:41 -0400[diff] [blame]661 *m1,m1fill,obslic *m1,m1fill,obslic
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]662 *m2,m2fill *m2,m2fill
663 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]664#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]665 *m4,m4fill *m4,m4fill
666 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]667#ifdef MIM
668 *mimcap *mimcap
669 *mimcap2 *mimcap2
670#endif (MIM)
671#endif (METAL5)
672 allnactivenonfet allnactivenonfet
673 allpactivenonfet allpactivenonfet
674 *poly,xpc,allfets *poly,xpc,allfets
675#ifdef REDISTRIBUTION
676 # RDL connects to m5 (i.e., padl) through glass cut
677 *mrdl *mrdl
678 glass metrdl
679#endif (REDISTRIBUTION)
680end
681
682#-----------------------------------------------------
683# CIF/GDS output layer definitions
684#-----------------------------------------------------
685# NOTE: All values in this section MUST be multiples of 25
686# or else magic will scale below the allowed layout grid size
687
688cifoutput
689
690#----------------------------------------------------------------
691style gdsii
692# NOTE: This section is used for actual GDS output
693#----------------------------------------------------------------
694 scalefactor 10 nanometers
695 options calma-permissive-labels
696 gridlimit 5
697
698#----------------------------------------------------------------
699# Create a temp layer from the cell bounding box for use in
700# generating ID layers. Note that "boundary", unlike "bbox",
701# requires the FIXED_BBOX property (abutment box) in the cell.
702#----------------------------------------------------------------
703 templayer CELLBOUND
704 boundary
705
706#----------------------------------------------------------------
707# BOUND
708#----------------------------------------------------------------
709 layer BOUND CELLBOUND
710 calma 235 4
711
712# Create a boundary outside of an abutment box, so that layers
713# can be made to stretch to the abutment box edges. First strink
714# so that any box that would be so small as to interact with
715# itself will be removed.
716
717 templayer CELLRING CELLBOUND
718 shrink 345
719 grow 545
720 and-not CELLBOUND
721
722#----------------------------------------------------------------
723# DNWELL
724#----------------------------------------------------------------
725
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]726 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]727 calma 64 18
728
729 layer PWRES rpw
730 and dnwell
731 calma 64 13
732
733#----------------------------------------------------------------
734# NWELL
735#----------------------------------------------------------------
736
737 layer NWELL allnwell
738 bloat-all rpw dnwell
739 and-not rpw,pwell
740 calma 64 20
741
742 layer WELLTXT
743 labels allnwell noport
744 calma 64 16
745
746 layer WELLPIN
747 labels allnwell port
748 calma 64 5
749
750#----------------------------------------------------------------
751# SUB (text/port only)
752#----------------------------------------------------------------
753
754 layer SUBTXT
755 labels pwell noport
756 calma 122 16
757
758 layer SUBPIN
759 labels pwell port
760 calma 64 59
761
762#----------------------------------------------------------------
763# DIFF
764#----------------------------------------------------------------
765
766 layer DIFF allnactivenontap,allpactivenontap,allactiveres
767 labels allnactivenontap,allpactivenontap
768 calma 65 20
769
770#----------------------------------------------------------------
771# TAP
772#----------------------------------------------------------------
773
774 layer TAP allnactivetap,allpactivetap
775 labels allnactivetap,allpactivetap
776 calma 65 44
777
778#----------------------------------------------------------------
779# PPLUS, NPLUS (PSDM, NSDM)
780#----------------------------------------------------------------
781
782 templayer basePPLUS pdiffres,mvpdiffres
783 grow 15
784 or xhrpoly,uhrpoly,xpc
785 grow 110
786 bloat-or allpactivetap * 125 allnactivenontap 0
787 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]788
789 templayer baseNPLUS ndiffres,mvndiffres
790 grow 125
791 bloat-or allnactivetap * 125 allpactivenontap 0
792 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]793
794 templayer extendPPLUS basePPLUS,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]795 bridge 380 380
796 and-not baseNPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]797 and-not CELLRING
798
799 layer PPLUS basePPLUS,extendPPLUS
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]800 grow 185
801 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]802 close 265000
803 calma 94 20
804
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]805 templayer extendNPLUS baseNPLUS,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]806 bridge 380 380
807 and-not basePPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]808 and-not CELLRING
809
810 layer NPLUS baseNPLUS,extendNPLUS
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]811 grow 185
812 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]813 close 265000
814 calma 93 44
815
816#----------------------------------------------------------------
817# LVTN
818#----------------------------------------------------------------
819
820 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
821 grow 180
822 bridge 380 380
823 grow 185
824 shrink 185
825 close 265000
826 calma 125 44
827
828#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]829# HVTR
830#----------------------------------------------------------------
831
832 layer HVTR pfetmvt
833 grow 180
834 bridge 380 380
835 grow 185
836 shrink 185
837 close 265000
838 calma 18 20
839
840#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]841# HVTP
842#----------------------------------------------------------------
843
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]844 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]845 grow 180
846 bridge 380 380
847 grow 185
848 shrink 185
849 close 265000
850 calma 78 44
851
852#----------------------------------------------------------------
853# SONOS
854#----------------------------------------------------------------
855
856 layer SONOS nsonos
857 grow 100
858 grow-min 410
859 bridge 500 410
860 grow 250
861 shrink 250
862 calma 80 20
863
864#----------------------------------------------------------------
865# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]866# coreli layer indicates a cell needing COREID. Also, devices
867# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]868#----------------------------------------------------------------
869
870 layer COREID
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]871 bloat-all nsonos,coreli,ppu,npd,npass CELLBOUND
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]872 calma 81 2
873
874#----------------------------------------------------------------
875# STDCELL applies to all cells containing scnfet or scpfet.
876#----------------------------------------------------------------
877
878 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]879 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]880 calma 81 4
881
882#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]883# NPNID and PNPID apply to bipolar transistors
884#----------------------------------------------------------------
885
886 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]887 bloat-all npn dnwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]888 calma 82 20
889
890 templayer pnparea pnp
891 grow 400
892
893 layer PNPID
894 bloat-all pnparea *psd
895 or pnparea
896 calma 82 44
897
898#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]899# RPM
900#----------------------------------------------------------------
901
902 layer RPM
903 bloat-all xhrpoly xpc
904 grow 200
905 grow-min 1270
906 grow 420
907 shrink 420
908 calma 86 20
909
910#----------------------------------------------------------------
911# URPM (2kOhms/sq. poly implant)
912#----------------------------------------------------------------
913
914 layer URPM
915 bloat-all uhrpoly xpc
916 grow 200
917 grow-min 1270
918 grow 420
919 shrink 420
920 calma 79 20
921
922#----------------------------------------------------------------
923# LDNTM (Tip implant for SONOS FETs)
924#----------------------------------------------------------------
925
926 layer LDNTM
927 bloat-all nsonos *ndiff
928 grow 185
929 grow 345
930 shrink 345
931 calma 11 44
932
933#----------------------------------------------------------------
934# HVNTM (Tip implant for MV ndiff devices)
935#----------------------------------------------------------------
936
937 templayer hvntm_block *mvpsd
938 grow 185
939
940 layer HVNTM
941 bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
942 bloat-all mvvaractor *mvnsd
943 and-not hvntm_block
944 grow 185
945 grow 345
946 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]947 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]948 calma 125 20
949
950#----------------------------------------------------------------
951# POLY
952#----------------------------------------------------------------
953
954 layer POLY allpoly
955 calma 66 20
956
957 layer POLYTXT
958 labels allpoly noport
959 calma 66 16
960
961 layer POLYPIN
962 labels allpoly port
963 calma 66 5
964
965#----------------------------------------------------------------
966# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
967#----------------------------------------------------------------
968
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]969 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]970 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]971 bloat-all alldiffmv nwell
972 grow 345
973 shrink 345
974
975 templayer large_ptap_mv thkox_area
976 shrink 420
977 grow 420
978
979 templayer small_ptap_mv thkox_area
980 and-not large_ptap_mv
981 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
982 grow-min 840
983
984 templayer baseTHKOX thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]985 bridge 700 600
986 grow 345
987 shrink 345
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]988
989 templayer extendTHKOX baseTHKOX,CELLRING
990 grow 345
991 shrink 345
992 and-not CELLRING
993
994 layer THKOX baseTHKOX,extendTHKOX
995 calma 75 20
996
997#----------------------------------------------------------------
998# CONT (LICON)
999#----------------------------------------------------------------
1000
1001 layer CONT allcont
1002 squares-grid 0 170 170
1003 calma 66 44
1004
1005 # Contact for pres is different than other LICON contacts
1006 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1007 templayer xpc_horiz xpc
1008 shrink 1007
1009 grow 1007
1010
1011 layer CONT xpc
1012 and-not xpc_horiz
1013 # Force long edge vertical for contacts narrower than 2um
1014 # Minimum space is 350 but 520 satisfies no. of contacts rule
1015 slots 80 190 520 80 2000 350
1016 calma 66 44
1017
1018 layer CONT xpc
1019 and xpc_horiz
1020 # Force long edge vertical for contacts wider than 2um
1021 # Minimum space is 350 but 520 satisfies no. of contacts rule
1022 slots 80 2000 350 80 190 520
1023 calma 66 44
1024
1025#----------------------------------------------------------------
1026# NPC (Nitride poly cut)
1027# surrounds CONT (LICON) on poly only (i.e., pc)
1028#----------------------------------------------------------------
1029
1030 layer NPC pc
1031 squares-grid 0 170 170
1032 grow 100
1033 bridge 270 270
1034 grow 130
1035 shrink 130
1036 calma 95 20
1037
1038 # NPC is also generated on xhrpoly and uhrpoly resistors
1039
1040 layer NPC xpc,xhrpoly,uhrpoly
1041 # xpc surrounds precision_resistor by 0.095um
1042 grow 95
1043 grow 130
1044 shrink 130
1045 calma 95 20
1046
1047#----------------------------------------------------------------
1048# Device markers
1049#----------------------------------------------------------------
1050
1051 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1052 calma 65 13
1053
1054 layer POLYRES mrp1
1055 calma 66 13
1056
1057 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1058 layer POLYSHORT rmp
1059 calma 66 15
1060
1061 # POLYRES extends to edge of contact cut
1062 layer POLYRES xhrpoly,uhrpoly
1063 grow 60
1064 and xpc
1065 or xhrpoly,uhrpoly
1066 calma 66 13
1067
1068 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1069 # To be done: Expand to include anode, cathode, and guard ring
1070 calma 81 23
1071
1072#----------------------------------------------------------------
1073# LI
1074#----------------------------------------------------------------
1075 layer LI allli
1076 calma 67 20
1077
1078 layer LITXT
1079 labels *locali,coreli noport
1080 calma 67 16
1081
1082 layer LIPIN
1083 labels *locali,coreli port
1084 calma 67 5
1085
1086 layer LIRES rli
1087 labels rli
1088 calma 67 13
1089
1090#----------------------------------------------------------------
1091# MCON
1092#----------------------------------------------------------------
1093 layer MCON lic
1094 squares-grid 0 170 190
1095 calma 67 44
1096
1097#----------------------------------------------------------------
1098# MET1
1099#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1100 layer MET1 allm1,m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1101 calma 68 20
1102
1103 layer MET1TXT
1104 labels allm1 noport
1105 calma 68 16
1106
1107 layer MET1PIN
1108 labels allm1 port
1109 calma 68 5
1110
1111 layer MET1RES rm1
1112 labels rm1
1113 calma 68 13
1114
1115#----------------------------------------------------------------
1116# VIA1
1117#----------------------------------------------------------------
1118 layer VIA1 via1
1119 squares-grid 55 150 170
1120 calma 68 44
1121
1122#----------------------------------------------------------------
1123# MET2
1124#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1125 layer MET2 allm2,m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1126 calma 69 20
1127
1128 layer MET2TXT
1129 labels allm2 noport
1130 calma 69 16
1131
1132 layer MET2PIN
1133 labels allm2 port
1134 calma 69 5
1135
1136 layer MET2RES rm2
1137 labels rm2
1138 calma 69 13
1139
1140#----------------------------------------------------------------
1141# VIA2
1142#----------------------------------------------------------------
1143 layer VIA2 via2
1144 squares-grid 40 200 200
1145 calma 69 44
1146
1147#----------------------------------------------------------------
1148# MET3
1149#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1150 layer MET3 allm3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1151 calma 70 20
1152
1153 layer MET3TXT
1154 labels allm3 noport
1155 calma 70 16
1156
1157 layer MET3PIN
1158 labels allm3 port
1159 calma 70 5
1160
1161 layer MET3RES rm3
1162 labels rm3
1163 calma 70 13
1164
1165#ifdef METAL5
1166#----------------------------------------------------------------
1167# VIA3
1168#----------------------------------------------------------------
1169 layer VIA3 via3
1170#ifdef MIM
1171 or mimcc
1172#endif (MIM)
1173 squares-grid 60 200 200
1174 calma 70 44
1175
1176#----------------------------------------------------------------
1177# MET4
1178#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1179 layer MET4 allm4,m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1180 calma 71 20
1181
1182 layer MET4TXT
1183 labels allm4 noport
1184 calma 71 16
1185
1186 layer MET4PIN
1187 labels allm4 port
1188 calma 71 5
1189
1190 layer MET4RES rm4
1191 labels rm4
1192 calma 71 13
1193
1194#----------------------------------------------------------------
1195# VIA4
1196#----------------------------------------------------------------
1197 layer VIA4 via4
1198#ifdef MIM
1199 or mim2cc
1200#endif (MIM)
1201 squares-grid 190 800 800
1202 calma 71 44
1203
1204#----------------------------------------------------------------
1205# MET5
1206#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1207 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1208 calma 72 20
1209
1210 layer MET5TXT
1211 labels allm5 noport
1212 calma 72 16
1213
1214 layer MET5PIN
1215 labels allm5 port
1216 calma 72 5
1217
1218 layer MET5RES rm5
1219 labels rm5
1220 calma 72 13
1221
1222#endif (METAL5)
1223
1224#ifdef REDISTRIBUTION
1225#----------------------------------------------------------------
1226# RDL
1227#----------------------------------------------------------------
1228 layer RDL *metrdl
1229 calma 74 20
1230
1231 layer RDLTXT
1232 labels *metrdl noport
1233 calma 74 16
1234
1235 layer RDLPIN
1236 labels *metrdl port
1237 calma 74 5
1238
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1239 layer PI1 *metrdl
1240 and padl,glass
1241 # Test only---needs GDS layer number
1242
1243 layer UBM *metrdl
1244 shrink 50000
1245 grow 40000
1246 # Test only---needs GDS layer number
1247
1248 layer PI2 *metrdl
1249 shrink 50000
1250 grow 25000
1251 # Test only---needs GDS layer number
1252
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1253#endif REDISTRIBUTION
1254
1255#----------------------------------------------------------------
1256# GLASS
1257#----------------------------------------------------------------
1258 layer GLASS glass
1259 calma 76 20
1260
1261#ifdef MIM
1262#----------------------------------------------------------------
1263# CAPM
1264#----------------------------------------------------------------
1265 layer CAPM *mimcap
1266 labels mimcap
1267 calma 89 44
1268
1269 layer CAPM2 *mimcap2
1270 labels mimcap2
1271 calma 97 44
1272#endif (MIM)
1273
1274#----------------------------------------------------------------
1275# Chip top level marker for DRC latchup rules to check 15um
1276# distance to taps (otherwise 6um is used)
1277#----------------------------------------------------------------
1278
1279 layer LOWTAPDENSITY
1280 bbox top
1281 # Clear 200um for pads + 50um for required high tap density
1282 # in critical area.
1283 shrink 250000
1284 calma 81 14
1285
1286#----------------------------------------------------------------
1287# FILLBLOCK
1288#----------------------------------------------------------------
1289 layer FILLOBSM1 fillblock
1290 calma 62 24
1291
1292 layer FILLOBSM2 fillblock
1293 calma 105 52
1294
1295 layer FILLOBSM3 fillblock
1296 calma 107 24
1297
1298 layer FILLOBSM4 fillblock
1299 calma 112 4
1300
1301 render DNWELL cwell -0.1 0.1
1302 render NWELL nwell 0.0 0.2062
1303 render DIFF ndiffusion 0.2062 0.12
1304 render TAP pdiffusion 0.2062 0.12
1305 render POLY polysilicon 0.3262 0.18
1306 render CONT via 0.5062 0.43
1307 render LI metal1 0.9361 0.10
1308 render MCON via 1.0361 0.34
1309 render MET1 metal2 1.3761 0.36
1310 render VIA1 via 1.7361 0.27
1311 render MET2 metal3 2.0061 0.36
1312 render VIA2 via 2.3661 0.42
1313 render MET3 metal4 2.7861 0.845
1314#ifdef METAL5
1315 render VIA3 via 3.6311 0.39
1316 render MET4 metal5 4.0211 0.845
1317 render VIA4 via 4.8661 0.505
1318 render MET5 metal6 5.3711 1.26
1319 render CAPM metal8 2.4661 0.2
1320 render CAPM2 metal9 3.7311 0.2
1321#ifdef REDISTRIBUTION
1322 render RDL metal7 11.8834 4.0
1323#endif (!REDISTRIBUTION)
1324#endif (!METAL5)
1325
1326#----------------------------------------------------------------
1327style drc
1328#----------------------------------------------------------------
1329# NOTE: This style is used for DRC only, not for GDS output
1330#----------------------------------------------------------------
1331 scalefactor 10 nanometers
1332 options calma-permissive-labels
1333
1334 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1335 templayer dnwell_shrink dnwell
1336 shrink 1030
1337
1338 templayer nwell_missing dnwell
1339 grow 400
1340 and-not dnwell_shrink
1341 and-not nwell
1342
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1343 templayer pwell_in_dnwell dnwell
1344 and-not nwell
1345
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1346 # SONOS nFET devices must be in deep nwell
1347 templayer dnwell_missing nsonos
1348 and-not dnwell
1349
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1350 # SONOS nFET devices must be in cell with abutment box
1351 templayer abutment_box
1352 boundary
1353
1354 templayer bbox_missing nsonos
1355 and-not abutment_box
1356
1357 # Make sure nwell covers varactor poly
1358 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1359 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1360 grow 150
1361 and-not nwell
1362
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1363 # Define MiM cap bottom plate for spacing rule
1364 templayer mim_bottom
1365 bloat-all *mimcap *metal3
1366
1367 # Define MiM2 cap bottom plate for spacing rule
1368 templayer mim2_bottom
1369 bloat-all *mimcap2 *metal4
1370
1371 # Note that metal fill is performed by the foundry and so is not
1372 # an option for a cifoutput style.
1373
1374 # Check latchup rule (15um minimum from tap LICON center to any
1375 # non-tap diffusion. Note that to count as a tap, the diffusion
1376 # must be contacted to LI
1377
1378 templayer ptap_reach psc,mvpsc
1379 and-not dnwell
1380 # grow total is 15um. grow in 0.84um increments to ensure that
1381 # no nwell ring is crossed
1382 grow 840
1383 and-not nwell,dnwell
1384 grow 840
1385 and-not nwell,dnwell
1386 grow 840
1387 and-not nwell,dnwell
1388 grow 840
1389 and-not nwell,dnwell
1390 grow 840
1391 and-not nwell,dnwell
1392 grow 840
1393 and-not nwell,dnwell
1394 grow 840
1395 and-not nwell,dnwell
1396 grow 840
1397 and-not nwell,dnwell
1398 grow 840
1399 and-not nwell,dnwell
1400 grow 840
1401 and-not nwell,dnwell
1402 grow 840
1403 and-not nwell,dnwell
1404 grow 840
1405 and-not nwell,dnwell
1406 grow 840
1407 and-not nwell,dnwell
1408 grow 840
1409 and-not nwell,dnwell
1410 grow 840
1411 and-not nwell,dnwell
1412 grow 840
1413 and-not nwell,dnwell
1414 grow 840
1415 and-not nwell,dnwell
1416 grow 635
1417 and-not nwell,dnwell
1418
1419 templayer ptap_missing *ndiff,*mvndiff
1420 and-not dnwell
1421 and-not ptap_reach
1422
1423 templayer ntap_reach nsc,mvnsc
1424 # grow total is 15um. grow in 1.27um increments to ensure that
1425 # no nwell ring is crossed. There is no difference between
1426 # ntaps in and out of deep nwell.
1427 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1428 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1429 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1430 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1431 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1432 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1433 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1434 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1435 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1436 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1437 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1438 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1439 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1440 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1441 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1442 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1443 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1444 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1445 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1446 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1447 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1448 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1449 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1450 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1451
1452 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1453 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1454 and-not ntap_reach
1455
1456 templayer dptap_reach psc,mvpsc
1457 and dnwell
1458 grow 840
1459 and-not nwell
1460 and dnwell
1461 grow 840
1462 and-not nwell
1463 and dnwell
1464 grow 840
1465 and-not nwell
1466 and dnwell
1467 grow 840
1468 and-not nwell
1469 and dnwell
1470 grow 840
1471 and-not nwell
1472 and dnwell
1473 grow 840
1474 and-not nwell
1475 and dnwell
1476 grow 840
1477 and-not nwell
1478 and dnwell
1479 grow 840
1480 and-not nwell
1481 and dnwell
1482 grow 840
1483 and-not nwell
1484 and dnwell
1485 grow 840
1486 and-not nwell
1487 and dnwell
1488 grow 840
1489 and-not nwell
1490 and dnwell
1491 grow 840
1492 and-not nwell
1493 and dnwell
1494 grow 840
1495 and-not nwell
1496 and dnwell
1497 grow 840
1498 and-not nwell
1499 and dnwell
1500 grow 840
1501 and-not nwell
1502 and dnwell
1503 grow 840
1504 and-not nwell
1505 and dnwell
1506 grow 840
1507 and-not nwell
1508 and dnwell
1509 grow 635
1510 and-not nwell
1511 and dnwell
1512
1513 templayer dptap_missing *ndiff,*mvndiff
1514 and dnwell
1515 and-not dptap_reach
1516
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1517 templayer pdiff_crosses_dnwell dnwell
1518 grow 20
1519 and-not dnwell
1520 and allpdifflv,allpdiffmv
1521
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1522 # MV nwell must be 2um from any other nwell
1523 templayer mvnwell
1524 bloat-all alldiffmv nwell
1525 grow-min 840
1526 bridge 700 600
1527
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1528 # Simple spacing checks to lvnwell must use CIF-DRC rule
1529 templayer allmvdiffnowell *mvndiff,*mvpsd
1530
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1531 templayer lvnwell nwell
1532 and-not mvnwell
1533
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1534 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1535 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1536
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1537 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1538 and-not nwell_with_tap
1539
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1540 templayer tap_with_licon
1541 bloat-all psc,mvpsc psd,mvpsd
1542 bloat-all nsc,mvnsc nsd,mvnsd
1543
1544 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1545 and-not tap_with_licon
1546
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1547 # Make sure varactor nwell contains no P diffusion
1548 templayer pdiff_in_varactor_well
1549 bloat-all varactor,mvvaractor nwell
1550 and allpactive
1551
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1552 # HVNTM spacing requires recreating HVNTM
1553 templayer hvntm_block *mvpsd
1554 grow 185
1555
1556 templayer hvntm_generate
1557 bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
1558 bloat-all mvvaractor *mvnsd
1559 and-not hvntm_block
1560 grow 185
1561 grow 345
1562 shrink 345
1563 and-not hvntm_block
1564
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1565 templayer m1_small_hole allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1566 close 140000
1567
1568 templayer m1_hole_empty m1_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1569 and-not allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1570
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1571 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1572 close 140000
1573
1574 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1575 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1576
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1577 templayer m1_huge allm1
1578 shrink 1500
1579 grow 1500
1580
1581 templayer m1_large_halo m1_huge
1582 grow 280
1583 and-not m1_huge
1584 and allm1
1585
1586 templayer m2_huge allm2
1587 shrink 1500
1588 grow 1500
1589
1590 templayer m2_large_halo m2_huge
1591 grow 280
1592 and-not m2_huge
1593 and allm2
1594
1595 templayer m3_huge allm3
1596 shrink 1500
1597 grow 1500
1598
1599 templayer m3_large_halo m3_huge
1600 grow 400
1601 and-not m3_huge
1602 and allm3
1603
1604 templayer m4_huge allm4
1605 shrink 1500
1606 grow 1500
1607
1608 templayer m4_large_halo m4_huge
1609 grow 400
1610 and-not m4_huge
1611 and allm4
1612
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1613#ifdef EXPERIMENTAL
1614#----------------------------------------------------------------
1615style paint
1616#----------------------------------------------------------------
1617# NOTE: This style is used for database manipulations only via
1618# the "cif paint" command.
1619#----------------------------------------------------------------
1620
1621 scalefactor 10 nanometers
1622
1623 templayer m1grow *m1
1624 grow 290
1625
1626 # layer listrap: Use the following set of commands to strap local
1627 # interconnect wires with metal1 (inside the cursor box) to satisfy
1628 # the maximum aspect ratio rule for local interconnect:
1629 #
1630 # tech unlock *
1631 # cif ostyle paint
1632 # cif paint m1strap comment
1633 # cif paint m1strap m1
1634 # cif paint listrap licon
1635 # erase comment
1636
1637 templayer m1strap *li
1638 and-not m1grow
1639 grow 30
1640
1641 templayer listrap comment
1642 slots 30 170 170 60
1643
1644#endif (EXPERIMENTAL)
1645
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1646#----------------------------------------------------------------
1647style wafflefill
1648#----------------------------------------------------------------
1649# Style used by scripts for automatically generating fill layers
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1650#----------------------------------------------------------------
1651 scalefactor 10 nanometers
1652 options calma-permissive-labels
1653 gridlimit 5
1654
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1655#----------------------------------------------------------------
1656# Generate guard-band around nwells to keep FOM from crossing
1657# Spacing from nwell = Diff/Tap 9 = 0.34um
1658# Enclosure by nwell = Diff/Tap 8 = 0.18um
1659#----------------------------------------------------------------
1660 templayer well_shrink nwell
1661 shrink 180
1662 templayer well_guardband nwell
1663 grow 340
1664 and-not well_shrink
1665
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1666#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1667# Interleaved FOM and POLY fill
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1668#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1669 templayer slots_fom_pass1
1670 bbox top
1671 slots 0 4080 1320 0 4080 1320 1360 0
1672 templayer obstruct_fom_pass1 alldiff,allpoly,rpw
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1673 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1674 or well_guardband
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1675 templayer fomfill_pass1 slots_fom_pass1
1676 and-not obstruct_fom_pass1
1677 shrink 2035
1678 grow 2035
1679
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1680#---------------------------------------------------
1681
1682 templayer slots_poly_pass1
1683 bbox top
1684 slots 0 720 360 0 720 360 240 0
1685 templayer obstruct_poly_pass1 alldiff,allpoly,rpw
1686 grow 700
1687 or fomfill_pass1
1688 grow 300
1689 or well_guardband
1690 templayer polyfill_pass1 slots_poly_pass1
1691 and-not obstruct_poly_pass1
1692 shrink 355
1693 grow 355
1694
1695#---------------------------------------------------
1696
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1697 templayer slots_fom_pass2
1698 bbox top
1699 slots 0 2500 1320 0 2500 1320 1360 0
1700 templayer obstruct_fom_pass2 fomfill_pass1
1701 grow 820
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1702 grow 200
1703 or polyfill_pass1
1704 grow 300
1705 or obstruct_fom_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1706 templayer fomfill_pass2 slots_fom_pass2
1707 and-not obstruct_fom_pass2
1708 shrink 1245
1709 grow 1245
1710
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1711#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1712
1713 templayer slots_poly_coarse
1714 bbox top
1715 slots 0 720 360 0 720 360 240 120
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1716 templayer obstruct_poly_coarse polyfill_pass1
1717 grow 60
1718 or fomfill_pass1,fomfill_pass2
1719 grow 300
1720 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1721 templayer polyfill_coarse slots_poly_coarse
1722 and-not obstruct_poly_coarse
1723 shrink 355
1724 grow 355
1725
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1726#---------------------------------------------------
1727
1728 templayer slots_fom_coarse
1729 bbox top
1730 slots 0 1500 1320 0 1500 1320 1360 0
1731 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1732 grow 1020
1733 or polyfill_pass1,polyfill_coarse
1734 grow 300
1735 or obstruct_fom_pass1
1736 templayer fomfill_coarse slots_fom_coarse
1737 and-not obstruct_fom_coarse
1738 shrink 745
1739 grow 745
1740
1741#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1742 templayer slots_poly_medium
1743 bbox top
1744 slots 0 540 360 0 540 360 240 100
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1745 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
1746 grow 1010
1747 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1748 templayer polyfill_medium slots_poly_medium
1749 and-not obstruct_poly_medium
1750 shrink 265
1751 grow 265
1752
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1753#---------------------------------------------------
1754
1755 templayer slots_fom_fine
1756 bbox top
1757 slots 0 500 400 0 500 400 160 0
1758 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1759 grow 1320
1760 or obstruct_fom_pass1
1761 templayer fomfill_fine slots_fom_fine
1762 and-not obstruct_fom_fine
1763 shrink 245
1764 grow 245
1765
1766#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1767 templayer slots_poly_fine
1768 bbox top
1769 slots 0 480 360 0 480 360 240 200
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1770 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1771 grow 650
1772 or polyfill_pass1,polyfill_coarse,polyfill_medium
1773 grow 360
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1774 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1775 templayer polyfill_fine slots_poly_fine
1776 and-not obstruct_poly_fine
1777 shrink 235
1778 grow 235
1779
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1780#---------------------------------------------------
1781 templayer fomfill fomfill_pass1
1782 or fomfill_pass2
1783 or fomfill_coarse
1784 or fomfill_fine
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1785
1786 templayer polyfill polyfill_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1787 or polyfill_coarse
1788 or polyfill_medium
1789 or polyfill_fine
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1790
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1791 layer FOMMASK fomfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1792 calma 23 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1793 layer POLYMASK polyfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1794 calma 28 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1795
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1796#---------------------------------------------------
1797# MET1 fill
1798#---------------------------------------------------
1799 templayer slots_m1_coarse
1800 bbox top
1801 slots 0 2000 200 0 2000 200 700 0
1802 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock
1803 grow 3000
1804 templayer met1fill_coarse slots_m1_coarse
1805 and-not obstruct_m1_coarse
1806 shrink 995
1807 grow 995
1808
1809 templayer slots_m1_medium
1810 bbox top
1811 slots 0 1000 200 0 1000 200 700 0
1812 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock
1813 grow 2800
1814 or met1fill_coarse
1815 grow 200
1816 templayer met1fill_medium slots_m1_medium
1817 and-not obstruct_m1_medium
1818 shrink 495
1819 grow 495
1820
1821 templayer slots_m1_fine
1822 bbox top
1823 slots 0 580 200 0 580 200 700 0
1824 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock
1825 grow 300
1826 or met1fill_coarse,met1fill_medium
1827 grow 200
1828 templayer met1fill_fine slots_m1_fine
1829 and-not obstruct_m1_fine
1830 shrink 285
1831 grow 285
1832
1833 templayer slots_m1_veryfine
1834 bbox top
1835 slots 0 300 200 0 300 200 100 50
1836 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock
1837 grow 100
1838 or met1fill_coarse,met1fill_medium,met1fill_fine
1839 grow 200
1840 templayer met1fill_veryfine slots_m1_veryfine
1841 and-not obstruct_m1_veryfine
1842 shrink 145
1843 grow 145
1844
1845 layer MET1MASK met1fill_coarse
1846 or met1fill_medium
1847 or met1fill_fine
1848 or met1fill_veryfine
1849 calma 36 0
1850
1851#---------------------------------------------------
1852# MET2 fill
1853#---------------------------------------------------
1854 templayer slots_m2_coarse
1855 bbox top
1856 slots 0 2000 200 0 2000 200 700 350
1857 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock
1858 grow 3000
1859 templayer met2fill_coarse slots_m2_coarse
1860 and-not obstruct_m2
1861 shrink 995
1862 grow 995
1863
1864 templayer slots_m2_medium
1865 bbox top
1866 slots 0 1000 200 0 1000 200 700 350
1867 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock
1868 grow 2800
1869 or met2fill_coarse
1870 grow 200
1871 templayer met2fill_medium slots_m2_medium
1872 and-not obstruct_m2_medium
1873 shrink 495
1874 grow 495
1875
1876 templayer slots_m2_fine
1877 bbox top
1878 slots 0 580 200 0 580 200 700 350
1879 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock
1880 grow 300
1881 or met2fill_coarse,met2fill_medium
1882 grow 200
1883 templayer met2fill_fine slots_m2_fine
1884 and-not obstruct_m2_fine
1885 shrink 285
1886 grow 285
1887
1888 templayer slots_m2_veryfine
1889 bbox top
1890 slots 0 300 200 0 300 200 100 100
1891 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock
1892 grow 100
1893 or met2fill_coarse,met2fill_medium,met2fill_fine
1894 grow 200
1895 templayer met2fill_veryfine slots_m2_veryfine
1896 and-not obstruct_m2_veryfine
1897 shrink 145
1898 grow 145
1899
1900 layer MET2MASK met2fill_coarse
1901 or met2fill_medium
1902 or met2fill_fine
1903 or met2fill_veryfine
1904 calma 41 0
1905
1906#---------------------------------------------------
1907# MET3 fill
1908#---------------------------------------------------
1909 templayer slots_m3_coarse
1910 bbox top
1911 slots 0 2000 300 0 2000 300 700 700
1912 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock
1913 grow 3000
1914 templayer met3fill_coarse slots_m3_coarse
1915 and-not obstruct_m3
1916 shrink 995
1917 grow 995
1918
1919 templayer slots_m3_medium
1920 bbox top
1921 slots 0 1000 300 0 1000 300 700 700
1922 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock
1923 grow 2700
1924 or met3fill_coarse
1925 grow 300
1926 templayer met3fill_medium slots_m3_medium
1927 and-not obstruct_m3_medium
1928 shrink 495
1929 grow 495
1930
1931 templayer slots_m3_fine
1932 bbox top
1933 slots 0 580 300 0 580 300 700 700
1934 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock
1935 grow 200
1936 or met3fill_coarse,met3fill_medium
1937 grow 300
1938 templayer met3fill_fine slots_m3_fine
1939 and-not obstruct_m3_fine
1940 shrink 285
1941 grow 285
1942
1943 templayer slots_m3_veryfine
1944 bbox top
1945 slots 0 400 300 0 400 300 150 200
1946 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock
1947 or met3fill_coarse,met3fill_medium,met3fill_fine
1948 grow 300
1949 templayer met3fill_veryfine slots_m3_veryfine
1950 and-not obstruct_m3_veryfine
1951 shrink 195
1952 grow 195
1953
1954 layer MET3MASK met3fill_coarse
1955 or met3fill_medium
1956 or met3fill_fine
1957 or met3fill_veryfine
1958 calma 34 0
1959
1960#ifdef METAL5
1961#---------------------------------------------------
1962# MET4 fill
1963#---------------------------------------------------
1964 templayer slots_m4_coarse
1965 bbox top
1966 slots 0 2000 300 0 2000 300 700 1050
1967 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock
1968 grow 3000
1969 templayer met4fill_coarse slots_m4_coarse
1970 and-not obstruct_m4
1971 shrink 995
1972 grow 995
1973
1974 templayer slots_m4_medium
1975 bbox top
1976 slots 0 1000 300 0 1000 300 700 1050
1977 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock
1978 grow 2700
1979 or met4fill_coarse
1980 grow 300
1981 templayer met4fill_medium slots_m4_medium
1982 and-not obstruct_m4_medium
1983 shrink 495
1984 grow 495
1985
1986 templayer slots_m4_fine
1987 bbox top
1988 slots 0 580 300 0 580 300 700 1050
1989 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock
1990 grow 200
1991 or met4fill_coarse,met4fill_medium
1992 grow 300
1993 templayer met4fill_fine slots_m4_fine
1994 and-not obstruct_m4_fine
1995 shrink 285
1996 grow 285
1997
1998 templayer slots_m4_veryfine
1999 bbox top
2000 slots 0 400 300 0 400 300 150 300
2001 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock
2002 or met4fill_coarse,met4fill_medium,met4fill_fine
2003 grow 300
2004 templayer met4fill_veryfine slots_m4_veryfine
2005 and-not obstruct_m4_veryfine
2006 shrink 195
2007 grow 195
2008
2009 layer MET4MASK met4fill_coarse
2010 or met4fill_medium
2011 or met4fill_fine
2012 or met4fill_veryfine
2013 calma 51 0
2014
2015#---------------------------------------------------
2016# MET5 fill
2017#---------------------------------------------------
2018 templayer slots_m5
2019 bbox top
2020 slots 0 3000 1600 0 3000 1600 1000 100
2021 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2022 grow 3000
2023 templayer met5fill_gen slots_m5
2024 and-not obstruct_m5
2025 shrink 1495
2026 grow 1495
2027
2028 layer MET5MASK met5fill_gen
2029 calma 59 0
2030#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2031
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2032end
2033
2034#-----------------------------------------------------------------------
2035cifinput
2036#-----------------------------------------------------------------------
2037# NOTE: All values in this section MUST be multiples of 25
2038# or else magic will scale below the allowed layout grid size
2039#-----------------------------------------------------------------------
2040
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]2041style sky130
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2042 scalefactor 10 nanometers
2043 gridlimit 5
2044
2045 options ignore-unknown-layer-labels no-reconnect-labels
2046
2047#ifndef MIM
2048 ignore CAPM
2049 ignore CAPM2
2050#endif (!MIM)
2051#ifndef METAL5
2052 ignore MET4,VIA3
2053 ignore MET5,VIA4
2054#endif
2055 ignore NPC
2056 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2057 ignore CAPID
2058 ignore LDNTM
2059 ignore HVNTM
2060 ignore POLYMOD
2061 ignore LOWTAPDENSITY
2062
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2063 layer pnp NWELL,WELLTXT,WELLPIN
2064 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2065 labels NWELL
2066 labels WELLTXT text
2067 labels WELLPIN port
2068
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2069 layer nwell NWELL,WELLTXT,WELLPIN
2070 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2071 labels NWELL
2072 labels WELLTXT text
2073 labels WELLPIN port
2074
2075 layer pwell SUBTXT,SUBPIN
2076 labels SUBTXT text
2077 labels SUBPIN port
2078
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2079 # Always draw pwell under p-tap
2080 layer pwell TAP
2081 and-not NWELL
2082
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2083 layer dnwell DNWELL
2084 labels DNWELL
2085
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2086 layer npn DNWELL
2087 and-not NWELL
2088 and NPNID
2089
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2090 layer rpw PWRES
2091 and DNWELL
2092 labels PWRES
2093
2094 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
2095 and-not POLY
2096 and-not NWELL
2097 and-not PPLUS
2098 and-not DIODE
2099 and-not DIFFRES
2100 and-not THKOX
2101 and NPLUS
2102 copyup ndifcheck
2103 labels DIFF
2104 labels DIFFTXT text
2105 labels DIFFPIN port
2106 labels TAPPIN port
2107
2108 layer ndiff ndiffarea
2109
2110 # Copy ndiff areas up for contact checks
2111 templayer xndifcheck ndifcheck
2112 copyup ndifcheck
2113
2114 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
2115 and-not POLY
2116 and-not NWELL
2117 and-not PPLUS
2118 and-not DIODE
2119 and-not DIFFRES
2120 and THKOX
2121 and NPLUS
2122 copyup ndifcheck
2123 labels DIFF
2124 labels DIFFTXT text
2125 labels DIFFPIN port
2126
2127 layer mvndiff mvndiffarea
2128
2129 # Copy ndiff areas up for contact checks
2130 templayer mvxndifcheck mvndifcheck
2131 copyup mvndifcheck
2132
2133 layer ndiode DIFF
2134 and NPLUS
2135 and DIODE
2136 and-not NWELL
2137 and-not POLY
2138 and-not PPLUS
2139 and-not THKOX
2140 and-not LVTN
2141 labels DIFF
2142
2143 layer ndiodelvt DIFF
2144 and NPLUS
2145 and DIODE
2146 and-not NWELL
2147 and-not POLY
2148 and-not PPLUS
2149 and-not THKOX
2150 and LVTN
2151 labels DIFF
2152
2153 templayer ndiodearea DIODE
2154 and NPLUS
2155 and-not THKOX
2156 and-not NWELL
2157 copyup DIODE,NPLUS
2158
2159 layer ndiffres DIFFRES
2160 and NPLUS
2161 and-not THKOX
2162 labels DIFF
2163
2164 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2165 and-not POLY
2166 and NWELL
2167 and-not NPLUS
2168 and-not DIODE
2169 and-not THKOX
2170 and PPLUS
2171 copyup pdifcheck
2172 labels DIFF
2173 labels DIFFTXT text
2174 labels DIFFPIN port
2175
2176 layer pdiff pdiffarea
2177
2178 layer mvndiode DIFF
2179 and NPLUS
2180 and DIODE
2181 and THKOX
2182 and-not POLY
2183 and-not PPLUS
2184 and-not LVTN
2185 labels DIFF
2186
2187 layer nndiode DIFF
2188 and NPLUS
2189 and DIODE
2190 and THKOX
2191 and-not POLY
2192 and-not PPLUS
2193 and LVTN
2194 labels DIFF
2195
2196 templayer mvndiodearea DIODE
2197 and NPLUS
2198 and THKOX
2199 and-not NWELL
2200 copyup DIODE,NPLUS
2201
2202 layer mvndiffres DIFFRES
2203 and NPLUS
2204 and THKOX
2205 labels DIFF
2206
2207 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2208 and-not POLY
2209 and NWELL
2210 and-not NPLUS
2211 and THKOX
2212 and-not DIODE
2213 and-not DIFFRES
2214 and PPLUS
2215 copyup mvpdifcheck
2216 labels DIFF
2217 labels DIFFTXT text
2218 labels DIFFPIN port
2219
2220 layer mvpdiff mvpdiffarea
2221
2222 # Copy pdiff areas up for contact checks
2223 templayer xpdifcheck pdifcheck
2224 copyup pdifcheck
2225
2226 layer pdiode DIFF
2227 and PPLUS
2228 and-not POLY
2229 and-not NPLUS
2230 and-not THKOX
2231 and-not LVTN
2232 and-not HVTP
2233 and DIODE
2234 labels DIFF
2235
2236 layer pdiodelvt DIFF
2237 and PPLUS
2238 and-not POLY
2239 and-not NPLUS
2240 and-not THKOX
2241 and LVTN
2242 and-not HVTP
2243 and DIODE
2244 labels DIFF
2245
2246 layer pdiodehvt DIFF
2247 and PPLUS
2248 and-not POLY
2249 and-not NPLUS
2250 and-not THKOX
2251 and-not LVTN
2252 and HVTP
2253 and DIODE
2254 labels DIFF
2255
2256 templayer pdiodearea DIODE
2257 and PPLUS
2258 and-not THKOX
2259 copyup DIODE,PPLUS
2260
2261 # Define pfet areas as known pdiff, regardless of the presence of a well.
2262
2263 templayer pfetarea DIFF
2264 and-not NPLUS
2265 and-not THKOX
2266 and POLY
2267
2268 layer pfet pfetarea
2269 and-not LVTN
2270 and-not HVTP
2271 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2272 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2273 labels DIFF
2274
2275 layer scpfet pfetarea
2276 and-not LVTN
2277 and-not HVTP
2278 and STDCELL
2279 labels DIFF
2280
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2281 layer scpfethvt pfetarea
2282 and-not LVTN
2283 and HVTP
2284 and STDCELL
2285 labels DIFF
2286
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2287 layer ppu pfetarea
2288 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2289 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2290 and COREID
2291 labels DIFF
2292
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2293 layer pfetlvt pfetarea
2294 and LVTN
2295 labels DIFF
2296
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2297 layer pfetmvt pfetarea
2298 and HVTR
2299 labels DIFF
2300
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2301 layer pfethvt pfetarea
2302 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2303 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2304 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2305 labels DIFF
2306
2307 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2308 layer nwell pfetarea
2309 grow 180
2310
2311 # Copy mvpdiff areas up for contact checks
2312 templayer mvxpdifcheck mvpdifcheck
2313 copyup mvpdifcheck
2314
2315 layer mvpdiode DIFF
2316 and PPLUS
2317 and-not POLY
2318 and-not NPLUS
2319 and THKOX
2320 and DIODE
2321 labels DIFF
2322
2323 templayer mvpdiodearea DIODE
2324 and PPLUS
2325 and THKOX
2326 copyup DIODE,PPLUS
2327
2328 # Define pfet areas as known pdiff,
2329 # regardless of the presence of a
2330 # well.
2331
2332 templayer mvpfetarea DIFF
2333 and-not NPLUS
2334 and THKOX
2335 and POLY
2336
2337 layer mvpfet mvpfetarea
2338 labels DIFF
2339
2340 layer pdiff DIFF,DIFFTXT,DIFFPIN
2341 and-not NPLUS
2342 and-not POLY
2343 and-not THKOX
2344 and-not DIODE
2345 and-not DIFFRES
2346 labels DIFF
2347 labels DIFFTXT text
2348 labels DIFFPIN port
2349
2350 layer pdiffres DIFFRES
2351 and PPLUS
2352 and NWELL
2353 and-not THKOX
2354 labels DIFF
2355
2356 layer nfet DIFF
2357 and POLY
2358 and-not PPLUS
2359 and NPLUS
2360 and-not THKOX
2361 and-not LVTN
2362 and-not SONOS
2363 and-not STDCELL
2364 labels DIFF
2365
2366 layer scnfet DIFF
2367 and POLY
2368 and-not PPLUS
2369 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2370 and-not NWELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2371 and-not THKOX
2372 and-not LVTN
2373 and-not SONOS
2374 and STDCELL
2375 labels DIFF
2376
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2377 layer npass DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2378 and POLY
2379 and-not PPLUS
2380 and NPLUS
2381 and-not NWELL
2382 and COREID
2383 labels DIFF
2384
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2385 layer npd DIFF
2386 and POLY
2387 and-not PPLUS
2388 and NPLUS
2389 and-not NWELL
2390 and COREID
2391 # Shrink-grow operation eliminates the smaller npass device
2392 shrink 70
2393 grow 70
2394 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2395
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2396 layer nfetlvt DIFF
2397 and POLY
2398 and-not PPLUS
2399 and NPLUS
2400 and-not THKOX
2401 and LVTN
2402 and-not SONOS
2403 labels DIFF
2404
2405 layer nsonos DIFF
2406 and POLY
2407 and-not PPLUS
2408 and NPLUS
2409 and-not THKOX
2410 and LVTN
2411 and SONOS
2412 labels DIFF
2413
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2414 templayer nsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2415 and NPLUS
2416 and NWELL
2417 and-not POLY
2418 and-not PPLUS
2419 and-not THKOX
2420 copyup nsubcheck
2421
2422 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2423 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2424
2425 layer nsd TAP,TAPPIN
2426 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2427 and-not POLY
2428 and-not THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2429 labels TAP
2430 labels TAPPIN port
2431
2432 templayer nsdexpand nsdarea
2433 grow 500
2434
2435 # Copy nsub areas up for contact checks
2436 templayer xnsubcheck nsubcheck
2437 copyup nsubcheck
2438
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2439 templayer psdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2440 and PPLUS
2441 and-not NWELL
2442 and-not POLY
2443 and-not NPLUS
2444 and-not THKOX
2445 and-not pfetexpand
2446 copyup psubcheck
2447
2448 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2449 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2450
2451 layer psd TAP,TAPPIN
2452 and PPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2453 and-not POLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2454 and-not THKOX
2455 labels TAP
2456 labels TAPPIN port
2457
2458 templayer psdexpand psdarea
2459 grow 500
2460
2461 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
2462 and-not NPLUS
2463 and-not POLY
2464 and THKOX
2465 and mvpfetexpand
2466 labels DIFF
2467 labels DIFFTXT text
2468 labels DIFFPIN port
2469
2470 layer mvpdiffres DIFFRES
2471 and PPLUS
2472 and NWELL
2473 and THKOX
2474 and-not mvrdpioedge
2475 labels DIFF
2476
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2477 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2478 and POLY
2479 and-not PPLUS
2480 and NPLUS
2481 and-not LVTN
2482 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2483 grow 1000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2484
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2485 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2486 and POLY
2487 and-not PPLUS
2488 and NPLUS
2489 and LVTN
2490 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2491 and-not mvnfetarea
2492
2493 layer mvnfet DIFF
2494 and POLY
2495 and-not PPLUS
2496 and NPLUS
2497 and THKOX
2498 and-not mvnnfetarea
2499 labels DIFF
2500
2501 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2502 labels DIFF
2503
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2504 templayer mvnsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2505 and NPLUS
2506 and NWELL
2507 and-not POLY
2508 and-not PPLUS
2509 and THKOX
2510 copyup mvnsubcheck
2511
2512 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2513 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2514
2515 layer mvnsd TAP,TAPPIN
2516 and NPLUS
2517 and THKOX
2518 labels TAP
2519 labels TAPPIN port
2520
2521 templayer mvnsdexpand mvnsdarea
2522 grow 500
2523
2524 # Copy nsub areas up for contact checks
2525 templayer mvxnsubcheck mvnsubcheck
2526 copyup mvnsubcheck
2527
2528 templayer mvpsdarea DIFF
2529 and PPLUS
2530 and-not NWELL
2531 and-not POLY
2532 and-not NPLUS
2533 and THKOX
2534 and-not mvpfetexpand
2535 copyup mvpsubcheck
2536
2537 layer mvpsd mvpsdarea
2538 labels DIFF
2539
2540 layer mvpsd TAP,TAPPIN
2541 and PPLUS
2542 and THKOX
2543 labels TAP
2544 labels TAPPIN port
2545
2546 templayer mvpsdexpand mvpsdarea
2547 grow 500
2548
2549 # Copy psub areas up for contact checks
2550 templayer xpsubcheck psubcheck
2551 copyup psubcheck
2552
2553 templayer mvxpsubcheck mvpsubcheck
2554 copyup mvpsubcheck
2555
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2556 layer psd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2557 and-not PPLUS
2558 and-not NPLUS
2559 and-not POLY
2560 and-not THKOX
2561 and-not pfetexpand
2562 and psdexpand
2563
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2564 layer nsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2565 and-not PPLUS
2566 and-not NPLUS
2567 and-not POLY
2568 and-not THKOX
2569 and nsdexpand
2570
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2571 layer mvpsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2572 and-not PPLUS
2573 and-not NPLUS
2574 and-not POLY
2575 and THKOX
2576 and-not mvpfetexpand
2577 and mvpsdexpand
2578
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2579 layer mvnsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2580 and-not PPLUS
2581 and-not NPLUS
2582 and-not POLY
2583 and THKOX
2584 and mvnsdexpand
2585
2586 templayer hresarea POLY
2587 and RPM
2588 grow 3000
2589
2590 templayer uresarea POLY
2591 and URPM
2592 grow 3000
2593
2594 templayer diffresarea DIFFRES
2595 and-not THKOX
2596 grow 3000
2597
2598 templayer mvdiffresarea DIFFRES
2599 and THKOX
2600 grow 3000
2601
2602 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2603
2604 layer pfet POLY
2605 and DIFF
2606 and diffresarea
2607 and-not NPLUS
2608 and-not STDCELL
2609
2610 layer scpfet POLY
2611 and DIFF
2612 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2613 and-not HVTP
2614 and-not NPLUS
2615 and STDCELL
2616
2617 layer scpfethvt POLY
2618 and DIFF
2619 and diffresarea
2620 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2621 and-not NPLUS
2622 and STDCELL
2623
2624 templayer xpolyterm RPM,URPM
2625 and POLY
2626 and-not POLYRES
2627 # add back the 0.06um contact surround in the direction of the resistor
2628 grow 60
2629 and POLY
2630
2631 layer xpc xpolyterm
2632
2633 templayer polyarea POLY
2634 and-not POLYRES
2635 and-not POLYSHORT
2636 and-not DIFF
2637 and-not RPM
2638 and-not URPM
2639 copyup polycheck
2640
2641 layer poly polyarea,POLYTXT,POLYPIN
2642 labels POLY
2643 labels POLYTXT text
2644 labels POLYPIN port
2645
2646 # Copy (non-resistor) poly areas up for contact checks
2647 templayer xpolycheck polycheck
2648 copyup polycheck
2649
2650 layer mrp1 POLY
2651 and POLYRES
2652 and-not RPM
2653 and-not URPM
2654 labels POLY
2655
2656 layer rmp POLY
2657 and POLYSHORT
2658 labels POLY
2659
2660 layer xhrpoly POLY
2661 and POLYRES
2662 and RPM
2663 and-not URPM
2664 and PPLUS
2665 and NPC
2666 and-not xpolyterm
2667 labels POLY
2668
2669 layer uhrpoly POLY
2670 and POLYRES
2671 and URPM
2672 and-not RPM
2673 and NPC
2674 and-not xpolyterm
2675 labels POLY
2676
2677 templayer ndcbase CONT
2678 and DIFF
2679 and NPLUS
2680 and-not NWELL
2681 and LI
2682 and-not THKOX
2683
2684 layer ndc ndcbase
2685 grow 85
2686 shrink 85
2687 shrink 85
2688 grow 85
2689 or ndcbase
2690 labels CONT
2691
2692 templayer nscbase CONT
2693 and DIFF,TAP
2694 and NPLUS
2695 and NWELL
2696 and LI
2697 and-not THKOX
2698
2699 layer nsc nscbase
2700 grow 85
2701 shrink 85
2702 shrink 85
2703 grow 85
2704 or nscbase
2705 labels CONT
2706
2707 templayer pdcbase CONT
2708 and DIFF
2709 and PPLUS
2710 and NWELL
2711 and LI
2712 and-not THKOX
2713
2714 layer pdc pdcbase
2715 grow 85
2716 shrink 85
2717 shrink 85
2718 grow 85
2719 or pdcbase
2720 labels CONT
2721
2722 templayer pdcnowell CONT
2723 and DIFF
2724 and PPLUS
2725 and pfetexpand
2726 and LI
2727 and-not THKOX
2728
2729 layer pdc pdcnowell
2730 grow 85
2731 shrink 85
2732 shrink 85
2733 grow 85
2734 or pdcnowell
2735 labels CONT
2736
2737 templayer pscbase CONT
2738 and DIFF,TAP
2739 and PPLUS
2740 and-not NWELL
2741 and-not pfetexpand
2742 and LI
2743 and-not THKOX
2744
2745 layer psc pscbase
2746 grow 85
2747 shrink 85
2748 shrink 85
2749 grow 85
2750 or pscbase
2751 labels CONT
2752
2753 templayer pcbase CONT
2754 and POLY
2755 and-not DIFF
2756 and-not RPM,URPM
2757 and LI
2758
2759 layer pc pcbase
2760 grow 85
2761 shrink 85
2762 shrink 85
2763 grow 85
2764 or pcbase
2765 labels CONT
2766
2767 templayer ndicbase CONT
2768 and DIFF
2769 and NPLUS
2770 and DIODE
2771 and-not POLY
2772 and-not PPLUS
2773 and-not THKOX
2774 and-not LVTN
2775
2776 layer ndic ndicbase
2777 grow 85
2778 shrink 85
2779 shrink 85
2780 grow 85
2781 or ndicbase
2782 labels CONT
2783
2784 templayer ndilvtcbase CONT
2785 and DIFF
2786 and NPLUS
2787 and DIODE
2788 and-not POLY
2789 and-not PPLUS
2790 and-not THKOX
2791 and LVTN
2792
2793 layer ndilvtc ndilvtcbase
2794 grow 85
2795 shrink 85
2796 shrink 85
2797 grow 85
2798 or ndilvtcbase
2799 labels CONT
2800
2801 templayer pdicbase CONT
2802 and DIFF
2803 and PPLUS
2804 and DIODE
2805 and-not POLY
2806 and-not NPLUS
2807 and-not THKOX
2808 and-not LVTN
2809 and-not HVTP
2810
2811 layer pdic pdicbase
2812 grow 85
2813 shrink 85
2814 shrink 85
2815 grow 85
2816 or pdicbase
2817 labels CONT
2818
2819 templayer pdilvtcbase CONT
2820 and DIFF
2821 and PPLUS
2822 and DIODE
2823 and-not POLY
2824 and-not NPLUS
2825 and-not THKOX
2826 and LVTN
2827 and-not HVTP
2828
2829 layer pdilvtc pdilvtcbase
2830 grow 85
2831 shrink 85
2832 shrink 85
2833 grow 85
2834 or pdilvtcbase
2835 labels CONT
2836
2837 templayer pdihvtcbase CONT
2838 and DIFF
2839 and PPLUS
2840 and DIODE
2841 and-not POLY
2842 and-not NPLUS
2843 and-not THKOX
2844 and-not LVTN
2845 and HVTP
2846
2847 layer pdihvtc pdihvtcbase
2848 grow 85
2849 shrink 85
2850 shrink 85
2851 grow 85
2852 or pdihvtcbase
2853 labels CONT
2854
2855 templayer mvndcbase CONT
2856 and DIFF
2857 and NPLUS
2858 and-not NWELL
2859 and LI
2860 and THKOX
2861
2862 layer mvndc mvndcbase
2863 grow 85
2864 shrink 85
2865 shrink 85
2866 grow 85
2867 or mvndcbase
2868 labels CONT
2869
2870 templayer mvnscbase CONT
2871 and DIFF,TAP
2872 and NPLUS
2873 and NWELL
2874 and LI
2875 and THKOX
2876
2877 layer mvnsc mvnscbase
2878 grow 85
2879 shrink 85
2880 shrink 85
2881 grow 85
2882 or mvnscbase
2883 labels CONT
2884
2885 templayer mvpdcbase CONT
2886 and DIFF
2887 and PPLUS
2888 and NWELL
2889 and LI
2890 and THKOX
2891
2892 layer mvpdc mvpdcbase
2893 grow 85
2894 shrink 85
2895 shrink 85
2896 grow 85
2897 or mvpdcbase
2898 labels CONT
2899
2900 templayer mvpdcnowell CONT
2901 and DIFF
2902 and PPLUS
2903 and mvpfetexpand
2904 and MET1
2905 and THKOX
2906
2907 layer mvpdc mvpdcnowell
2908 grow 85
2909 shrink 85
2910 shrink 85
2911 grow 85
2912 or mvpdcnowell
2913 labels CONT
2914
2915 templayer mvpscbase CONT
2916 and DIFF,TAP
2917 and PPLUS
2918 and-not NWELL
2919 and-not mvpfetexpand
2920 and LI
2921 and THKOX
2922
2923 layer mvpsc mvpscbase
2924 grow 85
2925 shrink 85
2926 shrink 85
2927 grow 85
2928 or mvpscbase
2929 labels CONT
2930
2931 templayer mvndicbase CONT
2932 and DIFF
2933 and NPLUS
2934 and DIODE
2935 and-not POLY
2936 and-not PPLUS
2937 and-not LVTN
2938 and THKOX
2939
2940 layer mvndic mvndicbase
2941 grow 85
2942 shrink 85
2943 shrink 85
2944 grow 85
2945 or mvndicbase
2946 labels CONT
2947
2948 templayer nndicbase CONT
2949 and DIFF
2950 and NPLUS
2951 and DIODE
2952 and-not POLY
2953 and-not PPLUS
2954 and LVTN
2955 and THKOX
2956
2957 layer nndic nndicbase
2958 grow 85
2959 shrink 85
2960 shrink 85
2961 grow 85
2962 or nndicbase
2963 labels CONT
2964
2965 templayer mvpdicbase CONT
2966 and DIFF
2967 and PPLUS
2968 and DIODE
2969 and-not POLY
2970 and-not NPLUS
2971 and THKOX
2972
2973 layer mvpdic mvpdicbase
2974 grow 85
2975 shrink 85
2976 shrink 85
2977 grow 85
2978 or mvpdicbase
2979 labels CONT
2980
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2981 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2982 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2983 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2984 labels LI
2985 labels LITXT text
2986 labels LIPIN port
2987
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2988 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2989 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2990 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2991 labels LI
2992 labels LITXT text
2993 labels LIPIN port
2994
2995 layer rli LI
2996 and LIRES,LISHORT
2997 labels LIRES,LISHORT
2998
2999 layer lic MCON
3000 grow 95
3001 shrink 95
3002 shrink 85
3003 grow 85
3004 or MCON
3005 labels MCON
3006
3007 layer m1 MET1,MET1TXT,MET1PIN
3008 and-not MET1RES,MET1SHORT
3009 labels MET1
3010 labels MET1TXT text
3011 labels MET1PIN port
3012
3013 layer rm1 MET1
3014 and MET1RES,MET1SHORT
3015 labels MET1RES,MET1SHORT
3016
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3017 layer m1fill MET1FILL
3018 labels MET1FILL
3019
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3020#ifdef MIM
3021 layer mimcap MET3
3022 and CAPM
3023 labels CAPM
3024
3025 layer mimcc VIA3
3026 and CAPM
3027 grow 60
3028 grow 40
3029 shrink 40
3030 labels CAPM
3031
3032 layer mimcap2 MET4
3033 and CAPM2
3034 labels CAPM2
3035
3036 layer mim2cc VIA4
3037 and CAPM2
3038 grow 190
3039 grow 210
3040 shrink 210
3041 labels CAPM2
3042
3043#endif (MIM)
3044
3045 templayer m2cbase VIA1
3046 grow 55
3047
3048 layer m2c m2cbase
3049 grow 30
3050 shrink 30
3051 shrink 130
3052 grow 130
3053 or m2cbase
3054
3055 layer m2 MET2,MET2TXT,MET2PIN
3056 and-not MET2RES,MET2SHORT
3057 labels MET2
3058 labels MET2TXT text
3059 labels MET2PIN port
3060
3061 layer rm2 MET2
3062 and MET2RES,MET2SHORT
3063 labels MET2RES,MET2SHORT
3064
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3065 layer m2fill MET2FILL
3066 labels MET2FILL
3067
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3068 templayer m3cbase VIA2
3069 grow 40
3070
3071 layer m3c m3cbase
3072 grow 60
3073 shrink 60
3074 shrink 140
3075 grow 140
3076 or m3cbase
3077
3078 layer m3 MET3,MET3TXT,MET3PIN
3079 and-not MET3RES,MET3SHORT
3080#ifdef MIM
3081 and-not CAPM
3082#endif (MIM)
3083 labels MET3
3084 labels MET3TXT text
3085 labels MET3PIN port
3086
3087 layer rm3 MET3
3088 and MET3RES,MET3SHORT
3089 labels MET3RES,MET3SHORT
3090
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3091 layer m3fill MET3FILL
3092 labels MET3FILL
3093
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3094#ifdef (METAL5)
3095
3096 templayer via3base VIA3
3097#ifdef MIM
3098 and-not CAPM
3099#endif (MIM)
3100 grow 60
3101
3102 layer via3 via3base
3103 grow 40
3104 shrink 40
3105 shrink 160
3106 grow 160
3107 or via3base
3108
3109 layer m4 MET4,MET4TXT,MET4PIN
3110 and-not MET4RES,MET4SHORT
3111#ifdef MIM
3112 and-not CAPM2
3113#endif (MIM)
3114 labels MET4
3115 labels MET4TXT text
3116 labels MET4PIN port
3117
3118 layer rm4 MET4
3119 and MET4RES,MET4SHORT
3120 labels MET4RES,MET4SHORT
3121
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3122 layer m4fill MET4FILL
3123 labels MET4FILL
3124
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3125 layer m5 MET5,MET5TXT,MET5PIN
3126 and-not MET5RES,MET5SHORT
3127 labels MET5
3128 labels MET5TXT text
3129 labels MET5PIN port
3130
3131 layer rm5 MET5
3132 and MET5RES,MET5SHORT
3133 labels MET5RES,MET5SHORT
3134
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3135 layer m5fill MET5FILL
3136 labels MET5FILL
3137
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3138 templayer via4base VIA4
3139#ifdef MIM
3140 and-not CAPM2
3141#endif (MIM)
3142 grow 190
3143
3144 layer via4 via4base
3145 grow 210
3146 shrink 210
3147 shrink 590
3148 grow 590
3149 or via4base
3150#endif (METAL5)
3151
3152#ifdef REDISTRIBUTION
3153 layer metrdl RDL,RDLTXT,RDLPIN
3154 labels RDL
3155 labels RDLTXT text
3156 labels RDLPIN port
3157#endif
3158
3159 # Find diffusion not covered in
3160 # NPLUS or PPLUS and pull it into
3161 # the next layer up
3162
3163 templayer gentrans DIFF
3164 and-not PPLUS
3165 and-not NPLUS
3166 and POLY
3167 copyup DIFF,POLY
3168
3169 templayer gendiff DIFF,TAP
3170 and-not PPLUS
3171 and-not NPLUS
3172 and-not POLY
3173 copyup DIFF
3174
3175 # Handle contacts found by copyup
3176
3177 templayer ndiccopy CONT
3178 and LI
3179 and DIODE
3180 and NPLUS
3181 and-not THKOX
3182
3183 layer ndic ndiccopy
3184 grow 85
3185 shrink 85
3186 shrink 85
3187 grow 85
3188 or ndiccopy
3189 labels CONT
3190
3191 templayer mvndiccopy CONT
3192 and LI
3193 and DIODE
3194 and NPLUS
3195 and THKOX
3196
3197 layer mvndic mvndiccopy
3198 grow 85
3199 shrink 85
3200 shrink 85
3201 grow 85
3202 or mvndiccopy
3203 labels CONT
3204
3205 templayer pdiccopy CONT
3206 and LI
3207 and DIODE
3208 and PPLUS
3209 and-not THKOX
3210
3211 layer pdic pdiccopy
3212 grow 85
3213 shrink 85
3214 shrink 85
3215 grow 85
3216 or pdiccopy
3217 labels CONT
3218
3219 templayer mvpdiccopy CONT
3220 and LI
3221 and DIODE
3222 and PPLUS
3223 and THKOX
3224
3225 layer mvpdic mvpdiccopy
3226 grow 85
3227 shrink 85
3228 shrink 85
3229 grow 85
3230 or mvpdiccopy
3231 labels CONT
3232
3233 templayer ndccopy CONT
3234 and ndifcheck
3235
3236 layer ndc ndccopy
3237 grow 85
3238 shrink 85
3239 shrink 85
3240 grow 85
3241 or ndccopy
3242 labels CONT
3243
3244 templayer mvndccopy CONT
3245 and mvndifcheck
3246
3247 layer mvndc mvndccopy
3248 grow 85
3249 shrink 85
3250 shrink 85
3251 grow 85
3252 or mvndccopy
3253 labels CONT
3254
3255 templayer pdccopy CONT
3256 and pdifcheck
3257
3258 layer pdc pdccopy
3259 grow 85
3260 shrink 85
3261 shrink 85
3262 grow 85
3263 or pdccopy
3264 labels CONT
3265
3266 templayer mvpdccopy CONT
3267 and mvpdifcheck
3268
3269 layer mvpdc mvpdccopy
3270 grow 85
3271 shrink 85
3272 shrink 85
3273 grow 85
3274 or mvpdccopy
3275 labels CONT
3276
3277 templayer pccopy CONT
3278 and polycheck
3279
3280 layer pc pccopy
3281 grow 85
3282 shrink 85
3283 shrink 85
3284 grow 85
3285 or pccopy
3286 labels CONT
3287
3288 templayer nsccopy CONT
3289 and nsubcheck
3290
3291 layer nsc nsccopy
3292 grow 85
3293 shrink 85
3294 shrink 85
3295 grow 85
3296 or nsccopy
3297 labels CONT
3298
3299 templayer mvnsccopy CONT
3300 and mvnsubcheck
3301
3302 layer mvnsc mvnsccopy
3303 grow 85
3304 shrink 85
3305 shrink 85
3306 grow 85
3307 or mvnsccopy
3308 labels CONT
3309
3310 templayer psccopy CONT
3311 and psubcheck
3312
3313 layer psc psccopy
3314 grow 85
3315 shrink 85
3316 shrink 85
3317 grow 85
3318 or psccopy
3319 labels CONT
3320
3321 templayer mvpsccopy CONT
3322 and mvpsubcheck
3323
3324 layer mvpsc mvpsccopy
3325 grow 85
3326 shrink 85
3327 shrink 85
3328 grow 85
3329 or mvpsccopy
3330 labels CONT
3331
3332 # Find contacts not covered in
3333 # metal and pull them into the
3334 # next layer up
3335
3336 templayer gencont CONT
3337 and LI
3338 and-not DIFF,TAP
3339 and-not POLY
3340 and-not DIODE
3341 and-not nsubcheck
3342 and-not psubcheck
3343 and-not mvnsubcheck
3344 and-not mvpsubcheck
3345 copyup CONT,LI
3346
3347 templayer barecont CONT
3348 and-not LI
3349 and-not nsubcheck
3350 and-not psubcheck
3351 and-not mvnsubcheck
3352 and-not mvpsubcheck
3353 copyup CONT
3354
3355 layer glass GLASS,PADTXT,PADPIN
3356 labels GLASS
3357 labels PADTXT text
3358 labels PADPIN port
3359
3360 templayer boundary BOUND,STDCELL,PADCELL
3361 boundary
3362
3363 layer comment LVSTEXT
3364 labels LVSTEXT text
3365
3366 layer comment TTEXT
3367 labels TTEXT text
3368
3369 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3370 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3371
3372# MOS Varactor
3373
3374 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3375 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3376 and NPLUS
3377 and NWELL
3378 and-not THKOX
3379 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3380 # NOTE: Else forms a varactor that is not in the vendor netlist.
3381 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3382 labels POLY
3383
3384 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3385 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3386 and NPLUS
3387 and NWELL
3388 and-not THKOX
3389 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3390 labels POLY
3391
3392 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3393 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3394 and NPLUS
3395 and NWELL
3396 and THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3397 labels POLY
3398
3399 calma NWELL 64 20
3400 calma DIFF 65 20
3401 calma DNWELL 64 18
3402 calma PWRES 64 13
3403 calma TAP 65 44
3404 # LVTN
3405 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3406 # HVTR
3407 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3408 # HVTP
3409 calma HVTP 78 44
3410 # SONOS (TUNM)
3411 calma SONOS 80 20
3412 # NPLUS = NSDM
3413 calma NPLUS 93 44
3414 # PPLUS = PSDM
3415 calma PPLUS 94 20
3416 # HVI
3417 calma THKOX 75 20
3418 # NPC
3419 calma NPC 95 20
3420 # P+ POLY MASK
3421 calma RPM 86 20
3422 calma URPM 79 20
3423 calma LDNTM 11 44
3424 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3425 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3426 calma POLYRES 66 13
3427 # Diffusion resistor ID mark
3428 calma DIFFRES 65 13
3429 calma POLY 66 20
3430 calma POLYMOD 66 83
3431 # Diode ID mark
3432 calma DIODE 81 23
3433 # Bipolar NPN mark
3434 calma NPNID 82 20
3435 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3436 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3437 # Capacitor ID
3438 calma CAPID 82 64
3439 # Core area ID mark
3440 calma COREID 81 2
3441 # Standard cell ID mark
3442 calma STDCELL 81 4
3443 # Padframe cell ID mark
3444 calma PADCELL 81 3
3445 # Seal ring ID mark
3446 calma SEALID 81 1
3447 # Low tap density ID mark
3448 calma LOWTAPDENSITY 81 14
3449
3450 # LICON
3451 calma CONT 66 44
3452 calma LI 67 20
3453 calma MCON 67 44
3454
3455 calma MET1 68 20
3456 calma VIA1 68 44
3457 calma MET2 69 20
3458 calma VIA2 69 44
3459 calma MET3 70 20
3460#ifdef METAL5
3461 calma VIA3 70 44
3462 calma MET4 71 20
3463 calma VIA4 71 44
3464 calma MET5 72 20
3465#endif
3466#ifdef REDISTRIBUTION
3467 calma RDL 74 20
3468#endif
3469 calma GLASS 76 20
3470
3471 calma SUBPIN 64 59
3472 calma PADPIN 76 5
3473 calma DIFFPIN 65 6
3474 calma TAPPIN 65 5
3475 calma WELLPIN 64 5
3476 calma LIPIN 67 5
3477 calma POLYPIN 66 5
3478 calma MET1PIN 68 5
3479 calma MET2PIN 69 5
3480 calma MET3PIN 70 5
3481#ifdef METAL5
3482 calma MET4PIN 71 5
3483 calma MET5PIN 72 5
3484#endif
3485#ifdef REDISTRIBUTION
3486 calma RDLPIN 74 5
3487#endif
3488
3489 calma LIRES 67 13
3490 calma MET1RES 68 13
3491 calma MET2RES 69 13
3492 calma MET3RES 70 13
3493#ifdef METAL5
3494 calma MET4RES 71 13
3495 calma MET5RES 72 13
3496#endif
3497
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3498 calma MET1FILL 68 28
3499 calma MET2FILL 69 28
3500 calma MET3FILL 70 28
3501#ifdef METAL5
3502 calma MET4FILL 71 28
3503 calma MET5FILL 72 28
3504#endif
3505
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3506 calma POLYSHORT 66 15
3507 calma LISHORT 67 15
3508 calma MET1SHORT 68 15
3509 calma MET2SHORT 69 15
3510 calma MET3SHORT 70 15
3511#ifdef METAL5
3512 calma MET4SHORT 71 15
3513 calma MET5SHORT 72 15
3514#endif
3515
3516 calma SUBTXT 122 16
3517 calma PADTXT 76 16
3518 calma DIFFTXT 65 16
3519 calma POLYTXT 66 16
3520 calma WELLTXT 64 16
3521 calma LITXT 67 16
3522 calma MET1TXT 68 16
3523 calma MET2TXT 69 16
3524 calma MET3TXT 70 16
3525#ifdef METAL5
3526 calma MET4TXT 71 16
3527 calma MET5TXT 72 16
3528#endif
3529#ifdef REDISTRIBUTION
3530 calma RDLPIN 74 16
3531#endif
3532
3533 calma BOUND 235 4
3534
3535 calma LVSTEXT 83 44
3536
3537#ifdef (MIM)
3538 calma CAPM 89 44
3539 calma CAPM2 97 44
3540#endif (MIM)
3541
3542 calma FILLOBSM1 62 24
3543 calma FILLOBSM2 105 52
3544 calma FILLOBSM3 107 24
3545 calma FILLOBSM4 112 4
3546
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3547#-----------------------------------------------------------------------
3548
3549style vendorimport
3550 scalefactor 10 nanometers
3551 gridlimit 5
3552
3553 options ignore-unknown-layer-labels no-reconnect-labels
3554
3555#ifndef MIM
3556 ignore CAPM
3557 ignore CAPM2
3558#endif (!MIM)
3559#ifndef METAL5
3560 ignore MET4,VIA3
3561 ignore MET5,VIA4
3562#endif
3563 ignore NPC
3564 ignore SEALID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3565 ignore CAPID
3566 ignore LDNTM
3567 ignore HVNTM
3568 ignore POLYMOD
3569 ignore LOWTAPDENSITY
3570
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3571 layer pnp NWELL,WELLTXT,WELLPIN
3572 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3573 labels NWELL
3574 labels WELLTXT port
3575 labels WELLPIN port
3576
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3577 layer nwell NWELL,WELLTXT,WELLPIN
3578 and-not PNPID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3579 labels NWELL
3580 labels WELLTXT port
3581 labels WELLPIN port
3582
3583 layer pwell SUBTXT,SUBPIN
3584 labels SUBTXT port
3585 labels SUBPIN port
3586
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]3587 # Always draw pwell under p-tap
3588 layer pwell TAP
3589 and-not NWELL
3590
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3591 layer dnwell DNWELL
3592 labels DNWELL
3593
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3594 layer npn DNWELL
3595 and-not NWELL
3596 and NPNID
3597
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3598 layer rpw PWRES
3599 and DNWELL
3600 labels PWRES
3601
3602 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
3603 and-not POLY
3604 and-not NWELL
3605 and-not PPLUS
3606 and-not DIODE
3607 and-not DIFFRES
3608 and-not THKOX
3609 and NPLUS
3610 copyup ndifcheck
3611 labels DIFF
3612 labels DIFFTXT port
3613 labels DIFFPIN port
3614 labels TAPPIN port
3615
3616 layer ndiff ndiffarea
3617
3618 # Copy ndiff areas up for contact checks
3619 templayer xndifcheck ndifcheck
3620 copyup ndifcheck
3621
3622 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
3623 and-not POLY
3624 and-not NWELL
3625 and-not PPLUS
3626 and-not DIODE
3627 and-not DIFFRES
3628 and THKOX
3629 and NPLUS
3630 copyup ndifcheck
3631 labels DIFF
3632 labels DIFFTXT port
3633 labels DIFFPIN port
3634
3635 layer mvndiff mvndiffarea
3636
3637 # Copy ndiff areas up for contact checks
3638 templayer mvxndifcheck mvndifcheck
3639 copyup mvndifcheck
3640
3641 layer ndiode DIFF
3642 and NPLUS
3643 and DIODE
3644 and-not NWELL
3645 and-not POLY
3646 and-not PPLUS
3647 and-not THKOX
3648 and-not LVTN
3649 labels DIFF
3650
3651 layer ndiodelvt DIFF
3652 and NPLUS
3653 and DIODE
3654 and-not NWELL
3655 and-not POLY
3656 and-not PPLUS
3657 and-not THKOX
3658 and LVTN
3659 labels DIFF
3660
3661 templayer ndiodearea DIODE
3662 and NPLUS
3663 and-not THKOX
3664 and-not NWELL
3665 copyup DIODE,NPLUS
3666
3667 layer ndiffres DIFFRES
3668 and NPLUS
3669 and-not THKOX
3670 labels DIFF
3671
3672 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
3673 and-not POLY
3674 and NWELL
3675 and-not NPLUS
3676 and-not DIODE
3677 and-not THKOX
3678 and PPLUS
3679 copyup pdifcheck
3680 labels DIFF
3681 labels DIFFTXT port
3682 labels DIFFPIN port
3683
3684 layer pdiff pdiffarea
3685
3686 layer mvndiode DIFF
3687 and NPLUS
3688 and DIODE
3689 and THKOX
3690 and-not POLY
3691 and-not PPLUS
3692 and-not LVTN
3693 labels DIFF
3694
3695 layer nndiode DIFF
3696 and NPLUS
3697 and DIODE
3698 and THKOX
3699 and-not POLY
3700 and-not PPLUS
3701 and LVTN
3702 labels DIFF
3703
3704 templayer mvndiodearea DIODE
3705 and NPLUS
3706 and THKOX
3707 and-not NWELL
3708 copyup DIODE,NPLUS
3709
3710 layer mvndiffres DIFFRES
3711 and NPLUS
3712 and THKOX
3713 labels DIFF
3714
3715 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
3716 and-not POLY
3717 and NWELL
3718 and-not NPLUS
3719 and THKOX
3720 and-not DIODE
3721 and-not DIFFRES
3722 and PPLUS
3723 copyup mvpdifcheck
3724 labels DIFF
3725 labels DIFFTXT port
3726 labels DIFFPIN port
3727
3728 layer mvpdiff mvpdiffarea
3729
3730 # Copy pdiff areas up for contact checks
3731 templayer xpdifcheck pdifcheck
3732 copyup pdifcheck
3733
3734 layer pdiode DIFF
3735 and PPLUS
3736 and-not POLY
3737 and-not NPLUS
3738 and-not THKOX
3739 and-not LVTN
3740 and-not HVTP
3741 and DIODE
3742 labels DIFF
3743
3744 layer pdiodelvt DIFF
3745 and PPLUS
3746 and-not POLY
3747 and-not NPLUS
3748 and-not THKOX
3749 and LVTN
3750 and-not HVTP
3751 and DIODE
3752 labels DIFF
3753
3754 layer pdiodehvt DIFF
3755 and PPLUS
3756 and-not POLY
3757 and-not NPLUS
3758 and-not THKOX
3759 and-not LVTN
3760 and HVTP
3761 and DIODE
3762 labels DIFF
3763
3764 templayer pdiodearea DIODE
3765 and PPLUS
3766 and-not THKOX
3767 copyup DIODE,PPLUS
3768
3769 # Define pfet areas as known pdiff, regardless of the presence of a well.
3770
3771 templayer pfetarea DIFF
3772 and-not NPLUS
3773 and-not THKOX
3774 and POLY
3775
3776 layer pfet pfetarea
3777 and-not LVTN
3778 and-not HVTP
3779 and-not STDCELL
3780 and-not COREID
3781 labels DIFF
3782
3783 layer scpfet pfetarea
3784 and-not LVTN
3785 and-not HVTP
3786 and STDCELL
3787 labels DIFF
3788
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3789 layer scpfethvt pfetarea
3790 and-not LVTN
3791 and HVTP
3792 and STDCELL
3793 labels DIFF
3794
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3795 layer ppu pfetarea
3796 and-not LVTN
Tim Edwards94513d42020-11-15 22:07:34 -0500[diff] [blame]3797 and HVTP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3798 and COREID
3799 labels DIFF
3800
3801 layer pfetlvt pfetarea
3802 and LVTN
3803 labels DIFF
3804
3805 layer pfetmvt pfetarea
3806 and HVTR
3807 labels DIFF
3808
3809 layer pfethvt pfetarea
3810 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3811 and-not STDCELL
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]3812 and-not COREID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3813 labels DIFF
3814
3815 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
3816 layer nwell pfetarea
3817 grow 180
3818
3819 # Copy mvpdiff areas up for contact checks
3820 templayer mvxpdifcheck mvpdifcheck
3821 copyup mvpdifcheck
3822
3823 layer mvpdiode DIFF
3824 and PPLUS
3825 and-not POLY
3826 and-not NPLUS
3827 and THKOX
3828 and DIODE
3829 labels DIFF
3830
3831 templayer mvpdiodearea DIODE
3832 and PPLUS
3833 and THKOX
3834 copyup DIODE,PPLUS
3835
3836 # Define pfet areas as known pdiff,
3837 # regardless of the presence of a
3838 # well.
3839
3840 templayer mvpfetarea DIFF
3841 and-not NPLUS
3842 and THKOX
3843 and POLY
3844
3845 layer mvpfet mvpfetarea
3846 labels DIFF
3847
3848 layer pdiff DIFF,DIFFTXT,DIFFPIN
3849 and-not NPLUS
3850 and-not POLY
3851 and-not THKOX
3852 and-not DIODE
3853 and-not DIFFRES
3854 labels DIFF
3855 labels DIFFTXT port
3856 labels DIFFPIN port
3857
3858 layer pdiffres DIFFRES
3859 and PPLUS
3860 and NWELL
3861 and-not THKOX
3862 labels DIFF
3863
3864 layer nfet DIFF
3865 and POLY
3866 and-not PPLUS
3867 and NPLUS
3868 and-not THKOX
3869 and-not LVTN
3870 and-not SONOS
3871 and-not STDCELL
3872 labels DIFF
3873
3874 layer scnfet DIFF
3875 and POLY
3876 and-not PPLUS
3877 and NPLUS
3878 and-not NWELL
3879 and-not THKOX
3880 and-not LVTN
3881 and-not SONOS
3882 and STDCELL
3883 labels DIFF
3884
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]3885 layer npass DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3886 and POLY
3887 and-not PPLUS
3888 and NPLUS
3889 and-not NWELL
3890 and COREID
3891 labels DIFF
3892
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]3893 layer npd DIFF
3894 and POLY
3895 and-not PPLUS
3896 and NPLUS
3897 and-not NWELL
3898 and COREID
3899 # Shrink-grow operation eliminates the smaller npass device
3900 shrink 70
3901 grow 70
3902 labels DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3903
3904 layer nfetlvt DIFF
3905 and POLY
3906 and-not PPLUS
3907 and NPLUS
3908 and-not THKOX
3909 and LVTN
3910 and-not SONOS
3911 labels DIFF
3912
3913 layer nsonos DIFF
3914 and POLY
3915 and-not PPLUS
3916 and NPLUS
3917 and-not THKOX
3918 and LVTN
3919 and SONOS
3920 labels DIFF
3921
3922 templayer nsdarea TAP
3923 and NPLUS
3924 and NWELL
3925 and-not POLY
3926 and-not PPLUS
3927 and-not THKOX
3928 copyup nsubcheck
3929
3930 layer nsd nsdarea
3931 labels TAP
3932
3933 layer nsd TAP,TAPPIN
3934 and NPLUS
3935 and-not POLY
3936 and-not THKOX
3937 labels TAP
3938 labels TAPPIN port
3939
3940 templayer nsdexpand nsdarea
3941 grow 500
3942
3943 # Copy nsub areas up for contact checks
3944 templayer xnsubcheck nsubcheck
3945 copyup nsubcheck
3946
3947 templayer psdarea TAP
3948 and PPLUS
3949 and-not NWELL
3950 and-not POLY
3951 and-not NPLUS
3952 and-not THKOX
3953 and-not pfetexpand
3954 copyup psubcheck
3955
3956 layer psd psdarea
3957 labels TAP
3958
3959 layer psd TAP,TAPPIN
3960 and PPLUS
3961 and-not POLY
3962 and-not THKOX
3963 labels TAP
3964 labels TAPPIN port
3965
3966 templayer psdexpand psdarea
3967 grow 500
3968
3969 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
3970 and-not NPLUS
3971 and-not POLY
3972 and THKOX
3973 and mvpfetexpand
3974 labels DIFF
3975 labels DIFFTXT port
3976 labels DIFFPIN port
3977
3978 layer mvpdiffres DIFFRES
3979 and PPLUS
3980 and NWELL
3981 and THKOX
3982 and-not mvrdpioedge
3983 labels DIFF
3984
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3985 templayer mvnfetarea DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3986 and POLY
3987 and-not PPLUS
3988 and NPLUS
3989 and-not LVTN
3990 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3991 grow 1000
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3992
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3993 templayer mvnnfetarea DIFF,TAP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3994 and POLY
3995 and-not PPLUS
3996 and NPLUS
3997 and LVTN
3998 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3999 and-not mvnfetarea
4000
4001 layer mvnfet DIFF
4002 and POLY
4003 and-not PPLUS
4004 and NPLUS
4005 and THKOX
4006 and-not mvnnfetarea
4007 labels DIFF
4008
4009 layer mvnnfet mvnnfetarea
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4010 labels DIFF
4011
4012 templayer mvnsdarea TAP
4013 and NPLUS
4014 and NWELL
4015 and-not POLY
4016 and-not PPLUS
4017 and THKOX
4018 copyup mvnsubcheck
4019
4020 layer mvnsd mvnsdarea
4021 labels TAP
4022
4023 layer mvnsd TAP,TAPPIN
4024 and NPLUS
4025 and THKOX
4026 labels TAP
4027 labels TAPPIN port
4028
4029 templayer mvnsdexpand mvnsdarea
4030 grow 500
4031
4032 # Copy nsub areas up for contact checks
4033 templayer mvxnsubcheck mvnsubcheck
4034 copyup mvnsubcheck
4035
4036 templayer mvpsdarea DIFF
4037 and PPLUS
4038 and-not NWELL
4039 and-not POLY
4040 and-not NPLUS
4041 and THKOX
4042 and-not mvpfetexpand
4043 copyup mvpsubcheck
4044
4045 layer mvpsd mvpsdarea
4046 labels DIFF
4047
4048 layer mvpsd TAP,TAPPIN
4049 and PPLUS
4050 and THKOX
4051 labels TAP
4052 labels TAPPIN port
4053
4054 templayer mvpsdexpand mvpsdarea
4055 grow 500
4056
4057 # Copy psub areas up for contact checks
4058 templayer xpsubcheck psubcheck
4059 copyup psubcheck
4060
4061 templayer mvxpsubcheck mvpsubcheck
4062 copyup mvpsubcheck
4063
4064 layer psd TAP
4065 and-not PPLUS
4066 and-not NPLUS
4067 and-not POLY
4068 and-not THKOX
4069 and-not pfetexpand
4070 and psdexpand
4071
4072 layer nsd TAP
4073 and-not PPLUS
4074 and-not NPLUS
4075 and-not POLY
4076 and-not THKOX
4077 and nsdexpand
4078
4079 layer mvpsd TAP
4080 and-not PPLUS
4081 and-not NPLUS
4082 and-not POLY
4083 and THKOX
4084 and-not mvpfetexpand
4085 and mvpsdexpand
4086
4087 layer mvnsd TAP
4088 and-not PPLUS
4089 and-not NPLUS
4090 and-not POLY
4091 and THKOX
4092 and mvnsdexpand
4093
4094 templayer hresarea POLY
4095 and RPM
4096 grow 3000
4097
4098 templayer uresarea POLY
4099 and URPM
4100 grow 3000
4101
4102 templayer diffresarea DIFFRES
4103 and-not THKOX
4104 grow 3000
4105
4106 templayer mvdiffresarea DIFFRES
4107 and THKOX
4108 grow 3000
4109
4110 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
4111
4112 layer pfet POLY
4113 and DIFF
4114 and diffresarea
4115 and-not NPLUS
4116 and-not STDCELL
4117
4118 layer scpfet POLY
4119 and DIFF
4120 and diffresarea
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]4121 and-not HVTP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4122 and-not NPLUS
4123 and STDCELL
4124
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4125 layer scpfethvt POLY
4126 and DIFF
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4127 and diffresarea
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]4128 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4129 and-not NPLUS
4130 and STDCELL
4131
4132 templayer xpolyterm RPM,URPM
4133 and POLY
4134 and-not POLYRES
4135 # add back the 0.06um contact surround in the direction of the resistor
4136 grow 60
4137 and POLY
4138
4139 layer xpc xpolyterm
4140
4141 templayer polyarea POLY
4142 and-not POLYRES
4143 and-not POLYSHORT
4144 and-not DIFF
4145 and-not RPM
4146 and-not URPM
4147 copyup polycheck
4148
4149 layer poly polyarea,POLYTXT,POLYPIN
4150 labels POLY
4151 labels POLYTXT port
4152 labels POLYPIN port
4153
4154 # Copy (non-resistor) poly areas up for contact checks
4155 templayer xpolycheck polycheck
4156 copyup polycheck
4157
4158 layer mrp1 POLY
4159 and POLYRES
4160 and-not RPM
4161 and-not URPM
4162 labels POLY
4163
4164 layer rmp POLY
4165 and POLYSHORT
4166 labels POLY
4167
4168 layer xhrpoly POLY
4169 and POLYRES
4170 and RPM
4171 and-not URPM
4172 and PPLUS
4173 and NPC
4174 and-not xpolyterm
4175 labels POLY
4176
4177 layer uhrpoly POLY
4178 and POLYRES
4179 and URPM
4180 and-not RPM
4181 and NPC
4182 and-not xpolyterm
4183 labels POLY
4184
4185 templayer ndcbase CONT
4186 and DIFF
4187 and NPLUS
4188 and-not NWELL
4189 and LI
4190 and-not THKOX
4191
4192 layer ndc ndcbase
4193 grow 85
4194 shrink 85
4195 shrink 85
4196 grow 85
4197 or ndcbase
4198 labels CONT
4199
4200 templayer nscbase CONT
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4201 and DIFF,TAP
4202 and NPLUS
4203 and NWELL
4204 and LI
4205 and-not THKOX
4206
4207 layer nsc nscbase
4208 grow 85
4209 shrink 85
4210 shrink 85
4211 grow 85
4212 or nscbase
4213 labels CONT
4214
4215 templayer pdcbase CONT
4216 and DIFF
4217 and PPLUS
4218 and NWELL
4219 and LI
4220 and-not THKOX
4221
4222 layer pdc pdcbase
4223 grow 85
4224 shrink 85
4225 shrink 85
4226 grow 85
4227 or pdcbase
4228 labels CONT
4229
4230 templayer pdcnowell CONT
4231 and DIFF
4232 and PPLUS
4233 and pfetexpand
4234 and LI
4235 and-not THKOX
4236
4237 layer pdc pdcnowell
4238 grow 85
4239 shrink 85
4240 shrink 85
4241 grow 85
4242 or pdcnowell
4243 labels CONT
4244
4245 templayer pscbase CONT
4246 and DIFF,TAP
4247 and PPLUS
4248 and-not NWELL
4249 and-not pfetexpand
4250 and LI
4251 and-not THKOX
4252
4253 layer psc pscbase
4254 grow 85
4255 shrink 85
4256 shrink 85
4257 grow 85
4258 or pscbase
4259 labels CONT
4260
4261 templayer pcbase CONT
4262 and POLY
4263 and-not DIFF
4264 and-not RPM,URPM
4265 and LI
4266
4267 layer pc pcbase
4268 grow 85
4269 shrink 85
4270 shrink 85
4271 grow 85
4272 or pcbase
4273 labels CONT
4274
4275 templayer ndicbase CONT
4276 and DIFF
4277 and NPLUS
4278 and DIODE
4279 and-not POLY
4280 and-not PPLUS
4281 and-not THKOX
4282 and-not LVTN
4283
4284 layer ndic ndicbase
4285 grow 85
4286 shrink 85
4287 shrink 85
4288 grow 85
4289 or ndicbase
4290 labels CONT
4291
4292 templayer ndilvtcbase CONT
4293 and DIFF
4294 and NPLUS
4295 and DIODE
4296 and-not POLY
4297 and-not PPLUS
4298 and-not THKOX
4299 and LVTN
4300
4301 layer ndilvtc ndilvtcbase
4302 grow 85
4303 shrink 85
4304 shrink 85
4305 grow 85
4306 or ndilvtcbase
4307 labels CONT
4308
4309 templayer pdicbase CONT
4310 and DIFF
4311 and PPLUS
4312 and DIODE
4313 and-not POLY
4314 and-not NPLUS
4315 and-not THKOX
4316 and-not LVTN
4317 and-not HVTP
4318
4319 layer pdic pdicbase
4320 grow 85
4321 shrink 85
4322 shrink 85
4323 grow 85
4324 or pdicbase
4325 labels CONT
4326
4327 templayer pdilvtcbase CONT
4328 and DIFF
4329 and PPLUS
4330 and DIODE
4331 and-not POLY
4332 and-not NPLUS
4333 and-not THKOX
4334 and LVTN
4335 and-not HVTP
4336
4337 layer pdilvtc pdilvtcbase
4338 grow 85
4339 shrink 85
4340 shrink 85
4341 grow 85
4342 or pdilvtcbase
4343 labels CONT
4344
4345 templayer pdihvtcbase CONT
4346 and DIFF
4347 and PPLUS
4348 and DIODE
4349 and-not POLY
4350 and-not NPLUS
4351 and-not THKOX
4352 and-not LVTN
4353 and HVTP
4354
4355 layer pdihvtc pdihvtcbase
4356 grow 85
4357 shrink 85
4358 shrink 85
4359 grow 85
4360 or pdihvtcbase
4361 labels CONT
4362
4363 templayer mvndcbase CONT
4364 and DIFF
4365 and NPLUS
4366 and-not NWELL
4367 and LI
4368 and THKOX
4369
4370 layer mvndc mvndcbase
4371 grow 85
4372 shrink 85
4373 shrink 85
4374 grow 85
4375 or mvndcbase
4376 labels CONT
4377
4378 templayer mvnscbase CONT
4379 and DIFF,TAP
4380 and NPLUS
4381 and NWELL
4382 and LI
4383 and THKOX
4384
4385 layer mvnsc mvnscbase
4386 grow 85
4387 shrink 85
4388 shrink 85
4389 grow 85
4390 or mvnscbase
4391 labels CONT
4392
4393 templayer mvpdcbase CONT
4394 and DIFF
4395 and PPLUS
4396 and NWELL
4397 and LI
4398 and THKOX
4399
4400 layer mvpdc mvpdcbase
4401 grow 85
4402 shrink 85
4403 shrink 85
4404 grow 85
4405 or mvpdcbase
4406 labels CONT
4407
4408 templayer mvpdcnowell CONT
4409 and DIFF
4410 and PPLUS
4411 and mvpfetexpand
4412 and MET1
4413 and THKOX
4414
4415 layer mvpdc mvpdcnowell
4416 grow 85
4417 shrink 85
4418 shrink 85
4419 grow 85
4420 or mvpdcnowell
4421 labels CONT
4422
4423 templayer mvpscbase CONT
4424 and DIFF,TAP
4425 and PPLUS
4426 and-not NWELL
4427 and-not mvpfetexpand
4428 and LI
4429 and THKOX
4430
4431 layer mvpsc mvpscbase
4432 grow 85
4433 shrink 85
4434 shrink 85
4435 grow 85
4436 or mvpscbase
4437 labels CONT
4438
4439 templayer mvndicbase CONT
4440 and DIFF
4441 and NPLUS
4442 and DIODE
4443 and-not POLY
4444 and-not PPLUS
4445 and-not LVTN
4446 and THKOX
4447
4448 layer mvndic mvndicbase
4449 grow 85
4450 shrink 85
4451 shrink 85
4452 grow 85
4453 or mvndicbase
4454 labels CONT
4455
4456 templayer nndicbase CONT
4457 and DIFF
4458 and NPLUS
4459 and DIODE
4460 and-not POLY
4461 and-not PPLUS
4462 and LVTN
4463 and THKOX
4464
4465 layer nndic nndicbase
4466 grow 85
4467 shrink 85
4468 shrink 85
4469 grow 85
4470 or nndicbase
4471 labels CONT
4472
4473 templayer mvpdicbase CONT
4474 and DIFF
4475 and PPLUS
4476 and DIODE
4477 and-not POLY
4478 and-not NPLUS
4479 and THKOX
4480
4481 layer mvpdic mvpdicbase
4482 grow 85
4483 shrink 85
4484 shrink 85
4485 grow 85
4486 or mvpdicbase
4487 labels CONT
4488
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4489 layer coreli LI,LITXT,LIPIN
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4490 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4491 and COREID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4492 labels LI
4493 labels LITXT port
4494 labels LIPIN port
4495
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4496 layer locali LI,LITXT,LIPIN
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4497 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4498 and-not COREID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4499 labels LI
4500 labels LITXT port
4501 labels LIPIN port
4502
4503 layer rli LI
4504 and LIRES,LISHORT
4505 labels LIRES,LISHORT
4506
4507 layer lic MCON
4508 grow 95
4509 shrink 95
4510 shrink 85
4511 grow 85
4512 or MCON
4513 labels MCON
4514
4515 layer m1 MET1,MET1TXT,MET1PIN
4516 and-not MET1RES,MET1SHORT
4517 labels MET1
4518 labels MET1TXT port
4519 labels MET1PIN port
4520
4521 layer rm1 MET1
4522 and MET1RES,MET1SHORT
4523 labels MET1RES,MET1SHORT
4524
4525 layer m1fill MET1FILL
4526 labels MET1FILL
4527
4528#ifdef MIM
4529 layer mimcap MET3
4530 and CAPM
4531 labels CAPM
4532
4533 layer mimcc VIA3
4534 and CAPM
4535 grow 60
4536 grow 40
4537 shrink 40
4538 labels CAPM
4539
4540 layer mimcap2 MET4
4541 and CAPM2
4542 labels CAPM2
4543
4544 layer mim2cc VIA4
4545 and CAPM2
4546 grow 190
4547 grow 210
4548 shrink 210
4549 labels CAPM2
4550
4551#endif (MIM)
4552
4553 templayer m2cbase VIA1
4554 grow 55
4555
4556 layer m2c m2cbase
4557 grow 30
4558 shrink 30
4559 shrink 130
4560 grow 130
4561 or m2cbase
4562
4563 layer m2 MET2,MET2TXT,MET2PIN
4564 and-not MET2RES,MET2SHORT
4565 labels MET2
4566 labels MET2TXT port
4567 labels MET2PIN port
4568
4569 layer rm2 MET2
4570 and MET2RES,MET2SHORT
4571 labels MET2RES,MET2SHORT
4572
4573 layer m2fill MET2FILL
4574 labels MET2FILL
4575
4576 templayer m3cbase VIA2
4577 grow 40
4578
4579 layer m3c m3cbase
4580 grow 60
4581 shrink 60
4582 shrink 140
4583 grow 140
4584 or m3cbase
4585
4586 layer m3 MET3,MET3TXT,MET3PIN
4587 and-not MET3RES,MET3SHORT
4588#ifdef MIM
4589 and-not CAPM
4590#endif (MIM)
4591 labels MET3
4592 labels MET3TXT port
4593 labels MET3PIN port
4594
4595 layer rm3 MET3
4596 and MET3RES,MET3SHORT
4597 labels MET3RES,MET3SHORT
4598
4599 layer m3fill MET3FILL
4600 labels MET3FILL
4601
4602#ifdef (METAL5)
4603
4604 templayer via3base VIA3
4605#ifdef MIM
4606 and-not CAPM
4607#endif (MIM)
4608 grow 60
4609
4610 layer via3 via3base
4611 grow 40
4612 shrink 40
4613 shrink 160
4614 grow 160
4615 or via3base
4616
4617 layer m4 MET4,MET4TXT,MET4PIN
4618 and-not MET4RES,MET4SHORT
4619#ifdef MIM
4620 and-not CAPM2
4621#endif (MIM)
4622 labels MET4
4623 labels MET4TXT port
4624 labels MET4PIN port
4625
4626 layer rm4 MET4
4627 and MET4RES,MET4SHORT
4628 labels MET4RES,MET4SHORT
4629
4630 layer m4fill MET4FILL
4631 labels MET4FILL
4632
4633 layer m5 MET5,MET5TXT,MET5PIN
4634 and-not MET5RES,MET5SHORT
4635 labels MET5
4636 labels MET5TXT port
4637 labels MET5PIN port
4638
4639 layer rm5 MET5
4640 and MET5RES,MET5SHORT
4641 labels MET5RES,MET5SHORT
4642
4643 layer m5fill MET5FILL
4644 labels MET5FILL
4645
4646 templayer via4base VIA4
4647#ifdef MIM
4648 and-not CAPM2
4649#endif (MIM)
4650 grow 190
4651
4652 layer via4 via4base
4653 grow 210
4654 shrink 210
4655 shrink 590
4656 grow 590
4657 or via4base
4658#endif (METAL5)
4659
4660#ifdef REDISTRIBUTION
4661 layer metrdl RDL,RDLTXT,RDLPIN
4662 labels RDL
4663 labels RDLTXT port
4664 labels RDLPIN port
4665#endif
4666
4667 # Find diffusion not covered in
4668 # NPLUS or PPLUS and pull it into
4669 # the next layer up
4670
4671 templayer gentrans DIFF
4672 and-not PPLUS
4673 and-not NPLUS
4674 and POLY
4675 copyup DIFF,POLY
4676
4677 templayer gendiff DIFF,TAP
4678 and-not PPLUS
4679 and-not NPLUS
4680 and-not POLY
4681 copyup DIFF
4682
4683 # Handle contacts found by copyup
4684
4685 templayer ndiccopy CONT
4686 and LI
4687 and DIODE
4688 and NPLUS
4689 and-not THKOX
4690
4691 layer ndic ndiccopy
4692 grow 85
4693 shrink 85
4694 shrink 85
4695 grow 85
4696 or ndiccopy
4697 labels CONT
4698
4699 templayer mvndiccopy CONT
4700 and LI
4701 and DIODE
4702 and NPLUS
4703 and THKOX
4704
4705 layer mvndic mvndiccopy
4706 grow 85
4707 shrink 85
4708 shrink 85
4709 grow 85
4710 or mvndiccopy
4711 labels CONT
4712
4713 templayer pdiccopy CONT
4714 and LI
4715 and DIODE
4716 and PPLUS
4717 and-not THKOX
4718
4719 layer pdic pdiccopy
4720 grow 85
4721 shrink 85
4722 shrink 85
4723 grow 85
4724 or pdiccopy
4725 labels CONT
4726
4727 templayer mvpdiccopy CONT
4728 and LI
4729 and DIODE
4730 and PPLUS
4731 and THKOX
4732
4733 layer mvpdic mvpdiccopy
4734 grow 85
4735 shrink 85
4736 shrink 85
4737 grow 85
4738 or mvpdiccopy
4739 labels CONT
4740
4741 templayer ndccopy CONT
4742 and ndifcheck
4743
4744 layer ndc ndccopy
4745 grow 85
4746 shrink 85
4747 shrink 85
4748 grow 85
4749 or ndccopy
4750 labels CONT
4751
4752 templayer mvndccopy CONT
4753 and mvndifcheck
4754
4755 layer mvndc mvndccopy
4756 grow 85
4757 shrink 85
4758 shrink 85
4759 grow 85
4760 or mvndccopy
4761 labels CONT
4762
4763 templayer pdccopy CONT
4764 and pdifcheck
4765
4766 layer pdc pdccopy
4767 grow 85
4768 shrink 85
4769 shrink 85
4770 grow 85
4771 or pdccopy
4772 labels CONT
4773
4774 templayer mvpdccopy CONT
4775 and mvpdifcheck
4776
4777 layer mvpdc mvpdccopy
4778 grow 85
4779 shrink 85
4780 shrink 85
4781 grow 85
4782 or mvpdccopy
4783 labels CONT
4784
4785 templayer pccopy CONT
4786 and polycheck
4787
4788 layer pc pccopy
4789 grow 85
4790 shrink 85
4791 shrink 85
4792 grow 85
4793 or pccopy
4794 labels CONT
4795
4796 templayer nsccopy CONT
4797 and nsubcheck
4798
4799 layer nsc nsccopy
4800 grow 85
4801 shrink 85
4802 shrink 85
4803 grow 85
4804 or nsccopy
4805 labels CONT
4806
4807 templayer mvnsccopy CONT
4808 and mvnsubcheck
4809
4810 layer mvnsc mvnsccopy
4811 grow 85
4812 shrink 85
4813 shrink 85
4814 grow 85
4815 or mvnsccopy
4816 labels CONT
4817
4818 templayer psccopy CONT
4819 and psubcheck
4820
4821 layer psc psccopy
4822 grow 85
4823 shrink 85
4824 shrink 85
4825 grow 85
4826 or psccopy
4827 labels CONT
4828
4829 templayer mvpsccopy CONT
4830 and mvpsubcheck
4831
4832 layer mvpsc mvpsccopy
4833 grow 85
4834 shrink 85
4835 shrink 85
4836 grow 85
4837 or mvpsccopy
4838 labels CONT
4839
4840 # Find contacts not covered in
4841 # metal and pull them into the
4842 # next layer up
4843
4844 templayer gencont CONT
4845 and LI
4846 and-not DIFF,TAP
4847 and-not POLY
4848 and-not DIODE
4849 and-not nsubcheck
4850 and-not psubcheck
4851 and-not mvnsubcheck
4852 and-not mvpsubcheck
4853 copyup CONT,LI
4854
4855 templayer barecont CONT
4856 and-not LI
4857 and-not nsubcheck
4858 and-not psubcheck
4859 and-not mvnsubcheck
4860 and-not mvpsubcheck
4861 copyup CONT
4862
4863 layer glass GLASS,PADTXT,PADPIN
4864 labels GLASS
4865 labels PADTXT port
4866 labels PADPIN port
4867
4868 templayer boundary BOUND,STDCELL,PADCELL
4869 boundary
4870
4871 layer comment LVSTEXT
4872 labels LVSTEXT text
4873
4874 layer comment TTEXT
4875 labels TTEXT text
4876
4877 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4878 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4879
4880# MOS Varactor
4881
4882 layer var POLY
4883 and TAP
4884 and NPLUS
4885 and NWELL
4886 and-not THKOX
4887 and-not HVTP
4888 # NOTE: Else forms a varactor that is not in the vendor netlist.
4889 and-not COREID
4890 labels POLY
4891
4892 layer varhvt POLY
4893 and TAP
4894 and NPLUS
4895 and NWELL
4896 and-not THKOX
4897 and HVTP
4898 labels POLY
4899
4900 layer mvvar POLY
4901 and TAP
4902 and NPLUS
4903 and NWELL
4904 and THKOX
4905 labels POLY
4906
4907 calma NWELL 64 20
4908 calma DIFF 65 20
4909 calma DNWELL 64 18
4910 calma PWRES 64 13
4911 calma TAP 65 44
4912 # LVTN
4913 calma LVTN 125 44
4914 # HVTR
4915 calma HVTR 18 20
4916 # HVTP
4917 calma HVTP 78 44
4918 # SONOS (TUNM)
4919 calma SONOS 80 20
4920 # NPLUS = NSDM
4921 calma NPLUS 93 44
4922 # PPLUS = PSDM
4923 calma PPLUS 94 20
4924 # HVI
4925 calma THKOX 75 20
4926 # NPC
4927 calma NPC 95 20
4928 # P+ POLY MASK
4929 calma RPM 86 20
4930 calma URPM 79 20
4931 calma LDNTM 11 44
4932 calma HVNTM 125 20
Tim Edwards3360b9e2020-09-16 11:45:19 -0400[diff] [blame]4933 # Poly resistor ID mark
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4934 calma POLYRES 66 13
4935 # Diffusion resistor ID mark
4936 calma DIFFRES 65 13
4937 calma POLY 66 20
4938 calma POLYMOD 66 83
4939 # Diode ID mark
4940 calma DIODE 81 23
4941 # Bipolar NPN mark
4942 calma NPNID 82 20
4943 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]4944 calma PNPID 82 44
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4945 # Capacitor ID
4946 calma CAPID 82 64
4947 # Core area ID mark
4948 calma COREID 81 2
4949 # Standard cell ID mark
4950 calma STDCELL 81 4
4951 # Padframe cell ID mark
4952 calma PADCELL 81 3
4953 # Seal ring ID mark
4954 calma SEALID 81 1
4955 # Low tap density ID mark
4956 calma LOWTAPDENSITY 81 14
4957
4958 # LICON
4959 calma CONT 66 44
4960 calma LI 67 20
4961 calma MCON 67 44
4962
4963 calma MET1 68 20
4964 calma VIA1 68 44
4965 calma MET2 69 20
4966 calma VIA2 69 44
4967 calma MET3 70 20
4968#ifdef METAL5
4969 calma VIA3 70 44
4970 calma MET4 71 20
4971 calma VIA4 71 44
4972 calma MET5 72 20
4973#endif
4974#ifdef REDISTRIBUTION
4975 calma RDL 74 20
4976#endif
4977 calma GLASS 76 20
4978
4979 calma SUBPIN 64 59
4980 calma PADPIN 76 5
4981 calma DIFFPIN 65 6
4982 calma TAPPIN 65 5
4983 calma WELLPIN 64 5
4984 calma LIPIN 67 5
4985 calma POLYPIN 66 5
4986 calma MET1PIN 68 5
4987 calma MET2PIN 69 5
4988 calma MET3PIN 70 5
4989#ifdef METAL5
4990 calma MET4PIN 71 5
4991 calma MET5PIN 72 5
4992#endif
4993#ifdef REDISTRIBUTION
4994 calma RDLPIN 74 5
4995#endif
4996
4997 calma LIRES 67 13
4998 calma MET1RES 68 13
4999 calma MET2RES 69 13
5000 calma MET3RES 70 13
5001#ifdef METAL5
5002 calma MET4RES 71 13
5003 calma MET5RES 72 13
5004#endif
5005
5006 calma MET1FILL 68 28
5007 calma MET2FILL 69 28
5008 calma MET3FILL 70 28
5009#ifdef METAL5
5010 calma MET4FILL 71 28
5011 calma MET5FILL 72 28
5012#endif
5013
5014 calma POLYSHORT 66 15
5015 calma LISHORT 67 15
5016 calma MET1SHORT 68 15
5017 calma MET2SHORT 69 15
5018 calma MET3SHORT 70 15
5019#ifdef METAL5
5020 calma MET4SHORT 71 15
5021 calma MET5SHORT 72 15
5022#endif
5023
5024 calma SUBTXT 122 16
5025 calma PADTXT 76 16
5026 calma DIFFTXT 65 16
5027 calma POLYTXT 66 16
5028 calma WELLTXT 64 16
5029 calma LITXT 67 16
5030 calma MET1TXT 68 16
5031 calma MET2TXT 69 16
5032 calma MET3TXT 70 16
5033#ifdef METAL5
5034 calma MET4TXT 71 16
5035 calma MET5TXT 72 16
5036#endif
5037#ifdef REDISTRIBUTION
5038 calma RDLPIN 74 16
5039#endif
5040
5041 calma BOUND 235 4
5042
5043 calma LVSTEXT 83 44
5044
5045#ifdef (MIM)
5046 calma CAPM 89 44
5047 calma CAPM2 97 44
5048#endif (MIM)
5049
5050 calma FILLOBSM1 62 24
5051 calma FILLOBSM2 105 52
5052 calma FILLOBSM3 107 24
5053 calma FILLOBSM4 112 4
5054
5055end
5056
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5057#-----------------------------------------------------
5058# Digital flow maze router cost parameters
5059#-----------------------------------------------------
5060
5061mzrouter
5062end
5063
5064#-----------------------------------------------------
5065# Vendor DRC rules
5066#-----------------------------------------------------
5067
5068drc
5069
5070 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5071 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5072 cifstyle drc
5073
5074 variants (fast),(full)
5075
5076#-----------------------------
5077# DNWELL
5078#-----------------------------
5079
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5080 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
5081 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5082 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5083 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5084
5085 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5086 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5087 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5088 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5089 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5090
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5091 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
5092 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5093 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5094
5095#-----------------------------
5096# NWELL
5097#-----------------------------
5098
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5099 width allnwell 840 "N-well width < %d (nwell.1)"
5100 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5101
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5102 variants (full)
5103 cifmaxwidth nwell_missing_tap 0 bend_illegal \
5104 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]5105
5106 cifspacing mvnwell lvnwell 2000 touching_illegal \
5107 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
5108 cifspacing mvnwell mvnwell 2000 touching_ok \
5109 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5110 variants (fast),(full)
5111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5112#-----------------------------
5113# DIFF
5114#-----------------------------
5115
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5116 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5117 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5118 width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5119 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5120
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5121 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
5122 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
5123 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
5124 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
5125 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
5126 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5127 spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5128 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5129 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5130 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5131 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5132 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5133 spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5134 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5135 spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5136 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5137 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5138 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5139 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5140 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5141 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5142 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5143 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5144 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5145 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5146 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5147 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5148 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5149 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5150 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5151 surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5152 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5153 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5154 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5155 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5156 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]5157
5158variants (full)
5159 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
5160 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
5161variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5162
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5163 spacing allnfets allpactivenonfet 270 touching_illegal \
5164 "nFET cannot abut P-diffusion (diff/tap.3)"
5165 spacing allpfets allnactivenonfet 270 touching_illegal \
5166 "pFET cannot abut N-diffusion (diff/tap.3)"
5167
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5168 # Butting junction rules
5169 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5170 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5171 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5172 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5173 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5174 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5175 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5176 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5177
5178 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5179 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5180 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5181 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5182 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5183 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5184 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5185 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
5186
5187 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5188 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
5189 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
5190
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]5191 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
5192 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
5193
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5194 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5195
5196 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]5197 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5198
5199 # Latchup rules
5200 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5201 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5202 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5203 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5204 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5205 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5206
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5207 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5208
5209#-----------------------------
5210# POLY
5211#-----------------------------
5212
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5213 width allpoly 150 "poly width < %d (poly.1a)"
5214 spacing allpoly allpoly 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5215
5216 spacing allpolynonfet \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]5217 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5218 75 corner_ok allfets \
5219 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5220 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5221 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5222 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5223 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5224 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5225 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
5226 overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5227 overhang *poly allfets 130 "poly overhang of transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5228 rect_only allfets "No bends in transistors (poly.11)"
5229 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5230 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5231 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5232 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5233 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5234
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5235 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
5236 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
5237 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
5238 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
5239 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
5240 "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
5241
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5242 angles allpoly 90 "Only 90 degree angles permitted on poly (x.2)"
5243
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5244#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5245# HVTP
5246#--------------------------------------------------------------------
5247
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5248 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5249 360 touching_illegal \
5250 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
5251
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5252 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5253 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
5254
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5255#--------------------------------------------------------------------
5256# LVTN
5257#--------------------------------------------------------------------
5258
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5259 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
5260 allfetsnolvt 360 touching_illegal \
5261 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5262
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5263 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5264 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5265 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5266
5267 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5268 edge4way allfetsnolvt allactivenonfet 415 \
5269 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
5270 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5271
5272#--------------------------------------------------------------------
5273# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5274#--------------------------------------------------------------------
5275
5276# Layer NPC is defined automatically around poly contacts (grow 0.1um)
5277
5278#--------------------------------------------------------------------
5279# CONT (LICON, contact between poly/diff and LI)
5280#--------------------------------------------------------------------
5281
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5282 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
5283 width nsc/li 170 "N-tap contact width < %d (licon.1)"
5284 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
5285 width psc/li 170 "P-tap contact width < %d (licon.1)"
5286 width ndic/li 170 "N-diode contact width < %d (licon.1)"
5287 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5288 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5289
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5290 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
5291 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
5292 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5293
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5294 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
5295 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
5296 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
5297 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
5298 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
5299 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5300
5301 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5302 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5303 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5304 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5305 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5306 "Diffusion contact spacing < %d (licon.2)"
5307 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5308
5309 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5310 "poly contact spacing to diffusion < %d (licon.14)"
5311 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
5312 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5313
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5314 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5315 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5316 spacing ndc,pdc scnfet,npd,npass,scpfet,scpfethvt,ppu 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5317 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5318 spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5319 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5320 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5321 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5322 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5323 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5324
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5325 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5326 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5327 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
5328 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5329 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5330 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5331 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5332 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5333 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5334
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5335 spacing psc/a allnactivenontap 60 touching_illegal \
5336 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
5337 spacing nsc/a allpactivenontap 60 touching_illegal \
5338 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
5339
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5340 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5341 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5342 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
5343 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5344 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5345 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5346 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5347 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5348 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5349
5350 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5351 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5352 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5353 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5354
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5355 surround mvndc/a *mvndiff,mvnfet,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5356 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5357 surround mvpdc/a *mvpdiff,mvpfet,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5358 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5359 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5360 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5361 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5362 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5363
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5364 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
5365 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
5366 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
5367 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
5368
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5369 surround mvndc/a *mvndiff,mvnfet,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5370 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]5371 surround mvpdc/a *mvpdiff,mvpfet,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5372 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5373 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5374 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5375 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5376 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5377
5378 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5379 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5380 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5381 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5382
5383 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5384 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5385 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5386 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5387
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5388 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5389
5390#-------------------------------------------------------------
5391# LI - Local interconnect layer
5392#-------------------------------------------------------------
5393
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5394variants *
5395
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5396 width *li 170 "Local interconnect width < %d (li.1)"
5397 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5398
5399 # Note: coreli width rule uses edge4way rule so as not to imply that
5400 # all li contact types can also be minimum width 0.14um.
5401 edge4way ~(coreli,pc,ndc,nsc,pdc,psc)/li coreli 140 coreli,pc,ndc,nsc,pdc,psc \
5402 0 0 "Core local interconnect width < %d (li.c1)"
5403
5404 # width coreli 140 "Core local interconnect width < %d (li.c1)"
5405
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5406 spacing allli allli,*obsli 170 touching_ok "Local interconnect spacing < %d (li.3)"
5407 spacing coreli allli,*obsli 140 touching_ok "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5408
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5409 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5410 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5411
5412 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5413 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5414 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5415
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5416 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5417
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]5418 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
5419 angles coreli 45 \
5420 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5421
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5422#-------------------------------------------------------------
5423# MCON - Contact between local interconnect and metal1
5424#-------------------------------------------------------------
5425
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5426 width lic/m1 170 "mcon.width < %d (mcon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5427 spacing lic/m1 lic/m1,obslic/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5428
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5429 exact_overlap lic/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5430
5431#-------------------------------------------------------------
5432# METAL1 -
5433#-------------------------------------------------------------
5434
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5435 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
5436 spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (met1.2)"
5437 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5438
5439 surround lic/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5440 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5441 surround lic/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5442 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5443
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5444 angles allm1 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
5445
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5446variants (fast),(full)
5447 widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5448 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5449 widespacing *obsm1 3000 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5450 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5451
5452variants (full)
5453 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5454 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5455
5456 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
5457 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5458variants *
5459
5460#--------------------------------------------------
5461# VIA1
5462#--------------------------------------------------
5463
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5464 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
5465 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5466 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5467 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5468 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5469 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5470
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5471 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5472
5473#--------------------------------------------------
5474# METAL2 -
5475#--------------------------------------------------
5476
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5477 width allm2 140 "Metal2 width < %d (met2.1)"
5478 spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (met2.2)"
5479 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5480
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5481 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
5482
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5483variants (fast),(full)
5484 widespacing allm2 3000 allm2,obsm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5485 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5486 widespacing obsm2 3000 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5487 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5488
5489variants (full)
5490 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5491 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5492
5493 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
5494 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5495variants *
5496
5497#--------------------------------------------------
5498# VIA2
5499#--------------------------------------------------
5500
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5501 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5502
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5503 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5504
5505 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5506 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
5507 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5508
5509 exact_overlap v2/m2
5510
5511#--------------------------------------------------
5512# METAL3 -
5513#--------------------------------------------------
5514
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5515 width allm3 300 "Metal3 width < %d (met3.1)"
5516 spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (met3.2)"
5517 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5518
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5519 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
5520
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5521variants (fast),(full)
5522 widespacing allm3 3000 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5523 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5524 widespacing obsm3 3000 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5525 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]5526variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5527 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
5528 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5529variants *
5530
5531
5532#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5533#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5534#--------------------------------------------------
5535# VIA3 - Requires METAL5 Module
5536#--------------------------------------------------
5537
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5538 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
5539 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5540 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5541 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5542 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5543 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5544
5545 exact_overlap v3/m3
5546
5547#-----------------------------
5548# METAL4 - METAL4 Module
5549#-----------------------------
5550
5551variants *
5552
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5553 width allm4 300 "Metal4 width < %d (met4.1)"
5554 spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (met4.2)"
5555 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5556
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5557 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
5558
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5559variants (fast),(full)
5560 widespacing allm4 3000 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5561 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5562 widespacing obsm4 3000 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5563 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]5564variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5565 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
5566 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5567variants *
5568
5569#--------------------------------------------------
5570# VIA4 - Requires METAL5 Module
5571#--------------------------------------------------
5572
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5573 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
5574 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5575 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5576 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5577
5578 exact_overlap v4/m4
5579
5580#-----------------------------
5581# METAL5 - METAL5 Module
5582#-----------------------------
5583
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5584 width allm5 1600 "Metal5 width < %d (met5.1)"
5585 spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (met5.2)"
5586 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5587
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5588 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
5589
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5590#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5591#endif (METAL5)
5592
5593#ifdef REDISTRIBUTION
5594
5595variants (full)
5596
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5597 width metrdl 10000 "RDL width < %d (rdl.1)"
5598 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
5599 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
5600 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5601
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5602variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5603
5604#endif (REDISTRIBUTION)
5605
5606#--------------------------------------------------
5607# NMOS, PMOS
5608#--------------------------------------------------
5609
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5610 edge4way *poly allfetsstd 420 allfets 0 0 \
5611 "Transistor width < %d (diff/tap.2)"
5612 edge4way *poly allfetsspecial 360 allfets 0 0 \
5613 "Transistor in standard cell width < %d (diff/tap.2)"
5614
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5615 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5616 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5617
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5618 spacing allpolynonfet *nsd 55 corner_ok varactor \
5619 "poly spacing to diffusion tap < %d (poly.5)"
5620 spacing allpolynonfet *mvnsd 55 corner_ok mvvaractor \
5621 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5622
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]5623 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5624 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5625 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5626 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]5627 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5628 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]5629 edge4way *mvnsd *mvpdiff 300 ~mvpfet/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5630 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5631
5632 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5633 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5634 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5635
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5636 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5637 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5638
5639 # No HV FETs in LV diff
5640 spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5641 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5642
5643 spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5644 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5645
5646 # Minimum length of MV FETs. Note that this is larger than the minimum
5647 # width (0.29um), so an edge rule is required
5648
5649 edge4way mvndiff mvnfet 500 mvnfet 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5650 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5651
5652 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5653 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5654
5655 edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5656 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5657
5658#--------------------------------------------------
5659# mrp1 (N+ poly resistor)
5660#--------------------------------------------------
5661
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5662 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5663
5664#--------------------------------------------------
5665# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5666# uhrpoly (P+ poly resistor, 2kOhm/sq)
5667#--------------------------------------------------
5668
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5669 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
5670 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
5671 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
5672
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5673 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5674 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5675
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]5676 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]5677 "Poly resistor spacing to poly < %d (poly.9)"
5678
5679 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
5680 "Poly resistor spacing to poly < %d (poly.9)"
5681
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]5682 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5683 "Poly resistor spacing to poly < %d (poly.9)"
5684
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]5685 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5686 "Poly resistor spacing to diffusion < %d (poly.9)"
5687
5688#------------------------------------
5689# nsonos
5690#------------------------------------
5691
5692variants (full)
5693 cifmaxwidth bbox_missing 0 bend_illegal \
5694 "SONOS transistor must be in cell with abutment box (tunm.8)"
5695variants (fast),(full)
5696
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5697#------------------------------------
5698# MOS Varactor device rules
5699#------------------------------------
5700
5701 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5702 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5703
5704 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5705 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5706
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5707 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
5708 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5709
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5710variants (full)
5711 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
5712 "N-well overlap of varactor poly < 0.15um (varac.5)"
5713
5714 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
5715 "Varactor N-well must not contain P+ diffusion (varac.7)"
5716variants (fast),(full)
5717
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5718#ifdef MIM
5719#-----------------------------------------------------------
5720# MiM CAP (CAPM) -
5721#-----------------------------------------------------------
5722
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5723 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5724 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5725 spacing *mimcap via3/m3 80 touching_illegal \
5726 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
5727 surround *mimcc *mimcap 80 absence_illegal \
5728 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5729 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5730
5731 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5732 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5733 spacing via2 *mimcap 100 touching_illegal \
5734 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5735 spacing *mimcap *metal3/m3 500 surround_ok \
5736 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5737
5738variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]5739 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5740 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5741variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5742
5743 # MiM cap contact rules (VIA3)
5744
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5745 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5746 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5747 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5748 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5749 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5750
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5751 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
5752 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5753 spacing *mimcap2 via4/m4 10 touching_illegal \
5754 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
5755 surround *mim2cc *mimcap2 10 absence_illegal \
5756 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5757 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5758
5759 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5760 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]5761 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5762 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5763 spacing *mimcap2 *metal4/m4 500 surround_ok \
5764 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5765
5766variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]5767 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5768 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5769variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5770
5771 # MiM cap contact rules (VIA4)
5772
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5773 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5774 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5775 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5776 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5777 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5778 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5779
5780#endif (MIM)
5781
5782#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]5783# HVNTM
5784#----------------------------
5785variants (full)
5786 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
5787 "HVNTM spacing < %d (hvntm.2)"
5788variants (fast),(full)
5789
5790#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5791# End DRC style
5792#----------------------------
5793
5794end
5795
5796#----------------------------
5797# LEF format definitions
5798#----------------------------
5799
5800lef
5801
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]5802 masterslice pwell pwell PWELL substrate
5803 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]5804
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5805 routing li li1 LI1 LI li
5806
5807 routing m1 met1 MET1 m1
5808 routing m2 met2 MET2 m2
5809 routing m3 met3 MET3 m3
5810#ifdef METAL5
5811 routing m4 met4 MET4 m4
5812 routing m5 met5 MET5 m5
5813#endif (METAL5)
5814#ifdef REDISTRIBUTION
5815 routing mrdl met6 MET6 m6 MRDL METRDL
5816#endif
5817
5818 cut lic mcon MCON Mcon
5819 cut m2c via via1 VIA VIA1 cont2 via12
5820 cut m3c via2 VIA2 cont3 via23
5821#ifdef METAL5
5822 cut via3 via3 VIA3 cont4 via34
5823 cut via4 via4 VIA4 cont5 via45
5824#endif (METAL5)
5825
5826 obs obsli li1
5827 obs obsm1 met1
5828 obs obsm2 met2
5829 obs obsm3 met3
5830
5831#ifdef METAL5
5832 obs obsm4 met4
5833 obs obsm5 met5
5834#endif (METAL5)
5835#ifdef REDISTRIBUTION
5836 obs obsmrdl met6
5837#endif
5838
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]5839 # NOTE: obslic only used with li1, not obsli.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5840 obs obslic mcon
5841
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]5842 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
5843 obs obsm1 via
5844 obs obsm2 via2
5845#ifdef METAL5
5846 obs obsm3 via3
5847 obs obsm4 via4
5848#endif (METAL5)
5849
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5850end
5851
5852#-----------------------------------------------------
5853# Device and Parasitic extraction
5854#-----------------------------------------------------
5855
5856
5857extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5858 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5859 cscale 1
5860 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
5861 # dimensions must be in units of microns in the extract file.
5862 # Use extract style "ngspice(si)" to override this and produce
5863 # a file with SI units for length/area.
5864
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5865 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5866 lambda 1E6
5867 variants (si)
5868 lambda 1.0
5869 variants *
5870
5871 units microns
5872 step 7
5873 sidehalo 2
5874
5875 # NOTE: MiM cap layers have been purposely put out of order,
5876 # may want to reconsider.
5877
5878 planeorder dwell 0
5879 planeorder well 1
5880 planeorder active 2
5881 planeorder locali 3
5882 planeorder metal1 4
5883 planeorder metal2 5
5884 planeorder metal3 6
5885#ifdef METAL5
5886 planeorder metal4 7
5887 planeorder metal5 8
5888#ifdef REDISTRIBUTION
5889 planeorder metali 9
5890 planeorder block 10
5891 planeorder comment 11
5892 planeorder cap1 12
5893 planeorder cap2 13
5894#else (!REDISTRIBUTION)
5895 planeorder block 9
5896 planeorder comment 10
5897 planeorder cap1 11
5898 planeorder cap2 12
5899#endif (!REDISTRIBUTION)
5900#else (!METAL5)
5901#ifdef REDISTRIBUTION
5902 planeorder metali 7
5903 planeorder block 8
5904 planeorder comment 9
5905 planeorder cap1 10
5906 planeorder cap2 11
5907#else (!REDISTRIBUTION)
5908 planeorder block 7
5909 planeorder comment 8
5910 planeorder cap1 9
5911 planeorder cap2 10
5912#endif (!REDISTRIBUTION)
5913#endif (!METAL5)
5914
5915 height dnwell -0.1 0.1
5916 height nwell,pwell 0.0 0.2062
5917 height alldiff 0.2062 0.12
5918 height allpoly 0.3262 0.18
5919 height alldiffcont 0.3262 0.61
5920 height pc 0.5062 0.43
5921 height allli 0.9361 0.10
5922 height lic 1.0361 0.34
5923 height allm1 1.3761 0.36
5924 height v1 1.7361 0.27
5925 height allm2 2.0061 0.36
5926 height v2 2.3661 0.42
5927 height allm3 2.7861 0.845
5928#ifdef METAL5
5929 height v3 3.6311 0.39
5930 height allm4 4.0211 0.845
5931 height v4 4.8661 0.505
5932 height allm5 5.3711 1.26
5933 height mimcap 2.4661 0.2
5934 height mimcap2 3.7311 0.2
5935 height mimcc 2.6661 0.12
5936 height mim2cc 3.9311 0.09
5937#ifdef REDISTRIBUTION
5938 height mrdlc 6.6311 5.2523
5939 height mrdl 11.8834 4.0
5940#endif (!REDISTRIBUTION)
5941#endif (!METAL5)
5942
5943 # Antenna check parameters
5944 # Note that checks w/diode diffusion are not modeled
5945 model partial
5946 antenna poly sidewall 50 none
5947 antenna allcont surface 3 none
5948 antenna li sidewall 75 0 450
5949 antenna lic surface 3 0 18
5950 antenna m1,m2,m3 sidewall 400 2600 400
5951 antenna v1 surface 3 0 18
5952 antenna v2 surface 6 0 36
5953#ifdef METAL5
5954 antenna m4,m5 sidewall 400 2600 400
5955 antenna v3,v4 surface 6 0 36
5956#endif (METAL5)
5957
5958 tiedown alldiffnonfet
5959
5960 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
5961
5962# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
5963
5964# Resistances are in milliohms per square
5965# Optional 3rd argument is the corner adjustment fraction
5966# Device values come from trtc.cor (typical corner)
5967 resist (dnwell)/dwell 2200000
5968 resist (pwell)/well 3050000
5969 resist (nwell)/well 1700000
5970 resist (rpw)/well 3050000 0.5
5971 resist (*ndiff,nsd)/active 120000
5972 resist (*pdiff,*psd)/active 197000
5973 resist (*mvndiff,mvnsd)/active 114000
5974 resist (*mvpdiff,*mvpsd)/active 191000
5975
5976 resist ndiffres/active 120000 0.5
5977 resist pdiffres/active 197000 0.5
5978 resist mvndiffres/active 114000 0.5
5979 resist mvpdiffres/active 191000 0.5
5980 resist mrp1/active 48200 0.5
5981 resist xhrpoly/active 319800 0.5
5982 resist uhrpoly/active 2000000 0.5
5983
5984 resist (allpolynonres)/active 48200
5985 resist rmp/active 48200
5986
5987 resist (allli)/locali 12200
5988 resist (allm1)/metal1 125
5989 resist (allm2)/metal2 125
5990 resist (allm3)/metal3 47
5991#ifdef METAL5
5992 resist (allm4)/metal4 47
5993 resist (allm5)/metal5 29
5994#endif (METAL5)
5995#ifdef REDISTRIBUTION
5996 resist mrdl/metali 5
5997#endif (REDISTRIBUTION)
5998
5999 contact ndc,nsc 15000
6000 contact pdc,psc 15000
6001 contact mvndc,mvnsc 15000
6002 contact mvpdc,mvpsc 15000
6003 contact pc 15000
6004 contact lic 152000
6005 contact m2c 4500
6006 contact m3c 3410
6007#ifdef METAL5
6008#ifdef MIM
6009 contact mimcc 4500
6010 contact mim2cc 3410
6011#endif (MIM)
6012 contact via3 3410
6013 contact via4 380
6014#endif (METAL5)
6015#ifdef REDISTRIBUTION
6016 contact mrdlc 6
6017#endif (REDISTRIBUTION)
6018
6019#-------------------------------------------------------------------------
6020# Parasitic capacitance values: Use document (...)
6021#-------------------------------------------------------------------------
6022# This uses the new "default" definitions that determine the intervening
6023# planes from the planeorder stack, take care of the reflexive sideoverlap
6024# definitions, and generally clean up the section and make it more readable.
6025#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6026# Also uses "units microns" statement. All values are taken from the
6027# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
6028# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6029#-------------------------------------------------------------------------
6030# Remember that device capacitances to substrate are taken care of by the
6031# models. Thus, active and poly definitions ignore all "fet" types.
6032# fet types are excluded when computing parasitic capacitance to
6033# active from layers above them because poly is a shield; fet types are
6034# included for parasitics from layers above to poly. Resistor types
6035# should be removed from all parasitic capacitance calculations, or else
6036# they just create floating caps. Technically, the capacitance probably
6037# should be split between the two terminals. Unsure of the correct model.
6038#-------------------------------------------------------------------------
6039
6040#n-well
6041# NOTE: This value not found in PEX files
6042defaultareacap nwell well 120
6043
6044#n-active
6045# Rely on device models to capture *ndiff area cap
6046# Do not extract parasitics from resistors
6047# defaultareacap allnactivenonfet active 790
6048# defaultperimeter allnactivenonfet active 280
6049
6050#p-active
6051# Rely on device models to capture *pdiff area cap
6052# Do not extract parasitics from resistors
6053# defaultareacap allpactivenonfet active 810
6054# defaultperimeter allpactivenonfet active 300
6055
6056#poly
6057# Do not extract parasitics from resistors
6058# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6059# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6060# defaultperimeter allpolynonfet active 57
6061
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6062 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6063 defaultareacap *poly active nwell,obswell,pwell well 106
6064 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6065
6066#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6067 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6068 defaultareacap allli locali nwell,obswell,pwell well 37
6069 defaultperimeter allli locali nwell,obswell,pwell well 55
6070 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6071
6072#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6073 defaultoverlap allli locali allactivenonfet active 37
6074 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6075
6076#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6077 defaultoverlap allli locali allpolynonres active 94
6078 defaultsideoverlap allli locali allpolynonres active 52
6079 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6080
6081#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6082 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6083 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
6084 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6085 defaultoverlap allm1 metal1 nwell well 26
6086
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6087#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6088 defaultoverlap allm1 metal1 allactivenonfet active 26
6089 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6090
6091#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6092 defaultoverlap allm1 metal1 allpolynonres active 45
6093 defaultsideoverlap allm1 metal1 allpolynonres active 47
6094 defaultsideoverlap *poly active allm1 metal1 17
6095
6096#metal1->locali
6097 defaultoverlap allm1 metal1 allli locali 114
6098 defaultsideoverlap allm1 metal1 allli locali 59
6099 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6100
6101#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6102 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6103 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
6104 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
6105 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6106
6107#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6108 defaultoverlap allm2 metal2 allactivenonfet active 17
6109 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6110
6111#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6112 defaultoverlap allm2 metal2 allpolynonres active 24
6113 defaultsideoverlap allm2 metal2 allpolynonres active 41
6114 defaultsideoverlap *poly active allm2 metal2 11
6115
6116#metal2->locali
6117 defaultoverlap allm2 metal2 allli locali 38
6118 defaultsideoverlap allm2 metal2 allli locali 46
6119 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6120
6121#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6122 defaultoverlap allm2 metal2 allm1 metal1 134
6123 defaultsideoverlap allm2 metal2 allm1 metal1 67
6124 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6125
6126#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6127 defaultsidewall allm3 metal3 63
6128 defaultoverlap allm3 metal3 nwell well 12
6129 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
6130 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6131
6132#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6133 defaultoverlap allm3 metal3 allactive active 12
6134 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6135
6136#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6137 defaultoverlap allm3 metal3 allpolynonres active 16
6138 defaultsideoverlap allm3 metal3 allpolynonres active 44
6139 defaultsideoverlap *poly active allm3 metal3 9
6140
6141#metal3->locali
6142 defaultoverlap allm3 metal3 allli locali 21
6143 defaultsideoverlap allm3 metal3 allli locali 47
6144 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6145
6146#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6147 defaultoverlap allm3 metal3 allm1 metal1 35
6148 defaultsideoverlap allm3 metal3 allm1 metal1 55
6149 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6150
6151#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6152 defaultoverlap allm3 metal3 allm2 metal2 86
6153 defaultsideoverlap allm3 metal3 allm2 metal2 70
6154 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6155
6156#ifdef METAL5
6157#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6158 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6159# defaultareacap alltopm metal4 well 6
6160 areacap allm4/m4 8
6161 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6162 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6163
6164#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6165 defaultoverlap allm4 metal4 allactivenonfet active 8
6166 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6167
6168#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6169 defaultoverlap allm4 metal4 allpolynonres active 10
6170 defaultsideoverlap allm4 metal4 allpolynonres active 38
6171 defaultsideoverlap *poly active allm4 metal4 6
6172
6173#metal4->locali
6174 defaultoverlap allm4 metal4 allli locali 12
6175 defaultsideoverlap allm4 metal4 allli locali 40
6176 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6177
6178#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6179 defaultoverlap allm4 metal4 allm1 metal1 15
6180 defaultsideoverlap allm4 metal4 allm1 metal1 43
6181 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6182
6183#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6184 defaultoverlap allm4 metal4 allm2 metal2 20
6185 defaultsideoverlap allm4 metal4 allm2 metal2 46
6186 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6187
6188#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6189 defaultoverlap allm4 metal4 allm3 metal3 84
6190 defaultsideoverlap allm4 metal4 allm3 metal3 71
6191 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6192
6193#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6194 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6195# defaultareacap allm5 metal5 well 6
6196 areacap allm5/m5 6
6197 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6198 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6199
6200#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6201 defaultoverlap allm5 metal5 allactivenonfet active 6
6202 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6203
6204#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6205 defaultoverlap allm5 metal5 allpolynonres active 7
6206 defaultsideoverlap allm5 metal5 allpolynonres active 40
6207 defaultsideoverlap *poly active allm5 metal5 6
6208
6209#metal5->locali
6210 defaultoverlap allm5 metal5 allli locali 8
6211 defaultsideoverlap allm5 metal5 allli locali 41
6212 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6213
6214#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6215 defaultoverlap allm5 metal5 allm1 metal1 9
6216 defaultsideoverlap allm5 metal5 allm1 metal1 43
6217 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6218
6219#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6220 defaultoverlap allm5 metal5 allm2 metal2 11
6221 defaultsideoverlap allm5 metal5 allm2 metal2 46
6222 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6223
6224#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6225 defaultoverlap allm5 metal5 allm3 metal3 20
6226 defaultsideoverlap allm5 metal5 allm3 metal3 54
6227 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6228
6229#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6230 defaultoverlap allm5 metal5 allm4 metal4 68
6231 defaultsideoverlap allm5 metal5 allm4 metal4 83
6232 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6233#endif (METAL5)
6234
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]6235#ifdef REDISTRIBUTION
6236#endif (REDISTRIBUTION)
6237
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6238# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6239
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6240variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6241
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6242 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
6243 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6244 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6245 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
6246 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
6247 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
6248 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
6249 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6250 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6251 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6252
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6253 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6254 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6255 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6256 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6257 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
6258 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6259 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
6260 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6261 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6262 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6263 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6264 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6265 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6266 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6267 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6268 *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6269
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]6270 # Bipolars
6271 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
6272 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
6273 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
6274
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]6275 # Ignore the extended-drain FET geometry that forms part of the high-voltage
6276 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]6277 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
6278 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]6279
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6280 # Extended drain devices (must appear before the regular devices)
6281 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
6282 dnwell pwell,space/w error l=l w=w
6283 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
6284 dnwell pwell,space/w error l=l w=w
6285 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
6286 pwell,space/w nwell error l=l w=w
6287
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6288 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
6289 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
6290 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
6291 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
6292 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
6293 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6294
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6295 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
6296 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
6297 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
6298 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6299#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6300 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
6301 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6302#endif (METAL5)
6303
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6304 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6305 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6306 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6307 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6308 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6309 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6310 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6311 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6312 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6313 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6314 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6315 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6316 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6317 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6318 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6319 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6320 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6321 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6322 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6323 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6324 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6325 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6326 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6327 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6328
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]6329 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6330 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]6331 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6332 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6333 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6334 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]6335 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
6336 *mvndiff pwell,space/w error l=l w=w
6337 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
6338 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6339
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6340 device resistor sky130_fd_pr__res_generic_po rmp *poly
6341 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6342
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6343 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6344 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6345 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
6346 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]6347 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6348 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6349 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6350 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6351
6352 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
6353 pwell,space/w a=area
6354 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
6355 pwell,space/w a=area
6356 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
6357 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6358 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6359 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6360
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6361
6362#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]6363 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
6364 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6365#endif (MIM)
6366
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6367 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6368
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6369 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
6370 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
6371 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
6372 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6373 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6374 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
6375 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
6376 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6377 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6378 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
6379 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
6380 pwell,space/w
6381
6382 # Extended drain devices (must appear before the regular devices)
6383 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
6384 dnwell pwell,space/w error
6385 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
6386 dnwell pwell,space/w error
6387 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
6388 pwell,space/w nwell error
6389
6390 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
6391 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
6392 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6393
6394 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6395 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
6396 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
6397 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6398
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6399 device resistor sky130_fd_pr__res_generic_po rmp *poly
6400 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
6401 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
6402 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
6403 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6404#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6405 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
6406 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6407#endif (METAL5)
6408
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6409 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
6410 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
6411 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
6412 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
6413 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
6414 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
6415 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
6416 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
6417 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
6418 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
6419 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
6420 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
6421 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
6422 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
6423 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6424 device resistor mrdn_hv mvndiffres *mvndiff
6425 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6426 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6427
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6428 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6429 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
6430 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6431 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6432
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6433 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6434 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
6435 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6436 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6437
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]6438 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
6439 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]6440 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6441
6442#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6443 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
6444 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6445#endif (MIM)
6446
6447end
6448
6449#-----------------------------------------------------
6450# Wiring tool definitions
6451#-----------------------------------------------------
6452
6453wiring
6454 # All wiring values are in nanometers
6455 scalefactor 10
6456
6457 contact lic 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6458 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6459 contact v2 280 m2 0 45 m3 25 0
6460#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]6461 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6462 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6463#endif (METAL5)
6464
6465 contact pc 170 poly 50 80 li 0 80
6466 contact pdc 170 pdiff 40 60 li 0 80
6467 contact ndc 170 ndiff 40 60 li 0 80
6468 contact psc 170 psd 40 60 li 0 80
6469 contact nsc 170 nsd 40 60 li 0 80
6470
6471end
6472
6473#-----------------------------------------------------
6474# Plain old router. . .
6475#-----------------------------------------------------
6476
6477router
6478end
6479
6480#------------------------------------------------------------
6481# Plowing (restored in magic 8.2, need to fill this section)
6482#------------------------------------------------------------
6483
6484plowing
6485end
6486
6487#-----------------------------------------------------------------
6488# No special plot layers defined (use default PNM color choices)
6489#-----------------------------------------------------------------
6490
6491plot
6492 style pnm
6493 default
6494 draw fillblock no_color_at_all
6495 draw nwell cwell
6496end
6497