| commit | ec746c6bfedcc3a0ca616e920bb047fe3cdd4f18 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 81091e35b3f2e457eea920ab542a072a375e255b | |
| parent | 1cd268a4b1c27b591dd1ab0f66c03a2514c7394c [diff] | |
| parent | e9d513d1fa1cf4b0ae9ad26084961430eb5f1873 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>