| commit | e9d513d1fa1cf4b0ae9ad26084961430eb5f1873 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 4989e4d48069ee613de7f0dd5596fe82808ef8bc | |
| parent | c3d24b3b50d46c552c712cc770f48ffbbc0bd07f [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>