)]}'
{
  "commit": "ec746c6bfedcc3a0ca616e920bb047fe3cdd4f18",
  "tree": "81091e35b3f2e457eea920ab542a072a375e255b",
  "parents": [
    "1cd268a4b1c27b591dd1ab0f66c03a2514c7394c",
    "e9d513d1fa1cf4b0ae9ad26084961430eb5f1873"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}