| commit | 48c8310e464157d797c78cb2e6d6b5a21d710c20 | [log] [tgz] |
|---|---|---|
| author | Ethan Mahintorabi <ethanmoon@google.com> | Wed Nov 24 19:47:21 2021 -0800 |
| committer | Ethan Mahintorabi <ethanmoon@google.com> | Wed Nov 24 19:52:11 2021 -0800 |
| tree | a859d0aadc1ce4dcf3bbb48821d846ba06528e62 | |
| parent | d3c4505de8ec4c52fe70c276b351929297ffcd6e [diff] | |
| parent | 31cefa62c9a34b29409b8514104da4e0e68693c0 [diff] |
Fixes ReRAM Verilog-A model naming convention. Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>