tree a859d0aadc1ce4dcf3bbb48821d846ba06528e62
parent d3c4505de8ec4c52fe70c276b351929297ffcd6e
parent 31cefa62c9a34b29409b8514104da4e0e68693c0
author Ethan Mahintorabi <ethanmoon@google.com> 1637812041 -0800
committer Ethan Mahintorabi <ethanmoon@google.com> 1637812331 -0800

Fixes ReRAM Verilog-A model naming convention.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>