)]}'
{
  "commit": "48c8310e464157d797c78cb2e6d6b5a21d710c20",
  "tree": "a859d0aadc1ce4dcf3bbb48821d846ba06528e62",
  "parents": [
    "d3c4505de8ec4c52fe70c276b351929297ffcd6e",
    "31cefa62c9a34b29409b8514104da4e0e68693c0"
  ],
  "author": {
    "name": "Ethan Mahintorabi",
    "email": "ethanmoon@google.com",
    "time": "Wed Nov 24 19:47:21 2021 -0800"
  },
  "committer": {
    "name": "Ethan Mahintorabi",
    "email": "ethanmoon@google.com",
    "time": "Wed Nov 24 19:52:11 2021 -0800"
  },
  "message": "Fixes ReRAM Verilog-A model naming convention.\n\nSigned-off-by: Ethan Mahintorabi \u003cethanmoon@google.com\u003e\n",
  "tree_diff": []
}