commit 48c8310e464157d797c78cb2e6d6b5a21d710c20
author Ethan Mahintorabi <ethanmoon@google.com> Wed Nov 24 19:47:21 2021 -0800
committer Ethan Mahintorabi <ethanmoon@google.com> Wed Nov 24 19:52:11 2021 -0800
tree a859d0aadc1ce4dcf3bbb48821d846ba06528e62
parent d3c4505de8ec4c52fe70c276b351929297ffcd6e
parent 31cefa62c9a34b29409b8514104da4e0e68693c0

Fixes ReRAM Verilog-A model naming convention.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>

cells/reram_cell/sky130_fd_pr_reram__reram_cell.va

diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
index 978e0a8..8377a90 100644
--- a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
+++ b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
@@ -17,7 +17,7 @@
 `include "constants.vams"
 `include "disciplines.vams"
 
-module rram2(TE, BE);
+module sky130_fd_pr_reram__reram_cell(TE, BE);
     inout TE; // top electrode
     inout BE; // bottom electrode
     electrical TE, BE;