docs: Adding Parasitic Layout Extraction docs.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/docs/rules.rst b/docs/rules.rst
index 7ea4907..c8bde9b 100644
--- a/docs/rules.rst
+++ b/docs/rules.rst
@@ -19,4 +19,6 @@
rules/wlcsp
rules/hv
+ rules/rcx
+
rules/errors
diff --git a/docs/rules/rcx.rst b/docs/rules/rcx.rst
new file mode 100644
index 0000000..65c41b1
--- /dev/null
+++ b/docs/rules/rcx.rst
@@ -0,0 +1,61 @@
+Parasitic Layout Extraction
+===========================
+
+This table list layers and contacts included in SPICE models, and parasitic layers include in the AssuraLayout Extraction.
+
+The modeled columns indicate sheets and contacts that are parasitic resistance/capacitance included in the model extraction measurements.
+
+The CAD columns indicate sheets and contacts that are parasitics included in the schematic/layout RCX from Assura.
+
+.. csv-table:: Parasitic Extraction Table
+ :file: rcx/rcx-all.csv
+ :header-rows: 2
+
+
+.. note:: The models includes M1/M2 capacitance. As a result of RCX extraction limitation M1/M2 routing over the varactor will have no capacitance extraction.
+
+Routing and placement of devices over or under Precision resistors (xhrpoly_X_X) should be avoided.
+
+The parasitic capacitance between 3-terminal MIMC and any routing/devices is not included in layout RCX, except M3 by 1 snap grid width.
+
+No artificial fringing capacitance is extracted for MIMC M2/M3 due to CAD algorithm after CAPM sizing.
+
+The parasitic capacitance between Precision resistors (xhrpoly_X_X) and any routing/devices is not included in layout RCX.
+
+S8Q-5R is not supported for RF ESD diode RCX blocking.
+
+The ``areaid:substratecut`` will be extracted as a 0.123 ohm two terms resistor.
+
+Resistance Rules
+----------------
+
+.. todo:: This table should be rendered like the periphery rules.
+
+.. csv-table:: Table of resistance rules
+ :file: rcx/resistance.csv
+ :header-rows: 2
+
+
+Capacitance Rules
+-----------------
+
+.. todo:: This table should be rendered like the periphery rules.
+
+.. csv-table:: Table of capacitance rules
+ :file: rcx/capacitance.csv
+ :header-rows: 2
+
+
+Discrepencies
+-------------
+
+Non-precision poly resistors
+ These resistors do not extract capacitance to substrate.
+
+ This needs to be accounted for manually by using ICPS_0150_0210 (cap per perimeter), and ICPS_2000_4000 (cap per area).
+
+Un-shielded VPP's
+ Any routing above an un-shielded VPP will not be extracted.
+
+ The impact of this on total capacitance and parasitic capacitance is already comprehended in the model corners, however, cross-talk is not modeled. Also, parasitic cap is routed to ground and this may not be ideal for the scenario.
+ The parasitic cap can be estimated using RescapWeb.
diff --git a/docs/rules/rcx/capacitance.csv b/docs/rules/rcx/capacitance.csv
new file mode 100644
index 0000000..efd0ec6
--- /dev/null
+++ b/docs/rules/rcx/capacitance.csv
@@ -0,0 +1,30 @@
+,General(CAP.-)
+.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.)
+
+,MOS Devices (MOS.-)
+.mos.1,area between poly and diff should not have capacitance extracted.
+.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8)
+.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).
+.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.
+.mos.5,All 20V NMOS ISO DEFETs will have the parasitic diode included in the models.,This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub).
+.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.
+.mos.7,The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor.,The model will over-write all other instance parameters from CAD extraction.
+
+,Resistors (RES.-)
+.res.1,short devices must not have capacitance calculated across the device.
+.res.2,fuse devices must have capacitance extracted.
+.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.
+.res.4,metops that are merged must have capacitance extracted.
+.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.
+.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).
+.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
+.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
+
+,Capacitors (PASSIVES.-)
+.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)"
+.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)"
+.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)"
+.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)"
+
+,Bipolar Devices
+,none
diff --git a/docs/rules/rcx/rcx-all.csv b/docs/rules/rcx/rcx-all.csv
new file mode 100644
index 0000000..fac03cd
--- /dev/null
+++ b/docs/rules/rcx/rcx-all.csv
@@ -0,0 +1,25 @@
+Description,Model Structure,Modeled RX,,Actual CAD RX,,RX Discrepancy,Modeled CX,Actual CX,CX Discrepancy
+,,Contacts,Sheets,Contacts,Sheets,,Sheet,Sheet,
+All Periphery FETs,mXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min),licon/mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3,li-negligible
+20V NDEFETs NONISO,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3,li-negligible
+20V NDEFETs ISO,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li/dnwdiode_psub,li/m1/m2-m3,li-negligible
+20V PDEFETs,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3/dnwhvdiode_psub,li-negligible
+Cell FETs,NOT EXTRACTED FROM LAYOUT,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
+All Diodes,dXXXX n1 n2 area pj,licon,diff,licon/mcon/vias, poly/li/m1/m2-m3,licon-negligible,Junction,li/m1/m2-m3,none
+RF ESD Diodes,xesd_XXXX n1 n2 area pj,licon/mcon/ via,li/m1/m2,via2,m3,none,li/m1/m2,m3,none
+Parasitic PNP,qXXXX nc nb ne ns pnppar m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
+Parasitic PNP (5X),qXXXX nc nb ne ns pnppar5x m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
+Parasitic NPN,qXXXX nc nb ne ns npnpar m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
+Non-precision Resistors,rXXXX a b l w m,none,sheet layer,licon/mcon/vias,none (no sheet resistance where sheet layer & res id layer intersect),none,none,junction/li/m1/m2-m3,parasitic capacitance to substrate (tool limitation)
+Precision poly resistor,xXXXXX hrpoly_X_X r0 r1 b l w m,licon/mcon,poly/li,via,m1/m2-m3,none,poly-sub,m1/m2-m3,li-negligible
+MIM Capacitor (2-terminal),xXXXX xcmimc2 c0 c1 w l m ,via2,m3,N/A,poly/li/m1/m2,m2 (of the device) -negligible,capm-m2,li/m1/m2-m3,routing layers underneath device
+MIM Capacitor (3-terminal),xXXXX xcmimc c0 c1 b w l m ,via2,m3,N/A,poly/li/m1/m2,m2 (of the device) -negligible,m2-sub/capm-m2,(1) Carea of M2-sub (non-overlap CAPM w/ 0.14um upsize)\n(2) M3 Cap by 1 snap grid width,none
+Isolated Pwell Resistor,xXXXX pwres r0 r1 b l w m,licon/mcon,pwell/li,vias,m1/m2-m3,none,none,junction/m1/m2-m3,li-negligible
+Vertical Parallel Plate Cap,xXXXX xcmvpp c0 c1 b m (note: no special RCX implementation for VPP required since black-box LVS will be used),mcon/via,li/m1/m2,none (black box LVS),none (black box LVS),none,li/mcon//m1/via/m2,none (black box LVS),Parasitic capacitance to routing above
+Vertical Parallel Plate Cap over MOSCAP,xXXXX xcmvpp2_* c0 c1 b m ,mcon/via,li/m1/m2,none (black box LVS),none (black box LVS),none,li/mcon//m1/via/m2,none (black box LVS),Parasitic capacitance to routing above
+4-terminal Vertical Parallel Plate Cap (M3 Shielded),xXXXXX xcmvpp*x*_m3shield c0 c1 b term4 m=,licon/mcon/ via,poly/li/m1/m2,via3/via4,m3/m4/m5,none,poly/licon/li/mcon/m1/via/m2/m3,"m3-substrate (not m3-m2), neighboring metal to VPP metal",none
+4-terminal Vertical Parallel Plate Cap (M5 Shielded),xXXXXX xcmvpp*_*m5shield c0 c1 b term4 m=,licon/mcon/ via/via2/via3,poly/li/m1/m2/m3/m4,via4,m5,none,poly/licon/li/mcon/m1/via/m2/m3/m4/m5,neighboring metal to VPP metal,none
+3-terminal Vertical Parallel Plate Cap,xXXXXX xcmvpp*x* c0 c1 b m=\nxXXXXX xcmvpp*x*_lishield c0 c1 b m=,mcon/ via,li/m1/m2,via2/via3/via4,m3/m4/m5,none,li/mcon/m1/via/m2,neighboring metal to VPP metal,Parasitic capacitance to routing above
+3-terminal Vertical Parallel Plate Cap (for S8Q/S8P only),xXXXXX xcmvpp*x*_m3_lishield c0 c1 b m=,mcon/ via/via2,li/m1/m2/m3,via3/via4,m4/m5,none,li/mcon/m1/via/m2/via2/m3,neighboring metal to VPP metal,none
+Varactor,xXXXXX xcnwvc c0 c1 b l w m,licon/mcon/via,diff/poly/li/m1/m2,via2,m3,none,poly/li/m1/m2,nwdiodemodel/m3*,none
+Inductor,xXXXXX xindXXXX t1 t2 body (note: no special RCX implementation for inductor required since black-box LVS will be used),via,m2/Cu,Nothing extracted within inductor.dg layer,,none,m2/via/Cu,Nothing extracted within inductor.dg layer,none
diff --git a/docs/rules/rcx/resistance.csv b/docs/rules/rcx/resistance.csv
new file mode 100644
index 0000000..04980a0
--- /dev/null
+++ b/docs/rules/rcx/resistance.csv
@@ -0,0 +1,26 @@
+ ,General (RES.-)
+.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.
+
+,Sheet Resistance (SR.-)
+.X,Calibre now extracts deltaW by bucketing the sheet rho based on different widths.,The accuracy of each bucket must be within 2% of the Sheet Rho Calc using deltaW.
+.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology)
+.met2,Parasitic resistance is calculated for all metal2.
+.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1
+.li1,Parasitic resistance is calculated for all li1.
+.poly.1,Parasitic resistance on gates is calculated to the center of the gate.
+.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.
+.diff.1,Parasitic resistance is not extracted for any diffusion regions.
+.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.
+.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.
+
+,contact-to-gate space (CT.-)
+.via,All vias will have parasitic resistance extracted.
+.mcon,All mcons will have parasitic resistance extracted.
+.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.
+.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.
+.licon.3,All licons that are connected to FETs will be extracted by RCX.
+.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.
+.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.
+.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.
+.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models."
+.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models."
