Add configuration

openlane/unigate/config.json

diff --git a/openlane/unigate/config.json b/openlane/unigate/config.json
index 132c66a..a94868f 100644
--- a/openlane/unigate/config.json
+++ b/openlane/unigate/config.json
@@ -1,15 +1,29 @@
 {
     "DESIGN_NAME": "unigate",
     "DESIGN_IS_CORE": 0,
-    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/unigate.v"],
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/u21.v",
+        "dir::../../verilog/rtl/u31.v",
+        "dir::../../verilog/rtl/u41.v",
+        "dir::../../verilog/rtl/u22.v",
+        "dir::../../verilog/rtl/ucomb.v",
+        "dir::../../verilog/rtl/u21_ref.v",
+        "dir::../../verilog/rtl/u31_ref.v",
+        "dir::../../verilog/rtl/u41_ref.v",
+        "dir::../../verilog/rtl/u22_ref.v",
+        "dir::../../verilog/rtl/ucomb_ref.v",
+        "dir::../../verilog/rtl/ucomb_full.v",
+        "dir::../../verilog/rtl/unigate.v"
+    ],
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "wb_clk_i",
-    "CLOCK_NET": "counter.clk",
+    "CLOCK_NET": "wb_clk_i",
     "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 900 600",
+    "DIE_AREA": "0 0 2400 2700",
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
     "PL_BASIC_PLACEMENT": 0,
-    "PL_TARGET_DENSITY": 0.55,
+    "PL_TARGET_DENSITY": 0.2,
     "VDD_NETS": ["vccd1"],
     "GND_NETS": ["vssd1"],
     "DIODE_INSERTION_STRATEGY": 4,

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index e089c52..fab8db2 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -6,7 +6,21 @@
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
-    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/unigate.v"],
+    "VERILOG_FILES_BLACKBOX": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/u21.v",
+        "dir::../../verilog/rtl/u31.v",
+        "dir::../../verilog/rtl/u41.v",
+        "dir::../../verilog/rtl/u22.v",
+        "dir::../../verilog/rtl/ucomb.v",
+        "dir::../../verilog/rtl/u21_ref.v",
+        "dir::../../verilog/rtl/u31_ref.v",
+        "dir::../../verilog/rtl/u41_ref.v",
+        "dir::../../verilog/rtl/u22_ref.v",
+        "dir::../../verilog/rtl/ucomb_ref.v",
+        "dir::../../verilog/rtl/ucomb_full.v",
+        "dir::../../verilog/rtl/unigate.v"
+    ],
     "EXTRA_LEFS": "dir::../../lef/unigate.lef",
     "EXTRA_GDS_FILES": "dir::../../gds/unigate.gds",
     "FP_PDN_CHECK_NODES": 0,