Rename default macro
diff --git a/openlane/user_proj_example/config.json b/openlane/unigate/config.json
similarity index 93%
rename from openlane/user_proj_example/config.json
rename to openlane/unigate/config.json
index 370d74c..132c66a 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/unigate/config.json
@@ -1,7 +1,7 @@
{
- "DESIGN_NAME": "user_proj_example",
+ "DESIGN_NAME": "unigate",
"DESIGN_IS_CORE": 0,
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
+ "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/unigate.v"],
"CLOCK_PERIOD": 10,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "counter.clk",
@@ -42,4 +42,4 @@
"SYNTH_MAX_FANOUT": 4,
"PL_TARGET_DENSITY": 0.45
}
-}
\ No newline at end of file
+}
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/unigate/pin_order.cfg
similarity index 100%
rename from openlane/user_proj_example/pin_order.cfg
rename to openlane/unigate/pin_order.cfg
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..e089c52 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -6,9 +6,9 @@
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+ "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/unigate.v"],
+ "EXTRA_LEFS": "dir::../../lef/unigate.lef",
+ "EXTRA_GDS_FILES": "dir::../../gds/unigate.gds",
"FP_PDN_CHECK_NODES": 0,
"SYNTH_ELABORATE_ONLY": 1,
"PL_RANDOM_GLB_PLACEMENT": 1,
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/unigate.v
similarity index 98%
rename from verilog/rtl/user_proj_example.v
rename to verilog/rtl/unigate.v
index 26081e9..c8f9deb 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/unigate.v
@@ -17,7 +17,7 @@
/*
*-------------------------------------------------------------
*
- * user_proj_example
+ * unigate
*
* This is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
@@ -35,7 +35,7 @@
*-------------------------------------------------------------
*/
-module user_proj_example #(
+module unigate #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..00436c1 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,8 +21,8 @@
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
+ `include "gl/unigate.v"
`else
`include "user_project_wrapper.v"
- `include "user_proj_example.v"
-`endif
\ No newline at end of file
+ `include "unigate.v"
+`endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..e3295fe 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,7 +82,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+unigate mprj (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
