Add files via upload
diff --git a/openlane/arbiterpuf/config.json b/openlane/arbiterpuf/config.json
new file mode 100644
index 0000000..7ea7730
--- /dev/null
+++ b/openlane/arbiterpuf/config.json
@@ -0,0 +1,50 @@
+{
+ "DESIGN_NAME": "arbiterpuf",
+ "DESIGN_IS_CORE": 0,
+ "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/arbiterpuf.v"],
+ "CLOCK_PERIOD": 10,
+ "CLOCK_PORT": "",
+ "CLOCK_NET": "ipulse",
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 400 400",
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "PL_BASIC_PLACEMENT": 0,
+ "PL_TARGET_DENSITY": 0.45,
+ "VDD_NETS": ["vccd1"],
+ "GND_NETS": ["vssd1"],
+ "DIODE_INSERTION_STRATEGY": 4,
+ "RUN_CVC": 0,
+ "PL_RESIZER_HOLD_MAX_BUFFER_PERCENT": 80,
+ "PL_RESIZER_HOLD_SLACK_MARGIN": 0.8,
+ "GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT": 80,
+ "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.8,
+ "pdk::sky130*": {
+ "FP_CORE_UTIL": 45,
+ "RT_MAX_LAYER": "met4",
+ "scl::sky130_fd_sc_hd": {
+ "CLOCK_PERIOD": 10
+ },
+ "scl::sky130_fd_sc_hdll": {
+ "CLOCK_PERIOD": 20
+ },
+ "scl::sky130_fd_sc_hs": {
+ "CLOCK_PERIOD": 8
+ },
+ "scl::sky130_fd_sc_ls": {
+ "CLOCK_PERIOD": 10,
+ "SYNTH_MAX_FANOUT": 5
+ },
+ "scl::sky130_fd_sc_ms": {
+ "CLOCK_PERIOD": 10
+ }
+ },
+ "pdk::gf180mcuC": {
+ "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+ "CLOCK_PERIOD": 24.0,
+ "FP_CORE_UTIL": 40,
+ "RT_MAX_LAYER": "Metal4",
+ "SYNTH_MAX_FANOUT": 4,
+ "PL_TARGET_DENSITY": 0.45
+
+ }
+}
diff --git a/openlane/arbiterpuf/pin_order.cfg b/openlane/arbiterpuf/pin_order.cfg
new file mode 100644
index 0000000..dbb2d3c
--- /dev/null
+++ b/openlane/arbiterpuf/pin_order.cfg
@@ -0,0 +1,13 @@
+
+#S
+in.*
+
+clken
+rst
+#N
+io_.*
+ipulse
+ichallenge.*
+oresponse
+
+
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 370d74c..0838c0c 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -3,8 +3,8 @@
"DESIGN_IS_CORE": 0,
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
"CLOCK_PERIOD": 10,
- "CLOCK_PORT": "wb_clk_i",
- "CLOCK_NET": "counter.clk",
+ "CLOCK_PORT": "clk",
+ "CLOCK_NET": "clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 900 600",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
@@ -42,4 +42,4 @@
"SYNTH_MAX_FANOUT": 4,
"PL_TARGET_DENSITY": 0.45
}
-}
\ No newline at end of file
+}
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
index 2fda806..a2801ad 100644
--- a/openlane/user_proj_example/pin_order.cfg
+++ b/openlane/user_proj_example/pin_order.cfg
@@ -1,10 +1,155 @@
-#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
#S
wb_.*
wbs_.*
la_.*
-irq.*
+user_clock2
+user_irq.*
-#N
-io_.*
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..efa49e2 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -2,13 +2,13 @@
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
"CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2",
- "CLOCK_NET": "mprj.clk",
- "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
+ "CLOCK_PORT": "",
+ "CLOCK_NET": "puf1.ipulse",
+ "FP_PDN_MACRO_HOOKS": "puf1 vccd1 vssd1 vccd1 vssd1",
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+ "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/arbiterpuf.v"],
+ "EXTRA_LEFS": "dir::../../lef/arbiterpuf.lef",
+ "EXTRA_GDS_FILES": "dir::../../gds/arbiterpuf.gds",
"FP_PDN_CHECK_NODES": 0,
"SYNTH_ELABORATE_ONLY": 1,
"PL_RANDOM_GLB_PLACEMENT": 1,
@@ -81,5 +81,6 @@
"FP_PDN_CHECK_NODES": 0,
"MAGIC_WRITE_FULL_LEF": 0,
"FP_PDN_ENABLE_RAILS": 0
+
}
}
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..b5d0b80 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+puf1 1175 1690 N
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index c9632da..0592518 100644
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -36,6 +36,11 @@
io_in\[23\]
io_out\[23\]
io_oeb\[23\]
+#N
+
+ipulse
+ichallenge.*
+oresponse
#S
wb_.*
@@ -153,4 +158,4 @@
io_oeb\[36\]
io_in\[37\]
io_out\[37\]
-io_oeb\[37\]
\ No newline at end of file
+io_oeb\[37\]
