blob: 388070c76b8af0dc49086644159ce609c4f94460 [file] [log] [blame]
jeffdia089f252022-10-12 13:51:47 -07001{
2 "DESIGN_NAME": "user_project_wrapper",
jeffdib8e5cd62022-10-18 14:11:03 -07003 "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
jeffdia089f252022-10-12 13:51:47 -07004 "CLOCK_PERIOD": 10,
jeffdi3e9205b2022-10-12 17:17:16 -07005 "CLOCK_PORT": "user_clock2",
6 "CLOCK_NET": "mprj.clk",
7 "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
jeffdi32287c92022-10-17 17:24:50 -07008 "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
jeffdic0f115c2022-10-18 15:02:03 -07009 "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
10 "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
11 "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
jeffdi3e9205b2022-10-12 17:17:16 -070012 "FP_PDN_CHECK_NODES": 0,
jeffdib4d0b472022-10-12 17:27:10 -070013 "SYNTH_ELABORATE_ONLY": 1,
jeffdi3e9205b2022-10-12 17:17:16 -070014 "PL_RANDOM_GLB_PLACEMENT": 1,
15 "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
16 "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
17 "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
18 "FP_PDN_ENABLE_RAILS": 0,
19 "DIODE_INSERTION_STRATEGY": 0,
20 "FILL_INSERTION": 0,
21 "TAP_DECAP_INSERTION": 0,
22 "FP_PDN_VPITCH": 180,
23 "FP_PDN_HPITCH": 180,
24 "CLOCK_TREE_SYNTH": 0,
25 "FP_PDN_VOFFSET": 5,
26 "FP_PDN_HOFFSET": 5,
27 "MAGIC_ZEROIZE_ORIGIN": 0,
jeffdia089f252022-10-12 13:51:47 -070028 "FP_SIZING": "absolute",
jeffdi3e9205b2022-10-12 17:17:16 -070029 "RUN_CVC": 0,
30 "UNIT": 2.4,
jeffdi2c94e802022-10-12 17:25:45 -070031 "FP_IO_VEXTEND": "expr::2 * $UNIT",
32 "FP_IO_HEXTEND": "expr::2 * $UNIT",
jeffdi3e9205b2022-10-12 17:17:16 -070033 "FP_IO_VLENGTH": "ref::$UNIT",
34 "FP_IO_HLENGTH": "ref::$UNIT",
35 "FP_IO_VTHICKNESS_MULT": 4,
36 "FP_IO_HTHICKNESS_MULT": 4,
37 "FP_PDN_CORE_RING": 1,
38 "FP_PDN_CORE_RING_VWIDTH": 3.1,
39 "FP_PDN_CORE_RING_HWIDTH": 3.1,
40 "FP_PDN_CORE_RING_VOFFSET": 12.45,
41 "FP_PDN_CORE_RING_HOFFSET": 12.45,
Marwan Abbas0b646f62022-11-03 04:35:13 -070042 "FP_PDN_CORE_RING_VSPACING": 1.7,
43 "FP_PDN_CORE_RING_HSPACING": 1.7,
jeffdi3e9205b2022-10-12 17:17:16 -070044 "FP_PDN_VWIDTH": 3.1,
45 "FP_PDN_HWIDTH": 3.1,
jeffdi2c94e802022-10-12 17:25:45 -070046 "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
47 "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
jeffdi3e9205b2022-10-12 17:17:16 -070048 "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
49 "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
50 "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
jeffdia089f252022-10-12 13:51:47 -070051 "pdk::sky130*": {
jeffdi3e9205b2022-10-12 17:17:16 -070052 "RT_MAX_LAYER": "met4",
jeffdi480a8ae2022-10-24 20:02:21 -070053 "DIE_AREA": "0 0 2920 3520",
jeffdidc5a8a52022-10-24 20:01:03 -070054 "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
jeffdia089f252022-10-12 13:51:47 -070055 "scl::sky130_fd_sc_hd": {
56 "CLOCK_PERIOD": 10
57 },
58 "scl::sky130_fd_sc_hdll": {
59 "CLOCK_PERIOD": 10
60 },
61 "scl::sky130_fd_sc_hs": {
62 "CLOCK_PERIOD": 8
63 },
64 "scl::sky130_fd_sc_ls": {
65 "CLOCK_PERIOD": 10,
66 "SYNTH_MAX_FANOUT": 5
67 },
68 "scl::sky130_fd_sc_ms": {
69 "CLOCK_PERIOD": 10
70 }
jeffdi09aeb072022-10-17 14:38:07 -070071 },
jeffdia089f252022-10-12 13:51:47 -070072 "pdk::gf180mcuC": {
73 "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
jeffdi09aeb072022-10-17 14:38:07 -070074 "FP_PDN_CHECK_NODES": 0,
75 "FP_PDN_ENABLE_RAILS": 0,
76 "RT_MAX_LAYER": "Metal4",
77 "DIE_AREA": "0 0 3000 3000",
jeffdi88d9cbb2022-10-24 20:05:51 -070078 "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
jeffdi09aeb072022-10-17 14:38:07 -070079 "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
80 "DIODE_INSERTION_STRATEGY": 0,
81 "FP_PDN_CHECK_NODES": 0,
82 "MAGIC_WRITE_FULL_LEF": 0,
jeffdi500560a2022-10-17 15:00:19 -070083 "FP_PDN_ENABLE_RAILS": 0
jeffdi09aeb072022-10-17 14:38:07 -070084 }
jeffdia089f252022-10-12 13:51:47 -070085}