jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 1 | { |
| 2 | "DESIGN_NAME": "user_project_wrapper", |
jeffdi | b8e5cd6 | 2022-10-18 14:11:03 -0700 | [diff] [blame] | 3 | "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"], |
jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 4 | "CLOCK_PERIOD": 10, |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 5 | "CLOCK_PORT": "user_clock2", |
| 6 | "CLOCK_NET": "mprj.clk", |
| 7 | "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1", |
jeffdi | 32287c9 | 2022-10-17 17:24:50 -0700 | [diff] [blame] | 8 | "MACRO_PLACEMENT_CFG": "dir::macro.cfg", |
jeffdi | c0f115c | 2022-10-18 15:02:03 -0700 | [diff] [blame] | 9 | "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"], |
| 10 | "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef", |
| 11 | "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds", |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 12 | "FP_PDN_CHECK_NODES": 0, |
jeffdi | b4d0b47 | 2022-10-12 17:27:10 -0700 | [diff] [blame] | 13 | "SYNTH_ELABORATE_ONLY": 1, |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 14 | "PL_RANDOM_GLB_PLACEMENT": 1, |
| 15 | "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0, |
| 16 | "PL_RESIZER_TIMING_OPTIMIZATIONS": 0, |
| 17 | "PL_RESIZER_BUFFER_INPUT_PORTS": 0, |
| 18 | "FP_PDN_ENABLE_RAILS": 0, |
| 19 | "DIODE_INSERTION_STRATEGY": 0, |
| 20 | "FILL_INSERTION": 0, |
| 21 | "TAP_DECAP_INSERTION": 0, |
| 22 | "FP_PDN_VPITCH": 180, |
| 23 | "FP_PDN_HPITCH": 180, |
| 24 | "CLOCK_TREE_SYNTH": 0, |
| 25 | "FP_PDN_VOFFSET": 5, |
| 26 | "FP_PDN_HOFFSET": 5, |
| 27 | "MAGIC_ZEROIZE_ORIGIN": 0, |
jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 28 | "FP_SIZING": "absolute", |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 29 | "RUN_CVC": 0, |
| 30 | "UNIT": 2.4, |
jeffdi | 2c94e80 | 2022-10-12 17:25:45 -0700 | [diff] [blame] | 31 | "FP_IO_VEXTEND": "expr::2 * $UNIT", |
| 32 | "FP_IO_HEXTEND": "expr::2 * $UNIT", |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 33 | "FP_IO_VLENGTH": "ref::$UNIT", |
| 34 | "FP_IO_HLENGTH": "ref::$UNIT", |
| 35 | "FP_IO_VTHICKNESS_MULT": 4, |
| 36 | "FP_IO_HTHICKNESS_MULT": 4, |
| 37 | "FP_PDN_CORE_RING": 1, |
| 38 | "FP_PDN_CORE_RING_VWIDTH": 3.1, |
| 39 | "FP_PDN_CORE_RING_HWIDTH": 3.1, |
| 40 | "FP_PDN_CORE_RING_VOFFSET": 12.45, |
| 41 | "FP_PDN_CORE_RING_HOFFSET": 12.45, |
Marwan Abbas | 0b646f6 | 2022-11-03 04:35:13 -0700 | [diff] [blame^] | 42 | "FP_PDN_CORE_RING_VSPACING": 1.7, |
| 43 | "FP_PDN_CORE_RING_HSPACING": 1.7, |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 44 | "FP_PDN_VWIDTH": 3.1, |
| 45 | "FP_PDN_HWIDTH": 3.1, |
jeffdi | 2c94e80 | 2022-10-12 17:25:45 -0700 | [diff] [blame] | 46 | "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)", |
| 47 | "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)", |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 48 | "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"], |
| 49 | "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"], |
| 50 | "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS", |
jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 51 | "pdk::sky130*": { |
jeffdi | 3e9205b | 2022-10-12 17:17:16 -0700 | [diff] [blame] | 52 | "RT_MAX_LAYER": "met4", |
jeffdi | 480a8ae | 2022-10-24 20:02:21 -0700 | [diff] [blame] | 53 | "DIE_AREA": "0 0 2920 3520", |
jeffdi | dc5a8a5 | 2022-10-24 20:01:03 -0700 | [diff] [blame] | 54 | "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def", |
jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 55 | "scl::sky130_fd_sc_hd": { |
| 56 | "CLOCK_PERIOD": 10 |
| 57 | }, |
| 58 | "scl::sky130_fd_sc_hdll": { |
| 59 | "CLOCK_PERIOD": 10 |
| 60 | }, |
| 61 | "scl::sky130_fd_sc_hs": { |
| 62 | "CLOCK_PERIOD": 8 |
| 63 | }, |
| 64 | "scl::sky130_fd_sc_ls": { |
| 65 | "CLOCK_PERIOD": 10, |
| 66 | "SYNTH_MAX_FANOUT": 5 |
| 67 | }, |
| 68 | "scl::sky130_fd_sc_ms": { |
| 69 | "CLOCK_PERIOD": 10 |
| 70 | } |
jeffdi | 09aeb07 | 2022-10-17 14:38:07 -0700 | [diff] [blame] | 71 | }, |
jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 72 | "pdk::gf180mcuC": { |
| 73 | "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
jeffdi | 09aeb07 | 2022-10-17 14:38:07 -0700 | [diff] [blame] | 74 | "FP_PDN_CHECK_NODES": 0, |
| 75 | "FP_PDN_ENABLE_RAILS": 0, |
| 76 | "RT_MAX_LAYER": "Metal4", |
| 77 | "DIE_AREA": "0 0 3000 3000", |
jeffdi | 88d9cbb | 2022-10-24 20:05:51 -0700 | [diff] [blame] | 78 | "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def", |
jeffdi | 09aeb07 | 2022-10-17 14:38:07 -0700 | [diff] [blame] | 79 | "PL_OPENPHYSYN_OPTIMIZATIONS": 0, |
| 80 | "DIODE_INSERTION_STRATEGY": 0, |
| 81 | "FP_PDN_CHECK_NODES": 0, |
| 82 | "MAGIC_WRITE_FULL_LEF": 0, |
jeffdi | 500560a | 2022-10-17 15:00:19 -0700 | [diff] [blame] | 83 | "FP_PDN_ENABLE_RAILS": 0 |
jeffdi | 09aeb07 | 2022-10-17 14:38:07 -0700 | [diff] [blame] | 84 | } |
jeffdi | a089f25 | 2022-10-12 13:51:47 -0700 | [diff] [blame] | 85 | } |