tree: 7f53f735b72eb03fbdb4916acb317643596aa857 [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. configure.py
  17. info.yaml
  18. LICENSE
  19. Makefile
  20. README.md
README.md

Tiny User Project

Template for submitting TinyTapeout based projects to the Open MPW shuttle program.

Usage

  1. Generate a new project based on this template.

  2. Set GitHub Pages Sources as GitHub Actions.

  3. If using Wokwi:

    • Reuse or create a new Wokwi project.
    • Edit info.yaml:
      • In project:
        • Update wokwi_id with the last component of the Wokwi URL.
      • In documentation:
        • Update inputs to document the input wire of your project.
        • Update outputs to document the output wire of your project.
  4. If using Verilog:

    • Add your HDL code in verilog/rtl/.
    • Edit info.yaml:
      • In project:
        • Set wokwi_id to 0.
        • Uncomment and update top_module to match your top-level module.
        • Uncomment and list your Verilog sources in src_files (paths relative to the root of the repository).
      • In documentation:
        • Update inputs to document the input wire of your top-level module.
        • Update outputs to document the output wire of your top-level module.
  5. Commit, push and check the user_project_ci workflow summary (if successful a new commit including the hardened files will be automatically created).

  6. Submit your project github repository to the next Open MPW shuttle.