Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-034 / a1ae4f91c12da4bd7348a932ab44acfa98da5449
commita1ae4f91c12da4bd7348a932ab44acfa98da5449[log] [tgz]
authorm-usama-z <107983847+m-usama-z@users.noreply.github.com>Sat Nov 26 15:55:35 2022 +0500
committerGitHub <noreply@github.com>Sat Nov 26 15:55:35 2022 +0500
tree68dac5d34d1f2b9a00cfea2b49517f47aca827aa
parent5b0d2f0829ba44a5e2539dc7f558e7fe1af10320 [diff]
Update README.md
1 file changed
tree: 68dac5d34d1f2b9a00cfea2b49517f47aca827aa
  1. .github/
  2. def/
  3. dependencies/
  4. deps/
  5. docs/
  6. gds/
  7. lef/
  8. lib/
  9. mag/
  10. maglef/
  11. openlane/
  12. sdc/
  13. sdf/
  14. signoff/
  15. spef/
  16. spi/
  17. venv/
  18. verilog/
  19. caravel
  20. mgmt_core_wrapper
  21. .gitignore
  22. LICENSE
  23. Makefile
  24. README.md
README.md

UETRV_ESoC_v2

UETRV_ECORE_v2 is a RISC-V based SoC derived from UETRV_ESoC with a few changes. UETRV_ESoC_v2 has been passed through the Cadence VLSI flow for submission to Google and Efabless' Open MPW-8 shuttle program using Skywater‘s open-source 130 nm PDK (the project can be found on Efabless’ website here). The verilog RTL used in this repo is generated from Scala source, available here. Further details about the peripheral memory map, bootloader, example programs, testbenches etc. are also provided in that repo.

Updates from UETRV_ESoC

The following are the differences between UETRV_ESoC_v2 and UETRV_ESoC:

  • Fixed width of address bus in the instruction bus. Previously, the address bus was 2 bits narrower than required for the instruction memory size specified in the config.scala file.
  • Fixed selection of the motor control module to be accessed using the address given to data bus. Previously, although three motor control modules were instantiated, only the first motor module was accessible.
  • Fixed data memory to be word-addressable. Previously, data memory was byte-addressable which did not map properly to the Skywater PDK's SRAMs.
  • Added 2 inputs and 2 outputs to the motor control module, to aid in controlling stepper motors for a plotter's operation. The 2 inputs have been used to read the state of homing switches, and the 2 outputs have been used to provide the direction inputs to the stepper motor driver, but this usage of the IOs been done using firmware, thus they can be easily used for other purposes by modifying the firmware written in C language.
  • Increased instruction memory size to 8 KB and data memory size to 4 KB. As shown in the image below, the 4 lower SRAMs constitute the instruction memory and the 2 upper SRAMs constitute the data memory.

Testbench

The io_ports testbench provided in the caravel_user_project template configures and tests GPIOs' functionality. It has been merged with UETRV_ESoC‘s testbench (old_tb), resulting in io_ports_tb.v. This testbench runs full chip simulation by configuring the GPIOs using firmware for caravel’s management SoC, then it loads a program into UETRV_ESoC_v2 over GPIOs configured for SPI, then a sample firmware program transmits characters over UART. These characters are fed back to UETRV_ESoC_v2 by UART loopback. Some of these characters are commands for moving a plotter's pen as described below:

  • ‘u’ to move pen up in 2D-grid
  • ‘d’ for down
  • ‘l’ for left
  • ‘r’ for right
  • ‘L’ for lifting the pen
  • ‘D’ for dropping the pen

The testbench waits for each command to occur and verifies that the step and direction outputs for stepper motors, and the PWM output for the servo motor lifting and dropping the pen, have changed properly.