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foss-eda-tools/third_party/shuttle/sky130/mpw-008/slot-034/HEAD/./verilog/gl
tree: 9a445eaf099980cf5194aabf21e067f700819abd [path history] [tgz]
  1. SoC_Tile_for_backend_rtl_with_power_ports.v
  2. SoC_Tile_netlist.sim_gl_for_user_project_wrapper.v
  3. user_proj_example.v
  4. user_project_wrapper.nl.v
  5. user_project_wrapper.v
  6. user_project_wrapper.v.old
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