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## Testbench
-The io_ports testbench provided in the caravel_user_project template configures and tests GPIOs' functionality. It has been merged with UETRV_ESoC's testbench ([old_tb](https://github.com/ee-uet/UETRV_ESoC/blob/main/tb/SoC_tb.v)), resulting in [io_ports_tb.v](verilog/dv/io_ports/io_ports_tb.v). This testbench runs full chip simulation by configuring the GPIOs using firmware for caravel's management SoC. Following this, reset is applied which causes UETRV_ESoC_v2 to run its bootloader. The testbench mimics an SPI-based flash memory and loads a firmware into UETRV_ESoC_v2's instruction memory over GPIOs configured for SPI, in conjunction with the bootloader. Once loading of firmware is finished, the bootloader hands control over to the firmware. The firmware program transmits characters over UART, which are fed back to UETRV_ESoC_v2 by UART loopback. Some of these characters are commands for moving a plotter's pen as described below:
+The io_ports testbench provided in the caravel_user_project template configures and tests GPIOs' functionality. It has been merged with UETRV_ESoC's testbench ([old tb](https://github.com/ee-uet/UETRV_ESoC/blob/main/tb/SoC_tb.v)), resulting in [io_ports_tb.v](verilog/dv/io_ports/io_ports_tb.v). This testbench runs full chip simulation by configuring the GPIOs using firmware for caravel's management SoC. Following this, reset is applied which causes UETRV_ESoC_v2 to run its bootloader. The testbench mimics an SPI-based flash memory and loads a firmware into UETRV_ESoC_v2's instruction memory over GPIOs configured for SPI, in conjunction with the bootloader. Once loading of firmware is finished, the bootloader hands control over to the firmware. The firmware program transmits characters over UART, which are fed back to UETRV_ESoC_v2 by UART loopback. Some of these characters are commands for moving a plotter's pen as described below:
- 'u' to move pen up in 2D-grid
- 'd' to move pen down in 2D-grid
