verilog/rtl/tiny_user_project.v.jinja2

// Copyright 2022 Google LLC.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none

// tiny_user_project top module instance
// generated by configure.py
module tiny_user_project(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,
);

// pass input and output pins defined in user_defines.v
{{ module_name }} mod (
    io_in[{{ io_in_range[1] - 1 }}:{{ io_in_range[0] }}],
    io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}]
);
// all output enabled
assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 8'b0;

endmodule	// tiny_user_project

`default_nettype wire