| # PPCPU |
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| Submission of [pipelined pcpu](https://github.com/piotro888/ppcpu) to openMPW shuttle. |
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| `Edition: MPW-8` |
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| ## About ppcpu |
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| `ppcpu` is a 16-bit RISC processor, with designed from scratch architecture. This is 3rd(.1) revision of processor, which started as little project back in 2020. |
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| This is version 2.2 of ppcpu with many improvements and two cores. |
| |
| ## Features |
| * Outside bus interface for memory and devices |
| * 2 cores |
| * Instruction and data caches |
| * Custom PCPU ISA |
| * Memory paging |
| * 4 stage pipeline |
| * Microcontroller mode with intergrated memory |
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| ## Tests |
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| Boot tests are is included in `verilog/dv/`. |
| See README in this directory for description of testbenches |
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| Rest of tests for cpu and ISA are included in `ppcpu` repo. |
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| ## Docs |
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| For ISA docs see `pcpu` and `ppcpu` repositories. |
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| ## License |
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| See `LICENSE` file |
