Add tests!
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 3a6a8b4..13bf0dc 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -20,7 +20,7 @@
#.SILENT: clean all
-PATTERNS = boot_cw
+PATTERNS = boot_cw boot_cw_split boot_embed
all: ${PATTERNS}
diff --git a/verilog/dv/boot_cw/boot_cw.c b/verilog/dv/boot_cw/boot_cw.c
index a130d2d..c81dfe9 100644
--- a/verilog/dv/boot_cw/boot_cw.c
+++ b/verilog/dv/boot_cw/boot_cw.c
@@ -22,11 +22,53 @@
void main()
{
- // reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- // reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- // reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+ reg_la0_data = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
- // while (reg_mprj_xfer == 1);
- // for(;;);
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_uart_enable = 0;
+
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+ reg_la0_data = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
}
diff --git a/verilog/dv/boot_cw/boot_cw_tb.v b/verilog/dv/boot_cw/boot_cw_tb.v
index 74f3e5a..4bb6d07 100644
--- a/verilog/dv/boot_cw/boot_cw_tb.v
+++ b/verilog/dv/boot_cw/boot_cw_tb.v
@@ -59,7 +59,7 @@
assign mprj_io[CW_PIN_OFF+17:CW_PIN_OFF+2] = (cw_dir ? cw_io_i : 16'hZZZZ);
assign mprj_io[CW_PIN_OFF+18] = cw_ack;
assign mprj_io[CW_PIN_OFF+19] = cw_err;
- assign cw_clk = mprj_io[CW_PIN_OFF+20];
+ assign cw_clk = mprj_io[CW_PIN_OFF+29];
assign cw_rst = mprj_io[CW_PIN_OFF+21];
reg ext_irq, split_clk, core_disable, embed_mode;
@@ -316,10 +316,14 @@
initial begin
$dumpfile("boot_cw.vcd");
- $dumpvars(0, boot_cw_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (1) begin
+ repeat (33) begin // core sets up gpio at ~ 38k cycles
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $dumpvars(2, boot_cw_tb.uut.mprj);
+ repeat (5) begin // core sets up gpio at ~ 38k cycles
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
@@ -333,8 +337,8 @@
$finish;
end
- always @({mprj_io[37:CW_PIN_OFF+21],mprj_io[CW_PIN_OFF+19:0]}) begin //exclude clk
- #1 $display("MPRJ-IO state = %b ", mprj_io[31:0]);
+ always @(mprj_io[36:8]) begin //exclude clk
+ #1 $display("MPRJ-IO state = %b ", mprj_io[37:8]);
end
initial begin
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/boot_cw_split/Makefile
similarity index 99%
rename from verilog/dv/io_ports/Makefile
rename to verilog/dv/boot_cw_split/Makefile
index 3fd0b56..444c58b 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/boot_cw_split/Makefile
@@ -14,8 +14,6 @@
#
# SPDX-License-Identifier: Apache-2.0
-
-
PWDD := $(shell pwd)
BLOCKS := $(shell basename $(PWDD))
diff --git a/verilog/dv/boot_cw_split/boot_cw_split.c b/verilog/dv/boot_cw_split/boot_cw_split.c
new file mode 100644
index 0000000..c81dfe9
--- /dev/null
+++ b/verilog/dv/boot_cw_split/boot_cw_split.c
@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+
+void main()
+{
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+ reg_la0_data = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
+
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_uart_enable = 0;
+
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+ reg_la0_data = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
+}
+
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/boot_cw_split/boot_cw_split_tb.v
similarity index 77%
rename from verilog/dv/la_test1/la_test1_tb.v
rename to verilog/dv/boot_cw_split/boot_cw_split_tb.v
index 6aeceb1..4226b9d 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/boot_cw_split/boot_cw_split_tb.v
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Piotr Wegrzyn
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -13,11 +13,19 @@
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
+/*
+ CW BOOT TEST
+
+ Boots core in CW mode, monitors CW bus pins and inserts fixed instruction to see if CW outside
+ communication works correctly
+
+*/
+
`default_nettype none
`timescale 1 ns / 1 ps
-module la_test1_tb;
+module boot_cw_split_tb;
reg clock;
reg RSTB;
reg CSB;
@@ -25,12 +33,7 @@
reg power1, power2;
wire gpio;
- wire uart_tx;
wire [37:0] mprj_io;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
always #12.5 clock <= (clock === 1'b0);
@@ -38,6 +41,119 @@
clock = 0;
end
+
+ // CW PINS
+ reg [15:0] cw_io_i;
+ wire [15:0] cw_io_o;
+ wire cw_req;
+ wire cw_dir;
+ reg cw_ack;
+ reg cw_err;
+ wire cw_clk;
+ wire cw_rst;
+
+ localparam CW_PIN_OFF=8;
+ assign cw_req = mprj_io[CW_PIN_OFF+0];
+ assign cw_dir = mprj_io[CW_PIN_OFF+1];
+ assign cw_io_o = mprj_io[CW_PIN_OFF+17:CW_PIN_OFF+2];
+ assign mprj_io[CW_PIN_OFF+17:CW_PIN_OFF+2] = (cw_dir ? cw_io_i : 16'hZZZZ);
+ assign mprj_io[CW_PIN_OFF+18] = cw_ack;
+ assign mprj_io[CW_PIN_OFF+19] = cw_err;
+ assign cw_clk = mprj_io[CW_PIN_OFF+29];
+ assign cw_rst = mprj_io[CW_PIN_OFF+21];
+
+ reg ext_irq, split_clk, core_disable, embed_mode;
+ reg spi_clk, spi_mosi;
+ wire spi_miso;
+ assign mprj_io[CW_PIN_OFF+22] = ext_irq;
+ assign mprj_io[CW_PIN_OFF+23] = split_clk;
+ assign mprj_io[CW_PIN_OFF+24] = core_disable;
+ assign mprj_io[CW_PIN_OFF+25] = embed_mode;
+ assign mprj_io[CW_PIN_OFF+26] = spi_clk;
+ assign mprj_io[CW_PIN_OFF+27] = spi_mosi;
+ assign spi_miso = mprj_io[CW_PIN_OFF+28];
+
+ initial begin
+ cw_ack <= 0;
+ cw_err <= 0;
+ ext_irq <= 0;
+ split_clk <= 1;
+ core_disable <= 0;
+ embed_mode <= 0;
+ spi_clk <= 1;
+ spi_mosi <= 0;
+ cw_io_i <= 0;
+ end
+
+ /*
+ * THE TEST
+ */
+ initial begin
+ $display("Start test");
+ $display("Waiting for CW request");
+ wait(cw_req);
+ wait(cw_io_o == 16'hff17); // 0xff addr high part + read req with 4 burst
+ wait(cw_io_o == 16'he000); // addr low part
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ // respond with jump to 0x0100
+ $display("Waiting for direction");
+ wait(cw_dir == 1'b1);
+ cw_io_i <= 16'h000e;
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_io_i <= 16'h0100;
+ cw_ack <= 1'b1;
+ // nops
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ $display("first instr fetched");
+
+ // simulate memory write instruction
+ wait(cw_req == 1'b1);
+ wait(cw_io_o == 16'hff17);
+ wait(cw_io_o == 16'he200); // assert addr after jump
+ $display("addr verified");
+ cw_ack <= 1'b1;
+ @(posedge cw_clk);
+ cw_ack <= 1'b0;
+ @(posedge cw_clk);
+ @(posedge cw_clk);
+ wait(cw_dir);
+ $finish;
+ end
+
+ /*
+ * TB INIT STUFF by Efabless
+ */
+
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
@@ -136,13 +252,17 @@
// assign mprj_io[3] = 1'b1;
initial begin
- $dumpfile("la_test1.vcd");
- $dumpvars(0, la_test1_tb);
+ $dumpfile("boot_cw_split.vcd");
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (250) begin
+ repeat (33) begin
repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
+ $display("+1000 cycles");
+ end
+ $dumpvars(0, boot_cw_split_tb);
+ repeat (8) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
@@ -154,14 +274,8 @@
$finish;
end
- initial begin
- wait(checkbits == 16'hAB40);
- $display("LA Test 1 started");
- wait(checkbits == 16'hAB41);
- wait(checkbits == 16'hAB51);
- $display("LA Test 2 passed");
- #10000;
- $finish;
+ always @({mprj_io[37:CW_PIN_OFF+21],mprj_io[CW_PIN_OFF+19:0]}) begin //exclude clk
+ #1 $display("MPRJ-IO state = %b ", mprj_io[37:8]);
end
initial begin
@@ -228,7 +342,7 @@
);
spiflash #(
- .FILENAME("la_test1.hex")
+ .FILENAME("boot_cw_split.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
@@ -238,10 +352,5 @@
.io3() // not used
);
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
endmodule
`default_nettype wire
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/boot_embed/Makefile
similarity index 99%
copy from verilog/dv/io_ports/Makefile
copy to verilog/dv/boot_embed/Makefile
index 3fd0b56..444c58b 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/boot_embed/Makefile
@@ -14,8 +14,6 @@
#
# SPDX-License-Identifier: Apache-2.0
-
-
PWDD := $(shell pwd)
BLOCKS := $(shell basename $(PWDD))
diff --git a/verilog/dv/boot_embed/boot_embed.c b/verilog/dv/boot_embed/boot_embed.c
new file mode 100644
index 0000000..8fd3964
--- /dev/null
+++ b/verilog/dv/boot_embed/boot_embed.c
@@ -0,0 +1,78 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+
+void main()
+{
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+ reg_la0_data = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
+
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_uart_enable = 0;
+
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+ reg_la0_data = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
+}
+
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/boot_embed/boot_embed_tb.v
similarity index 69%
copy from verilog/dv/la_test1/la_test1_tb.v
copy to verilog/dv/boot_embed/boot_embed_tb.v
index 6aeceb1..a70b298 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/boot_embed/boot_embed_tb.v
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2020 Piotr Wegrzyn
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -13,11 +13,19 @@
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
+/*
+ CW BOOT TEST
+
+ Boots core in CW mode, monitors CW bus pins and inserts fixed instruction to see if CW outside
+ communication works correctly
+
+*/
+
`default_nettype none
`timescale 1 ns / 1 ps
-module la_test1_tb;
+module boot_embed_tb;
reg clock;
reg RSTB;
reg CSB;
@@ -25,12 +33,7 @@
reg power1, power2;
wire gpio;
- wire uart_tx;
wire [37:0] mprj_io;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
always #12.5 clock <= (clock === 1'b0);
@@ -38,6 +41,152 @@
clock = 0;
end
+
+ // CW PINS
+ reg [15:0] cw_io_i;
+ wire [15:0] cw_io_o;
+ wire cw_req;
+ wire cw_dir;
+ reg cw_ack;
+ reg cw_err;
+ wire cw_clk;
+ wire cw_rst;
+ wire [1:0] gpio2in = 2'b10;
+
+ assign mprj_io[5:4] = gpio2in;
+ localparam CW_PIN_OFF=8;
+ assign cw_req = mprj_io[CW_PIN_OFF+0];
+ assign cw_dir = mprj_io[CW_PIN_OFF+1];
+ assign cw_io_o = mprj_io[CW_PIN_OFF+17:CW_PIN_OFF+2];
+ assign mprj_io[CW_PIN_OFF+17:CW_PIN_OFF+2] = (cw_dir ? cw_io_i : 16'hZZZZ);
+ assign mprj_io[CW_PIN_OFF+18] = cw_ack;
+ assign mprj_io[CW_PIN_OFF+19] = cw_err;
+ assign cw_clk = mprj_io[CW_PIN_OFF+29];
+ assign cw_rst = mprj_io[CW_PIN_OFF+21];
+
+ reg ext_irq, split_clk, core_disable, embed_mode;
+ reg spi_clk, spi_mosi;
+ wire spi_miso;
+ assign mprj_io[CW_PIN_OFF+22] = ext_irq;
+ assign mprj_io[CW_PIN_OFF+23] = split_clk;
+ assign mprj_io[CW_PIN_OFF+24] = core_disable;
+ assign mprj_io[CW_PIN_OFF+25] = embed_mode;
+ assign mprj_io[CW_PIN_OFF+26] = spi_clk;
+ assign mprj_io[CW_PIN_OFF+27] = spi_mosi;
+ assign spi_miso = mprj_io[CW_PIN_OFF+28];
+
+ initial begin
+ cw_ack <= 0;
+ cw_err <= 0;
+ ext_irq <= 0;
+ split_clk <= 0;
+ core_disable <= 1;
+ embed_mode <= 1;
+ spi_clk <= 1;
+ spi_mosi <= 1;
+ cw_io_i <= 0;
+
+ end
+ integer i;
+ task spi_tx (input [23:0] addr, input [15:0] data);
+ begin
+ $display("spi_tx: addr=%h data=%h", addr, data);
+ spi_mosi <= 1'b0;
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+
+ for (i=0; i<24; i=i+1) begin
+ spi_mosi <= addr[i];
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock); end
+ spi_mosi <= 1'b1; // we
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+ for (i=0; i<16; i=i+1) begin
+ spi_mosi <= data[i];
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+ end
+ spi_mosi <= 1'b1; // idle
+
+ while (spi_miso) begin // wait for end
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+ end
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+ end
+ endtask
+
+ reg gpio_release = 0;
+
+ /*
+ * THE TEST
+ */
+ initial begin
+ $display("Start test");
+ $dumpfile("boot_embed.vcd");
+ // wait for gpio init
+ wait(cw_rst);
+ wait(~cw_rst);
+ $dumpvars(0, boot_embed_tb);
+ $display("cw_rst: start spi load");
+ gpio_release <= 1'b1;
+
+ // init cycles
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+ spi_clk <= 1'b1; @(posedge clock); @(posedge clock); spi_clk <= 1'b0; @(posedge clock); @(posedge clock);
+
+ // load program from test.s file
+ // explained there
+ spi_tx(24'h800000, 16'h000e);
+ spi_tx(24'h800001, 16'h0010);
+ spi_tx(24'h800002, 16'h000e);
+ spi_tx(24'h800003, 16'h0001);
+
+ spi_tx(24'h800020, 16'h0004);
+ spi_tx(24'h800021, 16'h3888);
+ spi_tx(24'h800022, 16'h0005);
+ spi_tx(24'h800023, 16'h0400);
+
+ spi_tx(24'h800024, 16'h0004);
+ spi_tx(24'h800025, 16'h0003);
+ spi_tx(24'h800026, 16'h0011);
+ spi_tx(24'h800027, 16'h0001);
+ spi_tx(24'h800028, 16'h0004);
+ spi_tx(24'h800029, 16'h0002);
+ spi_tx(24'h80002a, 16'h0011);
+ spi_tx(24'h80002b, 16'h0200);
+
+ spi_tx(24'h80002c, 16'h0004);
+ spi_tx(24'h80002d, 16'h00f8);
+ spi_tx(24'h80002e, 16'h0005);
+ spi_tx(24'h80002f, 16'h0024);
+ spi_tx(24'h800030, 16'h0004);
+ spi_tx(24'h800031, 16'h0005);
+ spi_tx(24'h800032, 16'h0005);
+ spi_tx(24'h800033, 16'h0022);
+ spi_tx(24'h800034, 16'h0002);
+ spi_tx(24'h800035, 16'h0020);
+ spi_tx(24'h800036, 16'h0024);
+ spi_tx(24'h800037, 16'h0004);
+ spi_tx(24'h800038, 16'h0005);
+ spi_tx(24'h800039, 16'h0022);
+ $display("spi_load_finished");
+
+ // enable the core
+ core_disable <= 0;
+
+ // wait for gpio state
+ wait(mprj_io[2:0] == 3'b101);
+ $display("gpio pass 1");
+ wait(mprj_io[1:0] == 2'b10); // shifted input [5:4]
+ $display("gpio pass 2");
+ // todo: check spi load
+ @(posedge clock); @(posedge clock);
+ @(posedge clock); @(posedge clock);
+
+ $finish;
+ end
+
+ /*
+ * TB INIT STUFF by Efabless
+ */
+
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
@@ -136,14 +285,14 @@
// assign mprj_io[3] = 1'b1;
initial begin
- $dumpfile("la_test1.vcd");
- $dumpvars(0, la_test1_tb);
+
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (250) begin
+ repeat (50) begin // mgmt core sets up gpio at ~ 38k cycles
repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
+ $display("+1000 cycles");
end
+
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test LA (GL) Failed");
@@ -154,16 +303,10 @@
$finish;
end
- initial begin
- wait(checkbits == 16'hAB40);
- $display("LA Test 1 started");
- wait(checkbits == 16'hAB41);
- wait(checkbits == 16'hAB51);
- $display("LA Test 2 passed");
- #10000;
- $finish;
+ always @(mprj_io[36:8]) begin //exclude clk
+ #1 $display("MPRJ-IO state = %b ", mprj_io[37:8]);
end
-
+
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
@@ -195,8 +338,8 @@
assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign mprj_io[3] = 1; // Force CSB high.
- assign mprj_io[0] = 0; // Disable debug mode
+ assign mprj_io[3] = (gpio_release ? 1'bz : 1); // Force CSB high.
+ assign mprj_io[0] = (gpio_release ? 1'bz : 0); // Disable debug mode
caravel uut (
.vddio (VDD3V3),
@@ -228,7 +371,7 @@
);
spiflash #(
- .FILENAME("la_test1.hex")
+ .FILENAME("boot_embed.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
@@ -238,10 +381,5 @@
.io3() // not used
);
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
endmodule
`default_nettype wire
diff --git a/verilog/dv/boot_embed/hex2 b/verilog/dv/boot_embed/hex2
new file mode 100644
index 0000000..c6f4844
--- /dev/null
+++ b/verilog/dv/boot_embed/hex2
@@ -0,0 +1,16 @@
+:040000000010000EDE
+:040001000001000EEC
+:040010003888000428
+:0400110004000005E2
+:0400120000030004E3
+:0400130000010011D7
+:0400140000020004E2
+:0400150002000011D4
+:0400160000070004DB
+:0400170000240005BC
+:0400180000050004DB
+:04001900 0022 0005
+:04001A00 0020 0002
+:04001B00 0004 0024
+:04001C00 0022 0005
+:00000001FF
diff --git a/verilog/dv/boot_embed/hex3 b/verilog/dv/boot_embed/hex3
new file mode 100644
index 0000000..564ecb1
--- /dev/null
+++ b/verilog/dv/boot_embed/hex3
@@ -0,0 +1,16 @@
+:040000000010000EDE
+:040001000001000EEC
+:040010003888000428
+:0400110004000005E2
+:0400120000030004E3
+:0400130000010011D7
+:0400140000020004E2
+:0400150002000011D4
+:0400160000F80004EA
+:0400170000240005BC
+:0400180000050004DB
+:0400190000220005BC
+:04001A0000200002C0
+:04001B0000040024B9
+:04001C0000220005B9
+:00000001FF
diff --git a/verilog/dv/boot_embed/test.s b/verilog/dv/boot_embed/test.s
new file mode 100644
index 0000000..0f7cb0a
--- /dev/null
+++ b/verilog/dv/boot_embed/test.s
@@ -0,0 +1,24 @@
+jmp test
+loop:
+jmp loop
+
+.org 0x10
+test:
+; simple store to embed ram
+ldi r0, 0x3888
+std r0, 0x0400
+
+; setup paging
+ldi r0, 0b0011
+srs r0, 1
+ldi r0, 2 ; 0x002xxx => 0x0xxx
+srs r0, 0x200
+
+; gpio test
+ldi r0, 0b11111000
+std r0, 0x024 ; direction
+ldi r0, 0b101
+std r0, 0x022 ; set
+ldd r0, 0x020 ; read
+sri r0, r0, 4
+std r0, 0x022
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
deleted file mode 100644
index d204e4a..0000000
--- a/verilog/dv/io_ports/io_ports.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-/*
- IO Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
-void main()
-{
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
-
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- // reg_spi_enable = 1;
- // reg_spimaster_cs = 0x10001;
- // reg_spimaster_control = 0x0801;
-
- // reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- // Configure lower 8-IOs as user output
- // Observe counter value in the testbench
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-}
-
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
deleted file mode 100644
index 0ccc511..0000000
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module io_ports_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
-
- assign mprj_io_0 = mprj_io[7:0];
- // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = 1'b1;
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
-
- `ifdef ENABLE_SDF
- initial begin
- $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
- $sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
- $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
- $sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
- $sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
- $sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
- $sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
- $sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
- $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
- end
- `endif
-
- initial begin
- $dumpfile("io_ports.vcd");
- $dumpvars(0, io_ports_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (25) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- // Observe Output pins [7:0]
- wait(mprj_io_0 == 8'h01);
- wait(mprj_io_0 == 8'h02);
- wait(mprj_io_0 == 8'h03);
- wait(mprj_io_0 == 8'h04);
- wait(mprj_io_0 == 8'h05);
- wait(mprj_io_0 == 8'h06);
- wait(mprj_io_0 == 8'h07);
- wait(mprj_io_0 == 8'h08);
- wait(mprj_io_0 == 8'h09);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'hFF);
- wait(mprj_io_0 == 8'h00);
-
- `ifdef GL
- $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
- `else
- $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
- `endif
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #3_00_000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
- power1 <= 1'b1;
- #100;
- power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("io_ports.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/io_ports/verify.log b/verilog/dv/io_ports/verify.log
deleted file mode 100644
index f166328..0000000
--- a/verilog/dv/io_ports/verify.log
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile:30: /verilog/dv/make/sim.makefile: No such file or directory
-make: *** No rule to make target '/verilog/dv/make/sim.makefile'. Stop.
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/la_test1/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
deleted file mode 100644
index cad69d1..0000000
--- a/verilog/dv/la_test1/la_test1.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-// --------------------------------------------------------
-
-/*
- MPRJ Logic Analyzer Test:
- - Observes counter value through LA probes [31:0]
- - Sets counter initial value through LA probes [63:32]
- - Flags when counter value exceeds 500 through the management SoC gpio
- - Outputs message to the UART when the test concludes successfuly
-*/
-
-void main()
-{
- int j;
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- // reg_spi_enable = 1;
- // reg_spimaster_cs = 0x00000;
-
- // reg_spimaster_control = 0x0801;
-
- // reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flad the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- // reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- // Now, apply the configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0x00000000;
-
- while (1) {
- if (reg_la0_data_in > 0x1F4) {
- reg_mprj_datal = 0xAB410000;
- break;
- }
- }
- print("\n");
- print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
- reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/la_test1/verify.log b/verilog/dv/la_test1/verify.log
deleted file mode 100644
index f166328..0000000
--- a/verilog/dv/la_test1/verify.log
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile:30: /verilog/dv/make/sim.makefile: No such file or directory
-make: *** No rule to make target '/verilog/dv/make/sim.makefile'. Stop.
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/la_test2/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
deleted file mode 100644
index 25fad48..0000000
--- a/verilog/dv/la_test2/la_test2.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-/*
- MPRJ LA Test:
- - Sets counter clk through LA[64]
- - Sets counter rst through LA[65]
- - Observes count value for five clk cycle through LA[31:0]
-*/
-
-int clk = 0;
-int i;
-
-void main()
-{
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- reg_spi_enable = 1;
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
-
- // All GPIO pins are configured to be output
- // Used to flad the start/end of a test
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Configure All LA probes as inputs to the cpu
- reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB600000;
-
- // Configure LA[64] LA[65] as outputs from the cpu
- reg_la2_oenb = reg_la2_iena = 0x00000003;
-
- // Set clk & reset to one
- reg_la2_data = 0x00000003;
-
- // DELAY
- for (i=0; i<5; i=i+1) {}
-
- // Toggle clk & de-assert reset
- for (i=0; i<11; i=i+1) {
- clk = !clk;
- reg_la2_data = 0x00000000 | clk;
- }
-
- // reg_mprj_datal = 0xAB610000;
-
- while (1){
- if (reg_la0_data_in >= 0x05) {
- reg_mprj_datal = 0xAB610000;
- break;
- }
-
- }
-
-}
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
deleted file mode 100644
index fff3b72..0000000
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module la_test2_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
- always #15 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
-
- `ifdef ENABLE_SDF
- initial begin
- $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
- $sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
- // these breaks the simulation
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
- $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
- $sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
- $sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
- $sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
- $sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
- $sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
- $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
- end
- `endif
-
- initial begin
- $dumpfile("la_test2.vcd");
- $dumpvars(0, la_test2_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (75) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB60);
- $display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
- wait(checkbits == 16'hAB61);
- $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #3_000_000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
- power1 <= 1'b1;
- #100;
- power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("la_test2.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(),
- .io3()
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/la_test2/verify.log b/verilog/dv/la_test2/verify.log
deleted file mode 100644
index f166328..0000000
--- a/verilog/dv/la_test2/verify.log
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile:30: /verilog/dv/make/sim.makefile: No such file or directory
-make: *** No rule to make target '/verilog/dv/make/sim.makefile'. Stop.
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/mprj_stimulus/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
deleted file mode 100644
index 55aed98..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-
-// --------------------------------------------------------
-
-void main()
-{
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flag the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
-
- uint32_t testval;
-
- reg_mprj_datal = 0x00000000;
- reg_mprj_datah = 0x00000000;
-
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
- // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- /* TEST: Recast channels 35 to 32 to allow input to user project */
- /* This is done locally only: Do not run reg_mprj_xfer! */
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0x00000000;
-
- reg_mprj_datal = 0xAB410000;
- reg_mprj_datah = 0x00000000;
-
- // Test ability to force data on channel 37
- // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
-
- reg_mprj_datah = 0x0f0f0fc0;
- reg_mprj_datah = 0x00000000;
- reg_mprj_datah = 0x0f0f0fca;
- reg_mprj_datah = 0x0000000a;
- reg_mprj_datah = 0x0f0f0fc0;
- reg_mprj_datah = 0x00000000;
- reg_mprj_datah = 0x0f0f0fc5;
- reg_mprj_datah = 0x00000005;
-
- // Test ability to read back data generated by the user project
- // on the "monitored" outputs. Read from the lower 16 bits and
- // copy the value to the upper 16 bits.
-
- testval = reg_mprj_datal;
- reg_mprj_datal = (testval << 16);
- testval = reg_mprj_datal;
- reg_mprj_datal = (testval << 16);
-
- // Flag end of the test
- reg_mprj_datal = 0xAB510000;
-}
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
deleted file mode 100644
index e44d5a2..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype wire
-
-`timescale 1 ns / 1 ps
-
-module mprj_stimulus_tb;
- // Signals declaration
- reg clock;
- reg RSTB;
- reg power1, power2;
- reg CSB;
- wire gpio;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
- wire [3:0] status;
-
- // Signals Assignment
- assign checkbits = mprj_io[31:16];
- assign status = mprj_io[35:32];
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- `ifdef ENABLE_SDF
- initial begin
- $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
- $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
- $sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
- $sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
- $sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
- $sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
- $sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
- $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
- end
- `endif
-
- initial begin
- $dumpfile("mprj_stimulus.vcd");
- $dumpvars(0, mprj_stimulus_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (100) begin
- repeat (1000) @(posedge clock);
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB40);
- $display("Monitor: mprj_stimulus test started");
- wait(status == 4'ha);
- wait(status == 4'h5);
-
- // Values reflect copying user-controlled outputs to memory and back
- // to management-controlled outputs.
- wait(checkbits == 16'h1968 || checkbits == 16'h1969 || checkbits == 16'h198B); // They're off because the difference between GL and RTL
- wait(checkbits == 16'h1DCD || checkbits == 16'h1DCE || checkbits == 16'h1DE8); // They're off because the difference between GL and RTL
-
- wait(checkbits == 16'hAB51);
- $display("Monitor: mprj_stimulus test Passed");
- #10000;
- $finish;
- end
-
- // Reset Operation
- initial begin
- CSB <= 1'b1;
- RSTB <= 1'b0;
- #2000;
- RSTB <= 1'b1; // Release reset
- #1_300_000;
- CSB <= 1'b0; // Stop driving CSB
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
-
- spiflash #(
- .FILENAME("mprj_stimulus.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/mprj_stimulus/verify.log b/verilog/dv/mprj_stimulus/verify.log
deleted file mode 100644
index f166328..0000000
--- a/verilog/dv/mprj_stimulus/verify.log
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile:30: /verilog/dv/make/sim.makefile: No such file or directory
-make: *** No rule to make target '/verilog/dv/make/sim.makefile'. Stop.
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/wb_port/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/wb_port/verify.log b/verilog/dv/wb_port/verify.log
deleted file mode 100644
index f166328..0000000
--- a/verilog/dv/wb_port/verify.log
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile:30: /verilog/dv/make/sim.makefile: No such file or directory
-make: *** No rule to make target '/verilog/dv/make/sim.makefile'. Stop.
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
deleted file mode 100644
index c9c6996..0000000
--- a/verilog/dv/wb_port/wb_port.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
-
-/*
- Wishbone Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Checks counter value through the wishbone port
-*/
-
-void main()
-{
-
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- reg_spi_enable = 1;
- reg_wb_enable = 1;
- // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB600000;
-
- reg_mprj_slave = 0x00002710;
- reg_mprj_datal = 0xAB610000;
- if (reg_mprj_slave == 0x2B3D) {
- reg_mprj_datal = 0xAB610000;
- }
-}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
deleted file mode 100644
index 26ff469..0000000
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module wb_port_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
-
- assign mprj_io[3] = 1'b1;
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- `ifdef ENABLE_SDF
- initial begin
- $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
- $sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
- $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
- $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
- $sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
- $sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
- $sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
- $sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
- $sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
- $sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
- $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
- $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
- end
- `endif
-
- initial begin
- $dumpfile("wb_port.vcd");
- $dumpvars(0, wb_port_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (70) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB60);
- $display("Monitor: MPRJ-Logic WB Started");
- wait(checkbits == 16'hAB61);
- `ifdef GL
- $display("Monitor: Mega-Project WB (GL) Passed");
- `else
- $display("Monitor: Mega-Project WB (RTL) Passed");
- `endif
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #100000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("wb_port.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
