blob: 9f71af5bd70b92f44931c50d7416e301700ade29 [file] [log] [blame]
# Copyright 2020-2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
set_global_connections
set secondary []
foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
if { $vdd != $::env(VDD_NET)} {
lappend secondary $vdd
set db_net [[ord::get_db_block] findNet $vdd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $vdd]
$net setSpecial
$net setSigType "POWER"
}
}
if { $gnd != $::env(GND_NET)} {
lappend secondary $gnd
set db_net [[ord::get_db_block] findNet $gnd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $gnd]
$net setSpecial
$net setSigType "GROUND"
}
}
}
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
-secondary_power $secondary
# Assesses whether the design is the core of the chip or not based on the
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
if { $::env(DESIGN_IS_CORE) == 1 } {
# Used if the design is the core of the chip
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_LOWER_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring \
-nets "$::env(VDD_PIN) $::env(GND_PIN)"
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_UPPER_LAYER) \
-width $::env(FP_PDN_HWIDTH) \
-pitch $::env(FP_PDN_HPITCH) \
-offset $::env(FP_PDN_HOFFSET) \
-spacing $::env(FP_PDN_HSPACING) \
-starts_with POWER -extend_to_core_ring \
-nets "$::env(VDD_PIN) $::env(GND_PIN)"
add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
} else {
# Used if the design is a macro in the core
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins $::env(FP_PDN_LOWER_LAYER)
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_LOWER_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-starts_with POWER
}
# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_RAILS_LAYER) \
-width $::env(FP_PDN_RAIL_WIDTH) \
-followpins \
-starts_with POWER
add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
}
# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
add_pdn_ring \
-grid stdcell_grid \
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
-widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
}
define_pdn_grid \
-macro \
-default \
-name macro \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
add_pdn_connect \
-grid macro \
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"