| Jeff DiCorpo | 3e3b3f3 | 2023-03-24 15:55:35 -0700 | [diff] [blame^] | 1 | Project Chip ID is: 566208 |
| 2 | Setting Project Chip ID to: 0008a3c0 | ||||
| 3 | Step 1: Modify Layout of the user_id_programming subcell | ||||
| 4 | Done! | ||||
| 5 | Step 2: Add user project ID parameter to source verilog. | ||||
| 6 | Done! | ||||
| 7 | Step 3: Add user project ID parameter to gate-level verilog. | ||||
| 8 | Done! | ||||
| 9 | Step 4: Add user project ID text to top level layout. | ||||
| 10 | Done! | ||||